include/asm-arm/arch-at91rm9200/at91_pio.h

   1 /*
   2  * include/asm-arm/arch-at91rm9200/at91_pio.h
   3  *
   4  * Copyright (C) 2005 Ivan Kokshaysky
   5  * Copyright (C) SAN People
   6  *
   7  * Parallel I/O Controller (PIO) - System peripherals registers.
   8  * Based on AT91RM9200 datasheet revision E.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  */
  15
  16 #ifndef AT91_PIO_H
  17 #define AT91_PIO_H
  18
  19 #define PIO_PER         0x00    /* Enable Register */
  20 #define PIO_PDR         0x04    /* Disable Register */
  21 #define PIO_PSR         0x08    /* Status Register */
  22 #define PIO_OER         0x10    /* Output Enable Register */
  23 #define PIO_ODR         0x14    /* Output Disable Register */
  24 #define PIO_OSR         0x18    /* Output Status Register */
  25 #define PIO_IFER        0x20    /* Glitch Input Filter Enable */
  26 #define PIO_IFDR        0x24    /* Glitch Input Filter Disable */
  27 #define PIO_IFSR        0x28    /* Glitch Input Filter Status */
  28 #define PIO_SODR        0x30    /* Set Output Data Register */
  29 #define PIO_CODR        0x34    /* Clear Output Data Register */
  30 #define PIO_ODSR        0x38    /* Output Data Status Register */
  31 #define PIO_PDSR        0x3c    /* Pin Data Status Register */
  32 #define PIO_IER         0x40    /* Interrupt Enable Register */
  33 #define PIO_IDR         0x44    /* Interrupt Disable Register */
  34 #define PIO_IMR         0x48    /* Interrupt Mask Register */
  35 #define PIO_ISR         0x4c    /* Interrupt Status Register */
  36 #define PIO_MDER        0x50    /* Multi-driver Enable Register */
  37 #define PIO_MDDR        0x54    /* Multi-driver Disable Register */
  38 #define PIO_MDSR        0x58    /* Multi-driver Status Register */
  39 #define PIO_PUDR        0x60    /* Pull-up Disable Register */
  40 #define PIO_PUER        0x64    /* Pull-up Enable Register */
  41 #define PIO_PUSR        0x68    /* Pull-up Status Register */
  42 #define PIO_ASR         0x70    /* Peripheral A Select Register */
  43 #define PIO_BSR         0x74    /* Peripheral B Select Register */
  44 #define PIO_ABSR        0x78    /* AB Status Register */
  45 #define PIO_OWER        0xa0    /* Output Write Enable Register */
  46 #define PIO_OWDR        0xa4    /* Output Write Disable Register */
  47 #define PIO_OWSR        0xa8    /* Output Write Status Register */
  48
  49 #endif