include/asm-arm/arch-at91rm9200/at91_st.h

   1 /*
   2  * include/asm-arm/arch-at91rm9200/at91_st.h
   3  *
   4  * Copyright (C) 2005 Ivan Kokshaysky
   5  * Copyright (C) SAN People
   6  *
   7  * System Timer (ST) - System peripherals registers.
   8  * Based on AT91RM9200 datasheet revision E.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  */
  15
  16 #ifndef AT91_ST_H
  17 #define AT91_ST_H
  18
  19 #define AT91_ST_CR              (AT91_ST + 0x00)        /* Control Register */
  20 #define         AT91_ST_WDRST           (1 << 0)                /* Watchdog Timer Restart */
  21
  22 #define AT91_ST_PIMR            (AT91_ST + 0x04)        /* Period Interval Mode Register */
  23 #define         AT91_ST_PIV             (0xffff <<  0)          /* Period Interval Value */
  24
  25 #define AT91_ST_WDMR            (AT91_ST + 0x08)        /* Watchdog Mode Register */
  26 #define         AT91_ST_WDV             (0xffff <<  0)          /* Watchdog Counter Value */
  27 #define         AT91_ST_RSTEN           (1      << 16)          /* Reset Enable */
  28 #define         AT91_ST_EXTEN           (1      << 17)          /* External Signal Assertion Enable */
  29
  30 #define AT91_ST_RTMR            (AT91_ST + 0x0c)        /* Real-time Mode Register */
  31 #define         AT91_ST_RTPRES          (0xffff <<  0)          /* Real-time Prescalar Value */
  32
  33 #define AT91_ST_SR              (AT91_ST + 0x10)        /* Status Register */
  34 #define         AT91_ST_PITS            (1 << 0)                /* Period Interval Timer Status */
  35 #define         AT91_ST_WDOVF           (1 << 1)                /* Watchdog Overflow */
  36 #define         AT91_ST_RTTINC          (1 << 2)                /* Real-time Timer Increment */
  37 #define         AT91_ST_ALMS            (1 << 3)                /* Alarm Status */
  38
  39 #define AT91_ST_IER             (AT91_ST + 0x14)        /* Interrupt Enable Register */
  40 #define AT91_ST_IDR             (AT91_ST + 0x18)        /* Interrupt Disable Register */
  41 #define AT91_ST_IMR             (AT91_ST + 0x1c)        /* Interrupt Mask Register */
  42
  43 #define AT91_ST_RTAR            (AT91_ST + 0x20)        /* Real-time Alarm Register */
  44 #define         AT91_ST_ALMV            (0xfffff << 0)          /* Alarm Value */
  45
  46 #define AT91_ST_CRTR            (AT91_ST + 0x24)        /* Current Real-time Register */
  47 #define         AT91_ST_CRTV            (0xfffff << 0)          /* Current Real-Time Value */
  48
  49 #endif