include/asm-arm/arch-s3c2410/dma.h

   1 /* linux/include/asm-arm/arch-s3c2410/dma.h
   2  *
   3  * Copyright (C) 2003,2004,2006 Simtec Electronics
   4  *      Ben Dooks <ben@simtec.co.uk>
   5  *
   6  * Samsung S3C241XX DMA support
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11 */
  12
  13 #ifndef __ASM_ARCH_DMA_H
  14 #define __ASM_ARCH_DMA_H __FILE__
  15
  16 #include <linux/sysdev.h>
  17 #include <asm/hardware.h>
  18
  19 /*
  20  * This is the maximum DMA address(physical address) that can be DMAd to.
  21  *
  22  */
  23 #define MAX_DMA_ADDRESS         0x40000000
  24 #define MAX_DMA_TRANSFER_SIZE   0x100000 /* Data Unit is half word  */
  25
  26 /* We use `virtual` dma channels to hide the fact we have only a limited
  27  * number of DMA channels, and not of all of them (dependant on the device)
  28  * can be attached to any DMA source. We therefore let the DMA core handle
  29  * the allocation of hardware channels to clients.
  30 */
  31
  32 enum dma_ch {
  33         DMACH_XD0,
  34         DMACH_XD1,
  35         DMACH_SDI,
  36         DMACH_SPI0,
  37         DMACH_SPI1,
  38         DMACH_UART0,
  39         DMACH_UART1,
  40         DMACH_UART2,
  41         DMACH_TIMER,
  42         DMACH_I2S_IN,
  43         DMACH_I2S_OUT,
  44         DMACH_PCM_IN,
  45         DMACH_PCM_OUT,
  46         DMACH_MIC_IN,
  47         DMACH_USB_EP1,
  48         DMACH_USB_EP2,
  49         DMACH_USB_EP3,
  50         DMACH_USB_EP4,
  51         DMACH_UART0_SRC2,       /* s3c2412 second uart sources */
  52         DMACH_UART1_SRC2,
  53         DMACH_UART2_SRC2,
  54         DMACH_MAX,              /* the end entry */
  55 };
  56
  57 #define DMACH_LOW_LEVEL (1<<28) /* use this to specifiy hardware ch no */
  58
  59 /* we have 4 dma channels */
  60 #define S3C2410_DMA_CHANNELS        (4)
  61
  62 /* types */
  63
  64 enum s3c2410_dma_state {
  65         S3C2410_DMA_IDLE,
  66         S3C2410_DMA_RUNNING,
  67         S3C2410_DMA_PAUSED
  68 };
  69
  70
  71 /* enum s3c2410_dma_loadst
  72  *
  73  * This represents the state of the DMA engine, wrt to the loaded / running
  74  * transfers. Since we don't have any way of knowing exactly the state of
  75  * the DMA transfers, we need to know the state to make decisions on wether
  76  * we can
  77  *
  78  * S3C2410_DMA_NONE
  79  *
  80  * There are no buffers loaded (the channel should be inactive)
  81  *
  82  * S3C2410_DMA_1LOADED
  83  *
  84  * There is one buffer loaded, however it has not been confirmed to be
  85  * loaded by the DMA engine. This may be because the channel is not
  86  * yet running, or the DMA driver decided that it was too costly to
  87  * sit and wait for it to happen.
  88  *
  89  * S3C2410_DMA_1RUNNING
  90  *
  91  * The buffer has been confirmed running, and not finisged
  92  *
  93  * S3C2410_DMA_1LOADED_1RUNNING
  94  *
  95  * There is a buffer waiting to be loaded by the DMA engine, and one
  96  * currently running.
  97 */
  98
  99 enum s3c2410_dma_loadst {
 100         S3C2410_DMALOAD_NONE,
 101         S3C2410_DMALOAD_1LOADED,
 102         S3C2410_DMALOAD_1RUNNING,
 103         S3C2410_DMALOAD_1LOADED_1RUNNING,
 104 };
 105
 106 enum s3c2410_dma_buffresult {
 107         S3C2410_RES_OK,
 108         S3C2410_RES_ERR,
 109         S3C2410_RES_ABORT
 110 };
 111
 112 enum s3c2410_dmasrc {
 113         S3C2410_DMASRC_HW,              /* source is memory */
 114         S3C2410_DMASRC_MEM              /* source is hardware */
 115 };
 116
 117 /* enum s3c2410_chan_op
 118  *
 119  * operation codes passed to the DMA code by the user, and also used
 120  * to inform the current channel owner of any changes to the system state
 121 */
 122
 123 enum s3c2410_chan_op {
 124         S3C2410_DMAOP_START,
 125         S3C2410_DMAOP_STOP,
 126         S3C2410_DMAOP_PAUSE,
 127         S3C2410_DMAOP_RESUME,
 128         S3C2410_DMAOP_FLUSH,
 129         S3C2410_DMAOP_TIMEOUT,          /* internal signal to handler */
 130         S3C2410_DMAOP_STARTED,          /* indicate channel started */
 131 };
 132
 133 /* flags */
 134
 135 #define S3C2410_DMAF_SLOW         (1<<0)   /* slow, so don't worry about
 136                                             * waiting for reloads */
 137 #define S3C2410_DMAF_AUTOSTART    (1<<1)   /* auto-start if buffer queued */
 138
 139 /* dma buffer */
 140
 141 struct s3c2410_dma_client {
 142         char                *name;
 143 };
 144
 145 /* s3c2410_dma_buf_s
 146  *
 147  * internally used buffer structure to describe a queued or running
 148  * buffer.
 149 */
 150
 151 struct s3c2410_dma_buf;
 152 struct s3c2410_dma_buf {
 153         struct s3c2410_dma_buf  *next;
 154         int                      magic;         /* magic */
 155         int                      size;          /* buffer size in bytes */
 156         dma_addr_t               data;          /* start of DMA data */
 157         dma_addr_t               ptr;           /* where the DMA got to [1] */
 158         void                    *id;            /* client's id */
 159 };
 160
 161 /* [1] is this updated for both recv/send modes? */
 162
 163 struct s3c2410_dma_chan;
 164
 165 /* s3c2410_dma_cbfn_t
 166  *
 167  * buffer callback routine type
 168 */
 169
 170 typedef void (*s3c2410_dma_cbfn_t)(struct s3c2410_dma_chan *,
 171                                    void *buf, int size,
 172                                    enum s3c2410_dma_buffresult result);
 173
 174 typedef int  (*s3c2410_dma_opfn_t)(struct s3c2410_dma_chan *,
 175                                    enum s3c2410_chan_op );
 176
 177 struct s3c2410_dma_stats {
 178         unsigned long           loads;
 179         unsigned long           timeout_longest;
 180         unsigned long           timeout_shortest;
 181         unsigned long           timeout_avg;
 182         unsigned long           timeout_failed;
 183 };
 184
 185 struct s3c2410_dma_map;
 186
 187 /* struct s3c2410_dma_chan
 188  *
 189  * full state information for each DMA channel
 190 */
 191
 192 struct s3c2410_dma_chan {
 193         /* channel state flags and information */
 194         unsigned char            number;      /* number of this dma channel */
 195         unsigned char            in_use;      /* channel allocated */
 196         unsigned char            irq_claimed; /* irq claimed for channel */
 197         unsigned char            irq_enabled; /* irq enabled for channel */
 198         unsigned char            xfer_unit;   /* size of an transfer */
 199
 200         /* channel state */
 201
 202         enum s3c2410_dma_state   state;
 203         enum s3c2410_dma_loadst  load_state;
 204         struct s3c2410_dma_client *client;
 205
 206         /* channel configuration */
 207         enum s3c2410_dmasrc      source;
 208         unsigned long            dev_addr;
 209         unsigned long            load_timeout;
 210         unsigned int             flags;         /* channel flags */
 211
 212         struct s3c24xx_dma_map  *map;           /* channel hw maps */
 213
 214         /* channel's hardware position and configuration */
 215         void __iomem            *regs;          /* channels registers */
 216         void __iomem            *addr_reg;      /* data address register */
 217         unsigned int             irq;           /* channel irq */
 218         unsigned long            dcon;          /* default value of DCON */
 219
 220         /* driver handles */
 221         s3c2410_dma_cbfn_t       callback_fn;   /* buffer done callback */
 222         s3c2410_dma_opfn_t       op_fn;         /* channel op callback */
 223
 224         /* stats gathering */
 225         struct s3c2410_dma_stats *stats;
 226         struct s3c2410_dma_stats  stats_store;
 227
 228         /* buffer list and information */
 229         struct s3c2410_dma_buf  *curr;          /* current dma buffer */
 230         struct s3c2410_dma_buf  *next;          /* next buffer to load */
 231         struct s3c2410_dma_buf  *end;           /* end of queue */
 232
 233         /* system device */
 234         struct sys_device       dev;
 235 };
 236
 237 /* the currently allocated channel information */
 238 extern struct s3c2410_dma_chan s3c2410_chans[];
 239
 240 /* note, we don't really use dma_device_t at the moment */
 241 typedef unsigned long dma_device_t;
 242
 243 /* functions --------------------------------------------------------------- */
 244
 245 /* s3c2410_dma_request
 246  *
 247  * request a dma channel exclusivley
 248 */
 249
 250 extern int s3c2410_dma_request(dmach_t channel,
 251                                struct s3c2410_dma_client *, void *dev);
 252
 253
 254 /* s3c2410_dma_ctrl
 255  *
 256  * change the state of the dma channel
 257 */
 258
 259 extern int s3c2410_dma_ctrl(dmach_t channel, enum s3c2410_chan_op op);
 260
 261 /* s3c2410_dma_setflags
 262  *
 263  * set the channel's flags to a given state
 264 */
 265
 266 extern int s3c2410_dma_setflags(dmach_t channel,
 267                                 unsigned int flags);
 268
 269 /* s3c2410_dma_free
 270  *
 271  * free the dma channel (will also abort any outstanding operations)
 272 */
 273
 274 extern int s3c2410_dma_free(dmach_t channel, struct s3c2410_dma_client *);
 275
 276 /* s3c2410_dma_enqueue
 277  *
 278  * place the given buffer onto the queue of operations for the channel.
 279  * The buffer must be allocated from dma coherent memory, or the Dcache/WB
 280  * drained before the buffer is given to the DMA system.
 281 */
 282
 283 extern int s3c2410_dma_enqueue(dmach_t channel, void *id,
 284                                dma_addr_t data, int size);
 285
 286 /* s3c2410_dma_config
 287  *
 288  * configure the dma channel
 289 */
 290
 291 extern int s3c2410_dma_config(dmach_t channel, int xferunit, int dcon);
 292
 293 /* s3c2410_dma_devconfig
 294  *
 295  * configure the device we're talking to
 296 */
 297
 298 extern int s3c2410_dma_devconfig(int channel, enum s3c2410_dmasrc source,
 299                                  int hwcfg, unsigned long devaddr);
 300
 301 /* s3c2410_dma_getposition
 302  *
 303  * get the position that the dma transfer is currently at
 304 */
 305
 306 extern int s3c2410_dma_getposition(dmach_t channel,
 307                                    dma_addr_t *src, dma_addr_t *dest);
 308
 309 extern int s3c2410_dma_set_opfn(dmach_t, s3c2410_dma_opfn_t rtn);
 310 extern int s3c2410_dma_set_buffdone_fn(dmach_t, s3c2410_dma_cbfn_t rtn);
 311
 312 /* DMA Register definitions */
 313
 314 #define S3C2410_DMA_DISRC       (0x00)
 315 #define S3C2410_DMA_DISRCC      (0x04)
 316 #define S3C2410_DMA_DIDST       (0x08)
 317 #define S3C2410_DMA_DIDSTC      (0x0C)
 318 #define S3C2410_DMA_DCON        (0x10)
 319 #define S3C2410_DMA_DSTAT       (0x14)
 320 #define S3C2410_DMA_DCSRC       (0x18)
 321 #define S3C2410_DMA_DCDST       (0x1C)
 322 #define S3C2410_DMA_DMASKTRIG   (0x20)
 323 #define S3C2412_DMA_DMAREQSEL   (0x24)
 324
 325 #define S3C2410_DISRCC_INC      (1<<0)
 326 #define S3C2410_DISRCC_APB      (1<<1)
 327
 328 #define S3C2410_DMASKTRIG_STOP   (1<<2)
 329 #define S3C2410_DMASKTRIG_ON     (1<<1)
 330 #define S3C2410_DMASKTRIG_SWTRIG (1<<0)
 331
 332 #define S3C2410_DCON_DEMAND     (0<<31)
 333 #define S3C2410_DCON_HANDSHAKE  (1<<31)
 334 #define S3C2410_DCON_SYNC_PCLK  (0<<30)
 335 #define S3C2410_DCON_SYNC_HCLK  (1<<30)
 336
 337 #define S3C2410_DCON_INTREQ     (1<<29)
 338
 339 #define S3C2410_DCON_CH0_XDREQ0 (0<<24)
 340 #define S3C2410_DCON_CH0_UART0  (1<<24)
 341 #define S3C2410_DCON_CH0_SDI    (2<<24)
 342 #define S3C2410_DCON_CH0_TIMER  (3<<24)
 343 #define S3C2410_DCON_CH0_USBEP1 (4<<24)
 344
 345 #define S3C2410_DCON_CH1_XDREQ1 (0<<24)
 346 #define S3C2410_DCON_CH1_UART1  (1<<24)
 347 #define S3C2410_DCON_CH1_I2SSDI (2<<24)
 348 #define S3C2410_DCON_CH1_SPI    (3<<24)
 349 #define S3C2410_DCON_CH1_USBEP2 (4<<24)
 350
 351 #define S3C2410_DCON_CH2_I2SSDO (0<<24)
 352 #define S3C2410_DCON_CH2_I2SSDI (1<<24)
 353 #define S3C2410_DCON_CH2_SDI    (2<<24)
 354 #define S3C2410_DCON_CH2_TIMER  (3<<24)
 355 #define S3C2410_DCON_CH2_USBEP3 (4<<24)
 356
 357 #define S3C2410_DCON_CH3_UART2  (0<<24)
 358 #define S3C2410_DCON_CH3_SDI    (1<<24)
 359 #define S3C2410_DCON_CH3_SPI    (2<<24)
 360 #define S3C2410_DCON_CH3_TIMER  (3<<24)
 361 #define S3C2410_DCON_CH3_USBEP4 (4<<24)
 362
 363 #define S3C2410_DCON_SRCSHIFT   (24)
 364 #define S3C2410_DCON_SRCMASK    (7<<24)
 365
 366 #define S3C2410_DCON_BYTE       (0<<20)
 367 #define S3C2410_DCON_HALFWORD   (1<<20)
 368 #define S3C2410_DCON_WORD       (2<<20)
 369
 370 #define S3C2410_DCON_AUTORELOAD (0<<22)
 371 #define S3C2410_DCON_NORELOAD   (1<<22)
 372 #define S3C2410_DCON_HWTRIG     (1<<23)
 373
 374 #ifdef CONFIG_CPU_S3C2440
 375 #define S3C2440_DIDSTC_CHKINT   (1<<2)
 376
 377 #define S3C2440_DCON_CH0_I2SSDO (5<<24)
 378 #define S3C2440_DCON_CH0_PCMIN  (6<<24)
 379
 380 #define S3C2440_DCON_CH1_PCMOUT (5<<24)
 381 #define S3C2440_DCON_CH1_SDI    (6<<24)
 382
 383 #define S3C2440_DCON_CH2_PCMIN  (5<<24)
 384 #define S3C2440_DCON_CH2_MICIN  (6<<24)
 385
 386 #define S3C2440_DCON_CH3_MICIN  (5<<24)
 387 #define S3C2440_DCON_CH3_PCMOUT (6<<24)
 388 #endif
 389
 390 #ifdef CONFIG_CPU_S3C2412
 391
 392 #define S3C2412_DMAREQSEL_SRC(x)        ((x)<<1)
 393
 394 #define S3C2412_DMAREQSEL_HW            (1)
 395
 396 #define S3C2412_DMAREQSEL_SPI0TX        S3C2412_DMAREQSEL_SRC(0)
 397 #define S3C2412_DMAREQSEL_SPI0RX        S3C2412_DMAREQSEL_SRC(1)
 398 #define S3C2412_DMAREQSEL_SPI1TX        S3C2412_DMAREQSEL_SRC(2)
 399 #define S3C2412_DMAREQSEL_SPI1RX        S3C2412_DMAREQSEL_SRC(3)
 400 #define S3C2412_DMAREQSEL_I2STX         S3C2412_DMAREQSEL_SRC(4)
 401 #define S3C2412_DMAREQSEL_I2SRX         S3C2412_DMAREQSEL_SRC(5)
 402 #define S3C2412_DMAREQSEL_TIMER         S3C2412_DMAREQSEL_SRC(9)
 403 #define S3C2412_DMAREQSEL_SDI           S3C2412_DMAREQSEL_SRC(10)
 404 #define S3C2412_DMAREQSEL_USBEP1        S3C2412_DMAREQSEL_SRC(13)
 405 #define S3C2412_DMAREQSEL_USBEP2        S3C2412_DMAREQSEL_SRC(14)
 406 #define S3C2412_DMAREQSEL_USBEP3        S3C2412_DMAREQSEL_SRC(15)
 407 #define S3C2412_DMAREQSEL_USBEP4        S3C2412_DMAREQSEL_SRC(16)
 408 #define S3C2412_DMAREQSEL_XDREQ0        S3C2412_DMAREQSEL_SRC(17)
 409 #define S3C2412_DMAREQSEL_XDREQ1        S3C2412_DMAREQSEL_SRC(18)
 410 #define S3C2412_DMAREQSEL_UART0_0       S3C2412_DMAREQSEL_SRC(19)
 411 #define S3C2412_DMAREQSEL_UART0_1       S3C2412_DMAREQSEL_SRC(20)
 412 #define S3C2412_DMAREQSEL_UART1_0       S3C2412_DMAREQSEL_SRC(21)
 413 #define S3C2412_DMAREQSEL_UART1_1       S3C2412_DMAREQSEL_SRC(22)
 414 #define S3C2412_DMAREQSEL_UART2_0       S3C2412_DMAREQSEL_SRC(23)
 415 #define S3C2412_DMAREQSEL_UART2_1       S3C2412_DMAREQSEL_SRC(24)
 416
 417 #endif
 418 #endif /* __ASM_ARCH_DMA_H */