2 * include/asm-arm/arch-s3c2410/entry-macro.S
4 * Low-level IRQ helper macros for S3C2410-based platforms
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
11 /* We have a problem that the INTOFFSET register does not always
12 * show one interrupt. Occasionally we get two interrupts through
13 * the prioritiser, and this causes the INTOFFSET register to show
14 * what looks like the logical-or of the two interrupt numbers.
16 * Thanks to Klaus, Shannon, et al for helping to debug this problem
20 #define INTOFFSET (0x14)
22 #include <asm/hardware.h>
25 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
27 mov \base, #S3C24XX_VA_IRQ
29 @@ try the interrupt offset register, since it is there
31 ldr \irqstat, [ \base, #INTPND ]
34 ldr \irqnr, [ \base, #INTOFFSET ]
36 tst \irqstat, \tmp, lsl \irqnr
39 @@ the number specified is not a valid irq, so try
40 @@ and work it out for ourselves
42 mov \irqnr, #0 @@ start here
44 @@ work out which irq (if any) we got
46 movs \tmp, \irqstat, lsl#16
47 addeq \irqnr, \irqnr, #16
48 moveq \irqstat, \irqstat, lsr#16
50 addeq \irqnr, \irqnr, #8
51 moveq \irqstat, \irqstat, lsr#8
53 addeq \irqnr, \irqnr, #4
54 moveq \irqstat, \irqstat, lsr#4
56 addeq \irqnr, \irqnr, #2
57 moveq \irqstat, \irqstat, lsr#2
59 addeq \irqnr, \irqnr, #1
63 adds \irqnr, \irqnr, #IRQ_EINT0
65 @@ exit here, Z flag unset if IRQ
69 /* currently don't need an disable_fiq macro */