include/asm-arm/arch-s3c2410/regs-serial.h

   1 /* linux/include/asm-arm/arch-s3c2410/regs-serial.h
   2  *
   3  *  From linux/include/asm-arm/hardware/serial_s3c2410.h
   4  *
   5  *  Internal header file for Samsung S3C2410 serial ports (UART0-2)
   6  *
   7  *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
   8  *
   9  *  Additional defines, (c) 2003 Simtec Electronics (linux@simtec.co.uk)
  10  *
  11  *  Adapted from:
  12  *
  13  *  Internal header file for MX1ADS serial ports (UART1 & 2)
  14  *
  15  *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
  16  *
  17  * This program is free software; you can redistribute it and/or modify
  18  * it under the terms of the GNU General Public License as published by
  19  * the Free Software Foundation; either version 2 of the License, or
  20  * (at your option) any later version.
  21  *
  22  * This program is distributed in the hope that it will be useful,
  23  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  24  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  25  * GNU General Public License for more details.
  26  *
  27  * You should have received a copy of the GNU General Public License
  28  * along with this program; if not, write to the Free Software
  29  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  30 */
  31
  32 #ifndef __ASM_ARM_REGS_SERIAL_H
  33 #define __ASM_ARM_REGS_SERIAL_H
  34
  35 #define S3C24XX_VA_UART0      (S3C24XX_VA_UART)
  36 #define S3C24XX_VA_UART1      (S3C24XX_VA_UART + 0x4000 )
  37 #define S3C24XX_VA_UART2      (S3C24XX_VA_UART + 0x8000 )
  38
  39 #define S3C2410_PA_UART0      (S3C24XX_PA_UART)
  40 #define S3C2410_PA_UART1      (S3C24XX_PA_UART + 0x4000 )
  41 #define S3C2410_PA_UART2      (S3C24XX_PA_UART + 0x8000 )
  42
  43 #define S3C2410_URXH      (0x24)
  44 #define S3C2410_UTXH      (0x20)
  45 #define S3C2410_ULCON     (0x00)
  46 #define S3C2410_UCON      (0x04)
  47 #define S3C2410_UFCON     (0x08)
  48 #define S3C2410_UMCON     (0x0C)
  49 #define S3C2410_UBRDIV    (0x28)
  50 #define S3C2410_UTRSTAT   (0x10)
  51 #define S3C2410_UERSTAT   (0x14)
  52 #define S3C2410_UFSTAT    (0x18)
  53 #define S3C2410_UMSTAT    (0x1C)
  54
  55 #define S3C2410_LCON_CFGMASK      ((0xF<<3)|(0x3))
  56
  57 #define S3C2410_LCON_CS5          (0x0)
  58 #define S3C2410_LCON_CS6          (0x1)
  59 #define S3C2410_LCON_CS7          (0x2)
  60 #define S3C2410_LCON_CS8          (0x3)
  61 #define S3C2410_LCON_CSMASK       (0x3)
  62
  63 #define S3C2410_LCON_PNONE        (0x0)
  64 #define S3C2410_LCON_PEVEN        (0x5 << 3)
  65 #define S3C2410_LCON_PODD         (0x4 << 3)
  66 #define S3C2410_LCON_PMASK        (0x7 << 3)
  67
  68 #define S3C2410_LCON_STOPB        (1<<2)
  69 #define S3C2410_LCON_IRM          (1<<6)
  70
  71 #define S3C2440_UCON_CLKMASK      (3<<10)
  72 #define S3C2440_UCON_PCLK         (0<<10)
  73 #define S3C2440_UCON_UCLK         (1<<10)
  74 #define S3C2440_UCON_PCLK2        (2<<10)
  75 #define S3C2440_UCON_FCLK         (3<<10)
  76 #define S3C2440_UCON2_FCLK_EN     (1<<15)
  77 #define S3C2440_UCON0_DIVMASK     (15 << 12)
  78 #define S3C2440_UCON1_DIVMASK     (15 << 12)
  79 #define S3C2440_UCON2_DIVMASK     (7 << 12)
  80 #define S3C2440_UCON_DIVSHIFT     (12)
  81
  82 #define S3C2412_UCON_CLKMASK    (3<<10)
  83 #define S3C2412_UCON_UCLK       (1<<10)
  84 #define S3C2412_UCON_USYSCLK    (3<<10)
  85 #define S3C2412_UCON_PCLK       (0<<10)
  86 #define S3C2412_UCON_PCLK2      (2<<10)
  87
  88 #define S3C2410_UCON_UCLK         (1<<10)
  89 #define S3C2410_UCON_SBREAK       (1<<4)
  90
  91 #define S3C2410_UCON_TXILEVEL     (1<<9)
  92 #define S3C2410_UCON_RXILEVEL     (1<<8)
  93 #define S3C2410_UCON_TXIRQMODE    (1<<2)
  94 #define S3C2410_UCON_RXIRQMODE    (1<<0)
  95 #define S3C2410_UCON_RXFIFO_TOI   (1<<7)
  96
  97 #define S3C2410_UCON_DEFAULT      (S3C2410_UCON_TXILEVEL  | \
  98                                    S3C2410_UCON_RXILEVEL  | \
  99                                    S3C2410_UCON_TXIRQMODE | \
 100                                    S3C2410_UCON_RXIRQMODE | \
 101                                    S3C2410_UCON_RXFIFO_TOI)
 102
 103 #define S3C2410_UFCON_FIFOMODE    (1<<0)
 104 #define S3C2410_UFCON_TXTRIG0     (0<<6)
 105 #define S3C2410_UFCON_RXTRIG8     (1<<4)
 106 #define S3C2410_UFCON_RXTRIG12    (2<<4)
 107
 108 /* S3C2440 FIFO trigger levels */
 109 #define S3C2440_UFCON_RXTRIG1     (0<<4)
 110 #define S3C2440_UFCON_RXTRIG8     (1<<4)
 111 #define S3C2440_UFCON_RXTRIG16    (2<<4)
 112 #define S3C2440_UFCON_RXTRIG32    (3<<4)
 113
 114 #define S3C2440_UFCON_TXTRIG0     (0<<6)
 115 #define S3C2440_UFCON_TXTRIG16    (1<<6)
 116 #define S3C2440_UFCON_TXTRIG32    (2<<6)
 117 #define S3C2440_UFCON_TXTRIG48    (3<<6)
 118
 119 #define S3C2410_UFCON_RESETBOTH   (3<<1)
 120 #define S3C2410_UFCON_RESETTX     (1<<2)
 121 #define S3C2410_UFCON_RESETRX     (1<<1)
 122
 123 #define S3C2410_UFCON_DEFAULT     (S3C2410_UFCON_FIFOMODE | \
 124                                    S3C2410_UFCON_TXTRIG0  | \
 125                                    S3C2410_UFCON_RXTRIG8 )
 126
 127 #define S3C2410_UMCOM_AFC         (1<<4)
 128 #define S3C2410_UMCOM_RTS_LOW     (1<<0)
 129
 130 #define S3C2412_UMCON_AFC_63    (0<<5)
 131 #define S3C2412_UMCON_AFC_56    (1<<5)
 132 #define S3C2412_UMCON_AFC_48    (2<<5)
 133 #define S3C2412_UMCON_AFC_40    (3<<5)
 134 #define S3C2412_UMCON_AFC_32    (4<<5)
 135 #define S3C2412_UMCON_AFC_24    (5<<5)
 136 #define S3C2412_UMCON_AFC_16    (6<<5)
 137 #define S3C2412_UMCON_AFC_8     (7<<5)
 138
 139 #define S3C2410_UFSTAT_TXFULL     (1<<9)
 140 #define S3C2410_UFSTAT_RXFULL     (1<<8)
 141 #define S3C2410_UFSTAT_TXMASK     (15<<4)
 142 #define S3C2410_UFSTAT_TXSHIFT    (4)
 143 #define S3C2410_UFSTAT_RXMASK     (15<<0)
 144 #define S3C2410_UFSTAT_RXSHIFT    (0)
 145
 146 #define S3C2440_UFSTAT_TXFULL     (1<<14)
 147 #define S3C2440_UFSTAT_RXFULL     (1<<6)
 148 #define S3C2440_UFSTAT_TXSHIFT    (8)
 149 #define S3C2440_UFSTAT_RXSHIFT    (0)
 150 #define S3C2440_UFSTAT_TXMASK     (63<<8)
 151 #define S3C2440_UFSTAT_RXMASK     (63)
 152
 153 #define S3C2410_UTRSTAT_TXE       (1<<2)
 154 #define S3C2410_UTRSTAT_TXFE      (1<<1)
 155 #define S3C2410_UTRSTAT_RXDR      (1<<0)
 156
 157 #define S3C2410_UERSTAT_OVERRUN   (1<<0)
 158 #define S3C2410_UERSTAT_FRAME     (1<<2)
 159 #define S3C2410_UERSTAT_BREAK     (1<<3)
 160 #define S3C2410_UERSTAT_ANY       (S3C2410_UERSTAT_OVERRUN | \
 161                                    S3C2410_UERSTAT_FRAME | \
 162                                    S3C2410_UERSTAT_BREAK)
 163
 164 #define S3C2410_UMSTAT_CTS        (1<<0)
 165 #define S3C2410_UMSTAT_DeltaCTS   (1<<2)
 166
 167 #ifndef __ASSEMBLY__
 168
 169 /* struct s3c24xx_uart_clksrc
 170  *
 171  * this structure defines a named clock source that can be used for the
 172  * uart, so that the best clock can be selected for the requested baud
 173  * rate.
 174  *
 175  * min_baud and max_baud define the range of baud-rates this clock is
 176  * acceptable for, if they are both zero, it is assumed any baud rate that
 177  * can be generated from this clock will be used.
 178  *
 179  * divisor gives the divisor from the clock to the one seen by the uart
 180 */
 181
 182 struct s3c24xx_uart_clksrc {
 183         const char      *name;
 184         unsigned int     divisor;
 185         unsigned int     min_baud;
 186         unsigned int     max_baud;
 187 };
 188
 189 /* configuration structure for per-machine configurations for the
 190  * serial port
 191  *
 192  * the pointer is setup by the machine specific initialisation from the
 193  * arch/arm/mach-s3c2410/ directory.
 194 */
 195
 196 struct s3c2410_uartcfg {
 197         unsigned char      hwport;       /* hardware port number */
 198         unsigned char      unused;
 199         unsigned short     flags;
 200         upf_t              uart_flags;   /* default uart flags */
 201
 202         unsigned long      ucon;         /* value of ucon for port */
 203         unsigned long      ulcon;        /* value of ulcon for port */
 204         unsigned long      ufcon;        /* value of ufcon for port */
 205
 206         struct s3c24xx_uart_clksrc *clocks;
 207         unsigned int                clocks_size;
 208 };
 209
 210 /* s3c24xx_uart_devs
 211  *
 212  * this is exported from the core as we cannot use driver_register(),
 213  * or platform_add_device() before the console_initcall()
 214 */
 215
 216 extern struct platform_device *s3c24xx_uart_devs[3];
 217
 218 #endif /* __ASSEMBLY__ */
 219
 220 #endif /* __ASM_ARM_REGS_SERIAL_H */
 221