include/asm-arm/arch-s3c2410/uncompress.h

   1 /* linux/include/asm-arm/arch-s3c2410/uncompress.h
   2  *
   3  * Copyright (c) 2003 Simtec Electronics
   4  *      Ben Dooks <ben@simtec.co.uk>
   5  *
   6  * S3C2410 - uncompress code
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11 */
  12
  13 #ifndef __ASM_ARCH_UNCOMPRESS_H
  14 #define __ASM_ARCH_UNCOMPRESS_H
  15
  16 typedef unsigned int upf_t;     /* cannot include linux/serial_core.h */
  17
  18 /* defines for UART registers */
  19 #include "asm/arch/regs-serial.h"
  20 #include "asm/arch/regs-gpio.h"
  21 #include "asm/arch/regs-watchdog.h"
  22
  23 #include <asm/arch/map.h>
  24
  25 /* working in physical space... */
  26 #undef S3C2410_GPIOREG
  27 #undef S3C2410_WDOGREG
  28
  29 #define S3C2410_GPIOREG(x) ((S3C24XX_PA_GPIO + (x)))
  30 #define S3C2410_WDOGREG(x) ((S3C24XX_PA_WATCHDOG + (x)))
  31
  32 /* how many bytes we allow into the FIFO at a time in FIFO mode */
  33 #define FIFO_MAX         (14)
  34
  35 #define uart_base S3C24XX_PA_UART + (0x4000*CONFIG_S3C2410_LOWLEVEL_UART_PORT)
  36
  37 static __inline__ void
  38 uart_wr(unsigned int reg, unsigned int val)
  39 {
  40         volatile unsigned int *ptr;
  41
  42         ptr = (volatile unsigned int *)(reg + uart_base);
  43         *ptr = val;
  44 }
  45
  46 static __inline__ unsigned int
  47 uart_rd(unsigned int reg)
  48 {
  49         volatile unsigned int *ptr;
  50
  51         ptr = (volatile unsigned int *)(reg + uart_base);
  52         return *ptr;
  53 }
  54
  55
  56 /* we can deal with the case the UARTs are being run
  57  * in FIFO mode, so that we don't hold up our execution
  58  * waiting for tx to happen...
  59 */
  60
  61 static void putc(int ch)
  62 {
  63         int cpuid = S3C2410_GSTATUS1_2410;
  64
  65 #ifndef CONFIG_CPU_S3C2400
  66         cpuid = *((volatile unsigned int *)S3C2410_GSTATUS1);
  67         cpuid &= S3C2410_GSTATUS1_IDMASK;
  68 #endif
  69
  70         if (uart_rd(S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE) {
  71                 int level;
  72
  73                 while (1) {
  74                         level = uart_rd(S3C2410_UFSTAT);
  75
  76                         if (cpuid == S3C2410_GSTATUS1_2440 ||
  77                             cpuid == S3C2410_GSTATUS1_2442) {
  78                                 level &= S3C2440_UFSTAT_TXMASK;
  79                                 level >>= S3C2440_UFSTAT_TXSHIFT;
  80                         } else {
  81                                 level &= S3C2410_UFSTAT_TXMASK;
  82                                 level >>= S3C2410_UFSTAT_TXSHIFT;
  83                         }
  84
  85                         if (level < FIFO_MAX)
  86                                 break;
  87                 }
  88
  89         } else {
  90                 /* not using fifos */
  91
  92                 while ((uart_rd(S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE) != S3C2410_UTRSTAT_TXE)
  93                         barrier();
  94         }
  95
  96         /* write byte to transmission register */
  97         uart_wr(S3C2410_UTXH, ch);
  98 }
  99
 100 static inline void flush(void)
 101 {
 102 }
 103
 104 #define __raw_writel(d,ad) do { *((volatile unsigned int *)(ad)) = (d); } while(0)
 105
 106 /* CONFIG_S3C2410_BOOT_WATCHDOG
 107  *
 108  * Simple boot-time watchdog setup, to reboot the system if there is
 109  * any problem with the boot process
 110 */
 111
 112 #ifdef CONFIG_S3C2410_BOOT_WATCHDOG
 113
 114 #define WDOG_COUNT (0xff00)
 115
 116 static inline void arch_decomp_wdog(void)
 117 {
 118         __raw_writel(WDOG_COUNT, S3C2410_WTCNT);
 119 }
 120
 121 static void arch_decomp_wdog_start(void)
 122 {
 123         __raw_writel(WDOG_COUNT, S3C2410_WTDAT);
 124         __raw_writel(WDOG_COUNT, S3C2410_WTCNT);
 125         __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x80), S3C2410_WTCON);
 126 }
 127
 128 #else
 129 #define arch_decomp_wdog_start()
 130 #define arch_decomp_wdog()
 131 #endif
 132
 133 #ifdef CONFIG_S3C2410_BOOT_ERROR_RESET
 134
 135 static void arch_decomp_error(const char *x)
 136 {
 137         putstr("\n\n");
 138         putstr(x);
 139         putstr("\n\n -- System resetting\n");
 140
 141         __raw_writel(0x4000, S3C2410_WTDAT);
 142         __raw_writel(0x4000, S3C2410_WTCNT);
 143         __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x40), S3C2410_WTCON);
 144
 145         while(1);
 146 }
 147
 148 #define arch_error arch_decomp_error
 149 #endif
 150
 151 static void error(char *err);
 152
 153 static void
 154 arch_decomp_setup(void)
 155 {
 156         /* we may need to setup the uart(s) here if we are not running
 157          * on an BAST... the BAST will have left the uarts configured
 158          * after calling linux.
 159          */
 160
 161         arch_decomp_wdog_start();
 162 }
 163
 164
 165 #endif /* __ASM_ARCH_UNCOMPRESS_H */