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staging: erofs: integrate decompression inplace
[linux/fpc-iii.git] / drivers / tty / serial / 8250 / 8250_omap.c
blob0a8316632d751563ef12fe6b74c69a0570286f97
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * 8250-core based driver for the OMAP internal UART
4 *
5 * based on omap-serial.c, Copyright (C) 2010 Texas Instruments.
6 *
7 * Copyright (C) 2014 Sebastian Andrzej Siewior
8 *
9 */
10
11 #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
12 #define SUPPORT_SYSRQ
13 #endif
14
15 #include <linux/clk.h>
16 #include <linux/device.h>
17 #include <linux/io.h>
18 #include <linux/module.h>
19 #include <linux/serial_8250.h>
20 #include <linux/serial_reg.h>
21 #include <linux/tty_flip.h>
22 #include <linux/platform_device.h>
23 #include <linux/slab.h>
24 #include <linux/of.h>
25 #include <linux/of_device.h>
26 #include <linux/of_gpio.h>
27 #include <linux/of_irq.h>
28 #include <linux/delay.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/console.h>
31 #include <linux/pm_qos.h>
32 #include <linux/pm_wakeirq.h>
33 #include <linux/dma-mapping.h>
34
35 #include "8250.h"
36
37 #define DEFAULT_CLK_SPEED 48000000
38
39 #define UART_ERRATA_i202_MDR1_ACCESS (1 << 0)
40 #define OMAP_UART_WER_HAS_TX_WAKEUP (1 << 1)
41 #define OMAP_DMA_TX_KICK (1 << 2)
42 /*
43 * See Advisory 21 in AM437x errata SPRZ408B, updated April 2015.
44 * The same errata is applicable to AM335x and DRA7x processors too.
45 */
46 #define UART_ERRATA_CLOCK_DISABLE (1 << 3)
47
48 #define OMAP_UART_FCR_RX_TRIG 6
49 #define OMAP_UART_FCR_TX_TRIG 4
50
51 /* SCR register bitmasks */
52 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7)
53 #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6)
54 #define OMAP_UART_SCR_TX_EMPTY (1 << 3)
55 #define OMAP_UART_SCR_DMAMODE_MASK (3 << 1)
56 #define OMAP_UART_SCR_DMAMODE_1 (1 << 1)
57 #define OMAP_UART_SCR_DMAMODE_CTL (1 << 0)
58
59 /* MVR register bitmasks */
60 #define OMAP_UART_MVR_SCHEME_SHIFT 30
61 #define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0
62 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4
63 #define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f
64 #define OMAP_UART_MVR_MAJ_MASK 0x700
65 #define OMAP_UART_MVR_MAJ_SHIFT 8
66 #define OMAP_UART_MVR_MIN_MASK 0x3f
67
68 /* SYSC register bitmasks */
69 #define OMAP_UART_SYSC_SOFTRESET (1 << 1)
70
71 /* SYSS register bitmasks */
72 #define OMAP_UART_SYSS_RESETDONE (1 << 0)
73
74 #define UART_TI752_TLR_TX 0
75 #define UART_TI752_TLR_RX 4
76
77 #define TRIGGER_TLR_MASK(x) ((x & 0x3c) >> 2)
78 #define TRIGGER_FCR_MASK(x) (x & 3)
79
80 /* Enable XON/XOFF flow control on output */
81 #define OMAP_UART_SW_TX 0x08
82 /* Enable XON/XOFF flow control on input */
83 #define OMAP_UART_SW_RX 0x02
84
85 #define OMAP_UART_WER_MOD_WKUP 0x7f
86 #define OMAP_UART_TX_WAKEUP_EN (1 << 7)
87
88 #define TX_TRIGGER 1
89 #define RX_TRIGGER 48
90
91 #define OMAP_UART_TCR_RESTORE(x) ((x / 4) << 4)
92 #define OMAP_UART_TCR_HALT(x) ((x / 4) << 0)
93
94 #define UART_BUILD_REVISION(x, y) (((x) << 8) | (y))
95
96 #define OMAP_UART_REV_46 0x0406
97 #define OMAP_UART_REV_52 0x0502
98 #define OMAP_UART_REV_63 0x0603
99
100 struct omap8250_priv {
101 int line;
102 u8 habit;
103 u8 mdr1;
104 u8 efr;
105 u8 scr;
106 u8 wer;
107 u8 xon;
108 u8 xoff;
109 u8 delayed_restore;
110 u16 quot;
111
112 bool is_suspending;
113 int wakeirq;
114 int wakeups_enabled;
115 u32 latency;
116 u32 calc_latency;
117 struct pm_qos_request pm_qos_request;
118 struct work_struct qos_work;
119 struct uart_8250_dma omap8250_dma;
120 spinlock_t rx_dma_lock;
121 bool rx_dma_broken;
122 bool throttled;
123 };
124
125 #ifdef CONFIG_SERIAL_8250_DMA
126 static void omap_8250_rx_dma_flush(struct uart_8250_port *p);
127 #else
128 static inline void omap_8250_rx_dma_flush(struct uart_8250_port *p) { }
129 #endif
130
131 static u32 uart_read(struct uart_8250_port *up, u32 reg)
132 {
133 return readl(up->port.membase + (reg << up->port.regshift));
134 }
135
136 static void omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
137 {
138 struct uart_8250_port *up = up_to_u8250p(port);
139 struct omap8250_priv *priv = up->port.private_data;
140 u8 lcr;
141
142 serial8250_do_set_mctrl(port, mctrl);
143
144 /*
145 * Turn off autoRTS if RTS is lowered and restore autoRTS setting
146 * if RTS is raised
147 */
148 lcr = serial_in(up, UART_LCR);
149 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
150 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))
151 priv->efr |= UART_EFR_RTS;
152 else
153 priv->efr &= ~UART_EFR_RTS;
154 serial_out(up, UART_EFR, priv->efr);
155 serial_out(up, UART_LCR, lcr);
156 }
157
158 /*
159 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
160 * The access to uart register after MDR1 Access
161 * causes UART to corrupt data.
162 *
163 * Need a delay =
164 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
165 * give 10 times as much
166 */
167 static void omap_8250_mdr1_errataset(struct uart_8250_port *up,
168 struct omap8250_priv *priv)
169 {
170 u8 timeout = 255;
171 u8 old_mdr1;
172
173 old_mdr1 = serial_in(up, UART_OMAP_MDR1);
174 if (old_mdr1 == priv->mdr1)
175 return;
176
177 serial_out(up, UART_OMAP_MDR1, priv->mdr1);
178 udelay(2);
179 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
180 UART_FCR_CLEAR_RCVR);
181 /*
182 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
183 * TX_FIFO_E bit is 1.
184 */
185 while (UART_LSR_THRE != (serial_in(up, UART_LSR) &
186 (UART_LSR_THRE | UART_LSR_DR))) {
187 timeout--;
188 if (!timeout) {
189 /* Should *never* happen. we warn and carry on */
190 dev_crit(up->port.dev, "Errata i202: timedout %x\n",
191 serial_in(up, UART_LSR));
192 break;
193 }
194 udelay(1);
195 }
196 }
197
198 static void omap_8250_get_divisor(struct uart_port *port, unsigned int baud,
199 struct omap8250_priv *priv)
200 {
201 unsigned int uartclk = port->uartclk;
202 unsigned int div_13, div_16;
203 unsigned int abs_d13, abs_d16;
204
205 /*
206 * Old custom speed handling.
207 */
208 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) {
209 priv->quot = port->custom_divisor & UART_DIV_MAX;
210 /*
211 * I assume that nobody is using this. But hey, if somebody
212 * would like to specify the divisor _and_ the mode then the
213 * driver is ready and waiting for it.
214 */
215 if (port->custom_divisor & (1 << 16))
216 priv->mdr1 = UART_OMAP_MDR1_13X_MODE;
217 else
218 priv->mdr1 = UART_OMAP_MDR1_16X_MODE;
219 return;
220 }
221 div_13 = DIV_ROUND_CLOSEST(uartclk, 13 * baud);
222 div_16 = DIV_ROUND_CLOSEST(uartclk, 16 * baud);
223
224 if (!div_13)
225 div_13 = 1;
226 if (!div_16)
227 div_16 = 1;
228
229 abs_d13 = abs(baud - uartclk / 13 / div_13);
230 abs_d16 = abs(baud - uartclk / 16 / div_16);
231
232 if (abs_d13 >= abs_d16) {
233 priv->mdr1 = UART_OMAP_MDR1_16X_MODE;
234 priv->quot = div_16;
235 } else {
236 priv->mdr1 = UART_OMAP_MDR1_13X_MODE;
237 priv->quot = div_13;
238 }
239 }
240
241 static void omap8250_update_scr(struct uart_8250_port *up,
242 struct omap8250_priv *priv)
243 {
244 u8 old_scr;
245
246 old_scr = serial_in(up, UART_OMAP_SCR);
247 if (old_scr == priv->scr)
248 return;
249
250 /*
251 * The manual recommends not to enable the DMA mode selector in the SCR
252 * (instead of the FCR) register _and_ selecting the DMA mode as one
253 * register write because this may lead to malfunction.
254 */
255 if (priv->scr & OMAP_UART_SCR_DMAMODE_MASK)
256 serial_out(up, UART_OMAP_SCR,
257 priv->scr & ~OMAP_UART_SCR_DMAMODE_MASK);
258 serial_out(up, UART_OMAP_SCR, priv->scr);
259 }
260
261 static void omap8250_update_mdr1(struct uart_8250_port *up,
262 struct omap8250_priv *priv)
263 {
264 if (priv->habit & UART_ERRATA_i202_MDR1_ACCESS)
265 omap_8250_mdr1_errataset(up, priv);
266 else
267 serial_out(up, UART_OMAP_MDR1, priv->mdr1);
268 }
269
270 static void omap8250_restore_regs(struct uart_8250_port *up)
271 {
272 struct omap8250_priv *priv = up->port.private_data;
273 struct uart_8250_dma *dma = up->dma;
274
275 if (dma && dma->tx_running) {
276 /*
277 * TCSANOW requests the change to occur immediately however if
278 * we have a TX-DMA operation in progress then it has been
279 * observed that it might stall and never complete. Therefore we
280 * delay DMA completes to prevent this hang from happen.
281 */
282 priv->delayed_restore = 1;
283 return;
284 }
285
286 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
287 serial_out(up, UART_EFR, UART_EFR_ECB);
288
289 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
290 serial8250_out_MCR(up, UART_MCR_TCRTLR);
291 serial_out(up, UART_FCR, up->fcr);
292
293 omap8250_update_scr(up, priv);
294
295 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
296
297 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_RESTORE(16) |
298 OMAP_UART_TCR_HALT(52));
299 serial_out(up, UART_TI752_TLR,
300 TRIGGER_TLR_MASK(TX_TRIGGER) << UART_TI752_TLR_TX |
301 TRIGGER_TLR_MASK(RX_TRIGGER) << UART_TI752_TLR_RX);
302
303 serial_out(up, UART_LCR, 0);
304
305 /* drop TCR + TLR access, we setup XON/XOFF later */
306 serial8250_out_MCR(up, up->mcr);
307 serial_out(up, UART_IER, up->ier);
308
309 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
310 serial_dl_write(up, priv->quot);
311
312 serial_out(up, UART_EFR, priv->efr);
313
314 /* Configure flow control */
315 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
316 serial_out(up, UART_XON1, priv->xon);
317 serial_out(up, UART_XOFF1, priv->xoff);
318
319 serial_out(up, UART_LCR, up->lcr);
320
321 omap8250_update_mdr1(up, priv);
322
323 up->port.ops->set_mctrl(&up->port, up->port.mctrl);
324 }
325
326 /*
327 * OMAP can use "CLK / (16 or 13) / div" for baud rate. And then we have have
328 * some differences in how we want to handle flow control.
329 */
330 static void omap_8250_set_termios(struct uart_port *port,
331 struct ktermios *termios,
332 struct ktermios *old)
333 {
334 struct uart_8250_port *up = up_to_u8250p(port);
335 struct omap8250_priv *priv = up->port.private_data;
336 unsigned char cval = 0;
337 unsigned int baud;
338
339 switch (termios->c_cflag & CSIZE) {
340 case CS5:
341 cval = UART_LCR_WLEN5;
342 break;
343 case CS6:
344 cval = UART_LCR_WLEN6;
345 break;
346 case CS7:
347 cval = UART_LCR_WLEN7;
348 break;
349 default:
350 case CS8:
351 cval = UART_LCR_WLEN8;
352 break;
353 }
354
355 if (termios->c_cflag & CSTOPB)
356 cval |= UART_LCR_STOP;
357 if (termios->c_cflag & PARENB)
358 cval |= UART_LCR_PARITY;
359 if (!(termios->c_cflag & PARODD))
360 cval |= UART_LCR_EPAR;
361 if (termios->c_cflag & CMSPAR)
362 cval |= UART_LCR_SPAR;
363
364 /*
365 * Ask the core to calculate the divisor for us.
366 */
367 baud = uart_get_baud_rate(port, termios, old,
368 port->uartclk / 16 / UART_DIV_MAX,
369 port->uartclk / 13);
370 omap_8250_get_divisor(port, baud, priv);
371
372 /*
373 * Ok, we're now changing the port state. Do it with
374 * interrupts disabled.
375 */
376 pm_runtime_get_sync(port->dev);
377 spin_lock_irq(&port->lock);
378
379 /*
380 * Update the per-port timeout.
381 */
382 uart_update_timeout(port, termios->c_cflag, baud);
383
384 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
385 if (termios->c_iflag & INPCK)
386 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
387 if (termios->c_iflag & (IGNBRK | PARMRK))
388 up->port.read_status_mask |= UART_LSR_BI;
389
390 /*
391 * Characters to ignore
392 */
393 up->port.ignore_status_mask = 0;
394 if (termios->c_iflag & IGNPAR)
395 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
396 if (termios->c_iflag & IGNBRK) {
397 up->port.ignore_status_mask |= UART_LSR_BI;
398 /*
399 * If we're ignoring parity and break indicators,
400 * ignore overruns too (for real raw support).
401 */
402 if (termios->c_iflag & IGNPAR)
403 up->port.ignore_status_mask |= UART_LSR_OE;
404 }
405
406 /*
407 * ignore all characters if CREAD is not set
408 */
409 if ((termios->c_cflag & CREAD) == 0)
410 up->port.ignore_status_mask |= UART_LSR_DR;
411
412 /*
413 * Modem status interrupts
414 */
415 up->ier &= ~UART_IER_MSI;
416 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
417 up->ier |= UART_IER_MSI;
418
419 up->lcr = cval;
420 /* Up to here it was mostly serial8250_do_set_termios() */
421
422 /*
423 * We enable TRIG_GRANU for RX and TX and additionally we set
424 * SCR_TX_EMPTY bit. The result is the following:
425 * - RX_TRIGGER amount of bytes in the FIFO will cause an interrupt.
426 * - less than RX_TRIGGER number of bytes will also cause an interrupt
427 * once the UART decides that there no new bytes arriving.
428 * - Once THRE is enabled, the interrupt will be fired once the FIFO is
429 * empty - the trigger level is ignored here.
430 *
431 * Once DMA is enabled:
432 * - UART will assert the TX DMA line once there is room for TX_TRIGGER
433 * bytes in the TX FIFO. On each assert the DMA engine will move
434 * TX_TRIGGER bytes into the FIFO.
435 * - UART will assert the RX DMA line once there are RX_TRIGGER bytes in
436 * the FIFO and move RX_TRIGGER bytes.
437 * This is because threshold and trigger values are the same.
438 */
439 up->fcr = UART_FCR_ENABLE_FIFO;
440 up->fcr |= TRIGGER_FCR_MASK(TX_TRIGGER) << OMAP_UART_FCR_TX_TRIG;
441 up->fcr |= TRIGGER_FCR_MASK(RX_TRIGGER) << OMAP_UART_FCR_RX_TRIG;
442
443 priv->scr = OMAP_UART_SCR_RX_TRIG_GRANU1_MASK | OMAP_UART_SCR_TX_EMPTY |
444 OMAP_UART_SCR_TX_TRIG_GRANU1_MASK;
445
446 if (up->dma)
447 priv->scr |= OMAP_UART_SCR_DMAMODE_1 |
448 OMAP_UART_SCR_DMAMODE_CTL;
449
450 priv->xon = termios->c_cc[VSTART];
451 priv->xoff = termios->c_cc[VSTOP];
452
453 priv->efr = 0;
454 up->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF);
455
456 if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW) {
457 /* Enable AUTOCTS (autoRTS is enabled when RTS is raised) */
458 up->port.status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
459 priv->efr |= UART_EFR_CTS;
460 } else if (up->port.flags & UPF_SOFT_FLOW) {
461 /*
462 * OMAP rx s/w flow control is borked; the transmitter remains
463 * stuck off even if rx flow control is subsequently disabled
464 */
465
466 /*
467 * IXOFF Flag:
468 * Enable XON/XOFF flow control on output.
469 * Transmit XON1, XOFF1
470 */
471 if (termios->c_iflag & IXOFF) {
472 up->port.status |= UPSTAT_AUTOXOFF;
473 priv->efr |= OMAP_UART_SW_TX;
474 }
475 }
476 omap8250_restore_regs(up);
477
478 spin_unlock_irq(&up->port.lock);
479 pm_runtime_mark_last_busy(port->dev);
480 pm_runtime_put_autosuspend(port->dev);
481
482 /* calculate wakeup latency constraint */
483 priv->calc_latency = USEC_PER_SEC * 64 * 8 / baud;
484 priv->latency = priv->calc_latency;
485
486 schedule_work(&priv->qos_work);
487
488 /* Don't rewrite B0 */
489 if (tty_termios_baud_rate(termios))
490 tty_termios_encode_baud_rate(termios, baud, baud);
491 }
492
493 /* same as 8250 except that we may have extra flow bits set in EFR */
494 static void omap_8250_pm(struct uart_port *port, unsigned int state,
495 unsigned int oldstate)
496 {
497 struct uart_8250_port *up = up_to_u8250p(port);
498 u8 efr;
499
500 pm_runtime_get_sync(port->dev);
501 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
502 efr = serial_in(up, UART_EFR);
503 serial_out(up, UART_EFR, efr | UART_EFR_ECB);
504 serial_out(up, UART_LCR, 0);
505
506 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
507 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
508 serial_out(up, UART_EFR, efr);
509 serial_out(up, UART_LCR, 0);
510
511 pm_runtime_mark_last_busy(port->dev);
512 pm_runtime_put_autosuspend(port->dev);
513 }
514
515 static void omap_serial_fill_features_erratas(struct uart_8250_port *up,
516 struct omap8250_priv *priv)
517 {
518 u32 mvr, scheme;
519 u16 revision, major, minor;
520
521 mvr = uart_read(up, UART_OMAP_MVER);
522
523 /* Check revision register scheme */
524 scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT;
525
526 switch (scheme) {
527 case 0: /* Legacy Scheme: OMAP2/3 */
528 /* MINOR_REV[0:4], MAJOR_REV[4:7] */
529 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >>
530 OMAP_UART_LEGACY_MVR_MAJ_SHIFT;
531 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK);
532 break;
533 case 1:
534 /* New Scheme: OMAP4+ */
535 /* MINOR_REV[0:5], MAJOR_REV[8:10] */
536 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >>
537 OMAP_UART_MVR_MAJ_SHIFT;
538 minor = (mvr & OMAP_UART_MVR_MIN_MASK);
539 break;
540 default:
541 dev_warn(up->port.dev,
542 "Unknown revision, defaulting to highest\n");
543 /* highest possible revision */
544 major = 0xff;
545 minor = 0xff;
546 }
547 /* normalize revision for the driver */
548 revision = UART_BUILD_REVISION(major, minor);
549
550 switch (revision) {
551 case OMAP_UART_REV_46:
552 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS;
553 break;
554 case OMAP_UART_REV_52:
555 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS |
556 OMAP_UART_WER_HAS_TX_WAKEUP;
557 break;
558 case OMAP_UART_REV_63:
559 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS |
560 OMAP_UART_WER_HAS_TX_WAKEUP;
561 break;
562 default:
563 break;
564 }
565 }
566
567 static void omap8250_uart_qos_work(struct work_struct *work)
568 {
569 struct omap8250_priv *priv;
570
571 priv = container_of(work, struct omap8250_priv, qos_work);
572 pm_qos_update_request(&priv->pm_qos_request, priv->latency);
573 }
574
575 #ifdef CONFIG_SERIAL_8250_DMA
576 static int omap_8250_dma_handle_irq(struct uart_port *port);
577 #endif
578
579 static irqreturn_t omap8250_irq(int irq, void *dev_id)
580 {
581 struct uart_port *port = dev_id;
582 struct uart_8250_port *up = up_to_u8250p(port);
583 unsigned int iir;
584 int ret;
585
586 #ifdef CONFIG_SERIAL_8250_DMA
587 if (up->dma) {
588 ret = omap_8250_dma_handle_irq(port);
589 return IRQ_RETVAL(ret);
590 }
591 #endif
592
593 serial8250_rpm_get(up);
594 iir = serial_port_in(port, UART_IIR);
595 ret = serial8250_handle_irq(port, iir);
596 serial8250_rpm_put(up);
597
598 return IRQ_RETVAL(ret);
599 }
600
601 static int omap_8250_startup(struct uart_port *port)
602 {
603 struct uart_8250_port *up = up_to_u8250p(port);
604 struct omap8250_priv *priv = port->private_data;
605 int ret;
606
607 if (priv->wakeirq) {
608 ret = dev_pm_set_dedicated_wake_irq(port->dev, priv->wakeirq);
609 if (ret)
610 return ret;
611 }
612
613 pm_runtime_get_sync(port->dev);
614
615 up->mcr = 0;
616 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
617
618 serial_out(up, UART_LCR, UART_LCR_WLEN8);
619
620 up->lsr_saved_flags = 0;
621 up->msr_saved_flags = 0;
622
623 /* Disable DMA for console UART */
624 if (uart_console(port))
625 up->dma = NULL;
626
627 if (up->dma) {
628 ret = serial8250_request_dma(up);
629 if (ret) {
630 dev_warn_ratelimited(port->dev,
631 "failed to request DMA\n");
632 up->dma = NULL;
633 }
634 }
635
636 ret = request_irq(port->irq, omap8250_irq, IRQF_SHARED,
637 dev_name(port->dev), port);
638 if (ret < 0)
639 goto err;
640
641 up->ier = UART_IER_RLSI | UART_IER_RDI;
642 serial_out(up, UART_IER, up->ier);
643
644 #ifdef CONFIG_PM
645 up->capabilities |= UART_CAP_RPM;
646 #endif
647
648 /* Enable module level wake up */
649 priv->wer = OMAP_UART_WER_MOD_WKUP;
650 if (priv->habit & OMAP_UART_WER_HAS_TX_WAKEUP)
651 priv->wer |= OMAP_UART_TX_WAKEUP_EN;
652 serial_out(up, UART_OMAP_WER, priv->wer);
653
654 if (up->dma)
655 up->dma->rx_dma(up);
656
657 pm_runtime_mark_last_busy(port->dev);
658 pm_runtime_put_autosuspend(port->dev);
659 return 0;
660 err:
661 pm_runtime_mark_last_busy(port->dev);
662 pm_runtime_put_autosuspend(port->dev);
663 dev_pm_clear_wake_irq(port->dev);
664 return ret;
665 }
666
667 static void omap_8250_shutdown(struct uart_port *port)
668 {
669 struct uart_8250_port *up = up_to_u8250p(port);
670 struct omap8250_priv *priv = port->private_data;
671
672 flush_work(&priv->qos_work);
673 if (up->dma)
674 omap_8250_rx_dma_flush(up);
675
676 pm_runtime_get_sync(port->dev);
677
678 serial_out(up, UART_OMAP_WER, 0);
679
680 up->ier = 0;
681 serial_out(up, UART_IER, 0);
682
683 if (up->dma)
684 serial8250_release_dma(up);
685
686 /*
687 * Disable break condition and FIFOs
688 */
689 if (up->lcr & UART_LCR_SBC)
690 serial_out(up, UART_LCR, up->lcr & ~UART_LCR_SBC);
691 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
692
693 pm_runtime_mark_last_busy(port->dev);
694 pm_runtime_put_autosuspend(port->dev);
695 free_irq(port->irq, port);
696 dev_pm_clear_wake_irq(port->dev);
697 }
698
699 static void omap_8250_throttle(struct uart_port *port)
700 {
701 struct omap8250_priv *priv = port->private_data;
702 struct uart_8250_port *up = up_to_u8250p(port);
703 unsigned long flags;
704
705 pm_runtime_get_sync(port->dev);
706
707 spin_lock_irqsave(&port->lock, flags);
708 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
709 serial_out(up, UART_IER, up->ier);
710 priv->throttled = true;
711 spin_unlock_irqrestore(&port->lock, flags);
712
713 pm_runtime_mark_last_busy(port->dev);
714 pm_runtime_put_autosuspend(port->dev);
715 }
716
717 static int omap_8250_rs485_config(struct uart_port *port,
718 struct serial_rs485 *rs485)
719 {
720 struct uart_8250_port *up = up_to_u8250p(port);
721
722 /* Clamp the delays to [0, 100ms] */
723 rs485->delay_rts_before_send = min(rs485->delay_rts_before_send, 100U);
724 rs485->delay_rts_after_send = min(rs485->delay_rts_after_send, 100U);
725
726 port->rs485 = *rs485;
727
728 /*
729 * Both serial8250_em485_init and serial8250_em485_destroy
730 * are idempotent
731 */
732 if (rs485->flags & SER_RS485_ENABLED) {
733 int ret = serial8250_em485_init(up);
734
735 if (ret) {
736 rs485->flags &= ~SER_RS485_ENABLED;
737 port->rs485.flags &= ~SER_RS485_ENABLED;
738 }
739 return ret;
740 }
741
742 serial8250_em485_destroy(up);
743
744 return 0;
745 }
746
747 static void omap_8250_unthrottle(struct uart_port *port)
748 {
749 struct omap8250_priv *priv = port->private_data;
750 struct uart_8250_port *up = up_to_u8250p(port);
751 unsigned long flags;
752
753 pm_runtime_get_sync(port->dev);
754
755 spin_lock_irqsave(&port->lock, flags);
756 priv->throttled = false;
757 if (up->dma)
758 up->dma->rx_dma(up);
759 up->ier |= UART_IER_RLSI | UART_IER_RDI;
760 serial_out(up, UART_IER, up->ier);
761 spin_unlock_irqrestore(&port->lock, flags);
762
763 pm_runtime_mark_last_busy(port->dev);
764 pm_runtime_put_autosuspend(port->dev);
765 }
766
767 #ifdef CONFIG_SERIAL_8250_DMA
768 static int omap_8250_rx_dma(struct uart_8250_port *p);
769
770 static void __dma_rx_do_complete(struct uart_8250_port *p)
771 {
772 struct omap8250_priv *priv = p->port.private_data;
773 struct uart_8250_dma *dma = p->dma;
774 struct tty_port *tty_port = &p->port.state->port;
775 struct dma_tx_state state;
776 int count;
777 unsigned long flags;
778 int ret;
779
780 spin_lock_irqsave(&priv->rx_dma_lock, flags);
781
782 if (!dma->rx_running)
783 goto unlock;
784
785 dma->rx_running = 0;
786 dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state);
787
788 count = dma->rx_size - state.residue;
789
790 ret = tty_insert_flip_string(tty_port, dma->rx_buf, count);
791
792 p->port.icount.rx += ret;
793 p->port.icount.buf_overrun += count - ret;
794 unlock:
795 spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
796
797 tty_flip_buffer_push(tty_port);
798 }
799
800 static void __dma_rx_complete(void *param)
801 {
802 struct uart_8250_port *p = param;
803 struct omap8250_priv *priv = p->port.private_data;
804 struct uart_8250_dma *dma = p->dma;
805 struct dma_tx_state state;
806 unsigned long flags;
807
808 spin_lock_irqsave(&p->port.lock, flags);
809
810 /*
811 * If the tx status is not DMA_COMPLETE, then this is a delayed
812 * completion callback. A previous RX timeout flush would have
813 * already pushed the data, so exit.
814 */
815 if (dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state) !=
816 DMA_COMPLETE) {
817 spin_unlock_irqrestore(&p->port.lock, flags);
818 return;
819 }
820 __dma_rx_do_complete(p);
821 if (!priv->throttled)
822 omap_8250_rx_dma(p);
823
824 spin_unlock_irqrestore(&p->port.lock, flags);
825 }
826
827 static void omap_8250_rx_dma_flush(struct uart_8250_port *p)
828 {
829 struct omap8250_priv *priv = p->port.private_data;
830 struct uart_8250_dma *dma = p->dma;
831 struct dma_tx_state state;
832 unsigned long flags;
833 int ret;
834
835 spin_lock_irqsave(&priv->rx_dma_lock, flags);
836
837 if (!dma->rx_running) {
838 spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
839 return;
840 }
841
842 ret = dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state);
843 if (ret == DMA_IN_PROGRESS) {
844 ret = dmaengine_pause(dma->rxchan);
845 if (WARN_ON_ONCE(ret))
846 priv->rx_dma_broken = true;
847 }
848 spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
849
850 __dma_rx_do_complete(p);
851 dmaengine_terminate_all(dma->rxchan);
852 }
853
854 static int omap_8250_rx_dma(struct uart_8250_port *p)
855 {
856 struct omap8250_priv *priv = p->port.private_data;
857 struct uart_8250_dma *dma = p->dma;
858 int err = 0;
859 struct dma_async_tx_descriptor *desc;
860 unsigned long flags;
861
862 if (priv->rx_dma_broken)
863 return -EINVAL;
864
865 spin_lock_irqsave(&priv->rx_dma_lock, flags);
866
867 if (dma->rx_running)
868 goto out;
869
870 desc = dmaengine_prep_slave_single(dma->rxchan, dma->rx_addr,
871 dma->rx_size, DMA_DEV_TO_MEM,
872 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
873 if (!desc) {
874 err = -EBUSY;
875 goto out;
876 }
877
878 dma->rx_running = 1;
879 desc->callback = __dma_rx_complete;
880 desc->callback_param = p;
881
882 dma->rx_cookie = dmaengine_submit(desc);
883
884 dma_async_issue_pending(dma->rxchan);
885 out:
886 spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
887 return err;
888 }
889
890 static int omap_8250_tx_dma(struct uart_8250_port *p);
891
892 static void omap_8250_dma_tx_complete(void *param)
893 {
894 struct uart_8250_port *p = param;
895 struct uart_8250_dma *dma = p->dma;
896 struct circ_buf *xmit = &p->port.state->xmit;
897 unsigned long flags;
898 bool en_thri = false;
899 struct omap8250_priv *priv = p->port.private_data;
900
901 dma_sync_single_for_cpu(dma->txchan->device->dev, dma->tx_addr,
902 UART_XMIT_SIZE, DMA_TO_DEVICE);
903
904 spin_lock_irqsave(&p->port.lock, flags);
905
906 dma->tx_running = 0;
907
908 xmit->tail += dma->tx_size;
909 xmit->tail &= UART_XMIT_SIZE - 1;
910 p->port.icount.tx += dma->tx_size;
911
912 if (priv->delayed_restore) {
913 priv->delayed_restore = 0;
914 omap8250_restore_regs(p);
915 }
916
917 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
918 uart_write_wakeup(&p->port);
919
920 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&p->port)) {
921 int ret;
922
923 ret = omap_8250_tx_dma(p);
924 if (ret)
925 en_thri = true;
926
927 } else if (p->capabilities & UART_CAP_RPM) {
928 en_thri = true;
929 }
930
931 if (en_thri) {
932 dma->tx_err = 1;
933 p->ier |= UART_IER_THRI;
934 serial_port_out(&p->port, UART_IER, p->ier);
935 }
936
937 spin_unlock_irqrestore(&p->port.lock, flags);
938 }
939
940 static int omap_8250_tx_dma(struct uart_8250_port *p)
941 {
942 struct uart_8250_dma *dma = p->dma;
943 struct omap8250_priv *priv = p->port.private_data;
944 struct circ_buf *xmit = &p->port.state->xmit;
945 struct dma_async_tx_descriptor *desc;
946 unsigned int skip_byte = 0;
947 int ret;
948
949 if (dma->tx_running)
950 return 0;
951 if (uart_tx_stopped(&p->port) || uart_circ_empty(xmit)) {
952
953 /*
954 * Even if no data, we need to return an error for the two cases
955 * below so serial8250_tx_chars() is invoked and properly clears
956 * THRI and/or runtime suspend.
957 */
958 if (dma->tx_err || p->capabilities & UART_CAP_RPM) {
959 ret = -EBUSY;
960 goto err;
961 }
962 if (p->ier & UART_IER_THRI) {
963 p->ier &= ~UART_IER_THRI;
964 serial_out(p, UART_IER, p->ier);
965 }
966 return 0;
967 }
968
969 dma->tx_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
970 if (priv->habit & OMAP_DMA_TX_KICK) {
971 u8 tx_lvl;
972
973 /*
974 * We need to put the first byte into the FIFO in order to start
975 * the DMA transfer. For transfers smaller than four bytes we
976 * don't bother doing DMA at all. It seem not matter if there
977 * are still bytes in the FIFO from the last transfer (in case
978 * we got here directly from omap_8250_dma_tx_complete()). Bytes
979 * leaving the FIFO seem not to trigger the DMA transfer. It is
980 * really the byte that we put into the FIFO.
981 * If the FIFO is already full then we most likely got here from
982 * omap_8250_dma_tx_complete(). And this means the DMA engine
983 * just completed its work. We don't have to wait the complete
984 * 86us at 115200,8n1 but around 60us (not to mention lower
985 * baudrates). So in that case we take the interrupt and try
986 * again with an empty FIFO.
987 */
988 tx_lvl = serial_in(p, UART_OMAP_TX_LVL);
989 if (tx_lvl == p->tx_loadsz) {
990 ret = -EBUSY;
991 goto err;
992 }
993 if (dma->tx_size < 4) {
994 ret = -EINVAL;
995 goto err;
996 }
997 skip_byte = 1;
998 }
999
1000 desc = dmaengine_prep_slave_single(dma->txchan,
1001 dma->tx_addr + xmit->tail + skip_byte,
1002 dma->tx_size - skip_byte, DMA_MEM_TO_DEV,
1003 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1004 if (!desc) {
1005 ret = -EBUSY;
1006 goto err;
1007 }
1008
1009 dma->tx_running = 1;
1010
1011 desc->callback = omap_8250_dma_tx_complete;
1012 desc->callback_param = p;
1013
1014 dma->tx_cookie = dmaengine_submit(desc);
1015
1016 dma_sync_single_for_device(dma->txchan->device->dev, dma->tx_addr,
1017 UART_XMIT_SIZE, DMA_TO_DEVICE);
1018
1019 dma_async_issue_pending(dma->txchan);
1020 if (dma->tx_err)
1021 dma->tx_err = 0;
1022
1023 if (p->ier & UART_IER_THRI) {
1024 p->ier &= ~UART_IER_THRI;
1025 serial_out(p, UART_IER, p->ier);
1026 }
1027 if (skip_byte)
1028 serial_out(p, UART_TX, xmit->buf[xmit->tail]);
1029 return 0;
1030 err:
1031 dma->tx_err = 1;
1032 return ret;
1033 }
1034
1035 static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir)
1036 {
1037 switch (iir & 0x3f) {
1038 case UART_IIR_RLSI:
1039 case UART_IIR_RX_TIMEOUT:
1040 case UART_IIR_RDI:
1041 omap_8250_rx_dma_flush(up);
1042 return true;
1043 }
1044 return omap_8250_rx_dma(up);
1045 }
1046
1047 /*
1048 * This is mostly serial8250_handle_irq(). We have a slightly different DMA
1049 * hoook for RX/TX and need different logic for them in the ISR. Therefore we
1050 * use the default routine in the non-DMA case and this one for with DMA.
1051 */
1052 static int omap_8250_dma_handle_irq(struct uart_port *port)
1053 {
1054 struct uart_8250_port *up = up_to_u8250p(port);
1055 unsigned char status;
1056 unsigned long flags;
1057 u8 iir;
1058
1059 serial8250_rpm_get(up);
1060
1061 iir = serial_port_in(port, UART_IIR);
1062 if (iir & UART_IIR_NO_INT) {
1063 serial8250_rpm_put(up);
1064 return 0;
1065 }
1066
1067 spin_lock_irqsave(&port->lock, flags);
1068
1069 status = serial_port_in(port, UART_LSR);
1070
1071 if (status & (UART_LSR_DR | UART_LSR_BI)) {
1072 if (handle_rx_dma(up, iir)) {
1073 status = serial8250_rx_chars(up, status);
1074 omap_8250_rx_dma(up);
1075 }
1076 }
1077 serial8250_modem_status(up);
1078 if (status & UART_LSR_THRE && up->dma->tx_err) {
1079 if (uart_tx_stopped(&up->port) ||
1080 uart_circ_empty(&up->port.state->xmit)) {
1081 up->dma->tx_err = 0;
1082 serial8250_tx_chars(up);
1083 } else {
1084 /*
1085 * try again due to an earlier failer which
1086 * might have been resolved by now.
1087 */
1088 if (omap_8250_tx_dma(up))
1089 serial8250_tx_chars(up);
1090 }
1091 }
1092
1093 uart_unlock_and_check_sysrq(port, flags);
1094 serial8250_rpm_put(up);
1095 return 1;
1096 }
1097
1098 static bool the_no_dma_filter_fn(struct dma_chan *chan, void *param)
1099 {
1100 return false;
1101 }
1102
1103 #else
1104
1105 static inline int omap_8250_rx_dma(struct uart_8250_port *p)
1106 {
1107 return -EINVAL;
1108 }
1109 #endif
1110
1111 static int omap8250_no_handle_irq(struct uart_port *port)
1112 {
1113 /* IRQ has not been requested but handling irq? */
1114 WARN_ONCE(1, "Unexpected irq handling before port startup\n");
1115 return 0;
1116 }
1117
1118 static const u8 omap4_habit = UART_ERRATA_CLOCK_DISABLE;
1119 static const u8 am3352_habit = OMAP_DMA_TX_KICK | UART_ERRATA_CLOCK_DISABLE;
1120 static const u8 dra742_habit = UART_ERRATA_CLOCK_DISABLE;
1121
1122 static const struct of_device_id omap8250_dt_ids[] = {
1123 { .compatible = "ti,am654-uart" },
1124 { .compatible = "ti,omap2-uart" },
1125 { .compatible = "ti,omap3-uart" },
1126 { .compatible = "ti,omap4-uart", .data = &omap4_habit, },
1127 { .compatible = "ti,am3352-uart", .data = &am3352_habit, },
1128 { .compatible = "ti,am4372-uart", .data = &am3352_habit, },
1129 { .compatible = "ti,dra742-uart", .data = &dra742_habit, },
1130 {},
1131 };
1132 MODULE_DEVICE_TABLE(of, omap8250_dt_ids);
1133
1134 static int omap8250_probe(struct platform_device *pdev)
1135 {
1136 struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1137 struct resource *irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1138 struct device_node *np = pdev->dev.of_node;
1139 struct omap8250_priv *priv;
1140 struct uart_8250_port up;
1141 int ret;
1142 void __iomem *membase;
1143 const struct of_device_id *id;
1144
1145 if (!regs || !irq) {
1146 dev_err(&pdev->dev, "missing registers or irq\n");
1147 return -EINVAL;
1148 }
1149
1150 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
1151 if (!priv)
1152 return -ENOMEM;
1153
1154 membase = devm_ioremap_nocache(&pdev->dev, regs->start,
1155 resource_size(regs));
1156 if (!membase)
1157 return -ENODEV;
1158
1159 memset(&up, 0, sizeof(up));
1160 up.port.dev = &pdev->dev;
1161 up.port.mapbase = regs->start;
1162 up.port.membase = membase;
1163 up.port.irq = irq->start;
1164 /*
1165 * It claims to be 16C750 compatible however it is a little different.
1166 * It has EFR and has no FCR7_64byte bit. The AFE (which it claims to
1167 * have) is enabled via EFR instead of MCR. The type is set here 8250
1168 * just to get things going. UNKNOWN does not work for a few reasons and
1169 * we don't need our own type since we don't use 8250's set_termios()
1170 * or pm callback.
1171 */
1172 up.port.type = PORT_8250;
1173 up.port.iotype = UPIO_MEM;
1174 up.port.flags = UPF_FIXED_PORT | UPF_FIXED_TYPE | UPF_SOFT_FLOW |
1175 UPF_HARD_FLOW;
1176 up.port.private_data = priv;
1177
1178 up.port.regshift = 2;
1179 up.port.fifosize = 64;
1180 up.tx_loadsz = 64;
1181 up.capabilities = UART_CAP_FIFO;
1182 #ifdef CONFIG_PM
1183 /*
1184 * Runtime PM is mostly transparent. However to do it right we need to a
1185 * TX empty interrupt before we can put the device to auto idle. So if
1186 * PM is not enabled we don't add that flag and can spare that one extra
1187 * interrupt in the TX path.
1188 */
1189 up.capabilities |= UART_CAP_RPM;
1190 #endif
1191 up.port.set_termios = omap_8250_set_termios;
1192 up.port.set_mctrl = omap8250_set_mctrl;
1193 up.port.pm = omap_8250_pm;
1194 up.port.startup = omap_8250_startup;
1195 up.port.shutdown = omap_8250_shutdown;
1196 up.port.throttle = omap_8250_throttle;
1197 up.port.unthrottle = omap_8250_unthrottle;
1198 up.port.rs485_config = omap_8250_rs485_config;
1199
1200 ret = of_alias_get_id(np, "serial");
1201 if (ret < 0) {
1202 dev_err(&pdev->dev, "failed to get alias\n");
1203 return ret;
1204 }
1205 up.port.line = ret;
1206
1207 if (of_property_read_u32(np, "clock-frequency", &up.port.uartclk)) {
1208 struct clk *clk;
1209
1210 clk = devm_clk_get(&pdev->dev, NULL);
1211 if (IS_ERR(clk)) {
1212 if (PTR_ERR(clk) == -EPROBE_DEFER)
1213 return -EPROBE_DEFER;
1214 } else {
1215 up.port.uartclk = clk_get_rate(clk);
1216 }
1217 }
1218
1219 priv->wakeirq = irq_of_parse_and_map(np, 1);
1220
1221 id = of_match_device(of_match_ptr(omap8250_dt_ids), &pdev->dev);
1222 if (id && id->data)
1223 priv->habit |= *(u8 *)id->data;
1224
1225 if (!up.port.uartclk) {
1226 up.port.uartclk = DEFAULT_CLK_SPEED;
1227 dev_warn(&pdev->dev,
1228 "No clock speed specified: using default: %d\n",
1229 DEFAULT_CLK_SPEED);
1230 }
1231
1232 priv->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1233 priv->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1234 pm_qos_add_request(&priv->pm_qos_request, PM_QOS_CPU_DMA_LATENCY,
1235 priv->latency);
1236 INIT_WORK(&priv->qos_work, omap8250_uart_qos_work);
1237
1238 spin_lock_init(&priv->rx_dma_lock);
1239
1240 device_init_wakeup(&pdev->dev, true);
1241 pm_runtime_use_autosuspend(&pdev->dev);
1242 pm_runtime_set_autosuspend_delay(&pdev->dev, -1);
1243
1244 pm_runtime_irq_safe(&pdev->dev);
1245 pm_runtime_enable(&pdev->dev);
1246
1247 pm_runtime_get_sync(&pdev->dev);
1248
1249 omap_serial_fill_features_erratas(&up, priv);
1250 up.port.handle_irq = omap8250_no_handle_irq;
1251 #ifdef CONFIG_SERIAL_8250_DMA
1252 /*
1253 * Oh DMA support. If there are no DMA properties in the DT then
1254 * we will fall back to a generic DMA channel which does not
1255 * really work here. To ensure that we do not get a generic DMA
1256 * channel assigned, we have the the_no_dma_filter_fn() here.
1257 * To avoid "failed to request DMA" messages we check for DMA
1258 * properties in DT.
1259 */
1260 ret = of_property_count_strings(np, "dma-names");
1261 if (ret == 2) {
1262 up.dma = &priv->omap8250_dma;
1263 priv->omap8250_dma.fn = the_no_dma_filter_fn;
1264 priv->omap8250_dma.tx_dma = omap_8250_tx_dma;
1265 priv->omap8250_dma.rx_dma = omap_8250_rx_dma;
1266 priv->omap8250_dma.rx_size = RX_TRIGGER;
1267 priv->omap8250_dma.rxconf.src_maxburst = RX_TRIGGER;
1268 priv->omap8250_dma.txconf.dst_maxburst = TX_TRIGGER;
1269 }
1270 #endif
1271 ret = serial8250_register_8250_port(&up);
1272 if (ret < 0) {
1273 dev_err(&pdev->dev, "unable to register 8250 port\n");
1274 goto err;
1275 }
1276 priv->line = ret;
1277 platform_set_drvdata(pdev, priv);
1278 pm_runtime_mark_last_busy(&pdev->dev);
1279 pm_runtime_put_autosuspend(&pdev->dev);
1280 return 0;
1281 err:
1282 pm_runtime_dont_use_autosuspend(&pdev->dev);
1283 pm_runtime_put_sync(&pdev->dev);
1284 pm_runtime_disable(&pdev->dev);
1285 return ret;
1286 }
1287
1288 static int omap8250_remove(struct platform_device *pdev)
1289 {
1290 struct omap8250_priv *priv = platform_get_drvdata(pdev);
1291
1292 pm_runtime_dont_use_autosuspend(&pdev->dev);
1293 pm_runtime_put_sync(&pdev->dev);
1294 pm_runtime_disable(&pdev->dev);
1295 serial8250_unregister_port(priv->line);
1296 pm_qos_remove_request(&priv->pm_qos_request);
1297 device_init_wakeup(&pdev->dev, false);
1298 return 0;
1299 }
1300
1301 #ifdef CONFIG_PM_SLEEP
1302 static int omap8250_prepare(struct device *dev)
1303 {
1304 struct omap8250_priv *priv = dev_get_drvdata(dev);
1305
1306 if (!priv)
1307 return 0;
1308 priv->is_suspending = true;
1309 return 0;
1310 }
1311
1312 static void omap8250_complete(struct device *dev)
1313 {
1314 struct omap8250_priv *priv = dev_get_drvdata(dev);
1315
1316 if (!priv)
1317 return;
1318 priv->is_suspending = false;
1319 }
1320
1321 static int omap8250_suspend(struct device *dev)
1322 {
1323 struct omap8250_priv *priv = dev_get_drvdata(dev);
1324 struct uart_8250_port *up = serial8250_get_port(priv->line);
1325
1326 serial8250_suspend_port(priv->line);
1327
1328 pm_runtime_get_sync(dev);
1329 if (!device_may_wakeup(dev))
1330 priv->wer = 0;
1331 serial_out(up, UART_OMAP_WER, priv->wer);
1332 pm_runtime_mark_last_busy(dev);
1333 pm_runtime_put_autosuspend(dev);
1334
1335 flush_work(&priv->qos_work);
1336 return 0;
1337 }
1338
1339 static int omap8250_resume(struct device *dev)
1340 {
1341 struct omap8250_priv *priv = dev_get_drvdata(dev);
1342
1343 serial8250_resume_port(priv->line);
1344 return 0;
1345 }
1346 #else
1347 #define omap8250_prepare NULL
1348 #define omap8250_complete NULL
1349 #endif
1350
1351 #ifdef CONFIG_PM
1352 static int omap8250_lost_context(struct uart_8250_port *up)
1353 {
1354 u32 val;
1355
1356 val = serial_in(up, UART_OMAP_SCR);
1357 /*
1358 * If we lose context, then SCR is set to its reset value of zero.
1359 * After set_termios() we set bit 3 of SCR (TX_EMPTY_CTL_IT) to 1,
1360 * among other bits, to never set the register back to zero again.
1361 */
1362 if (!val)
1363 return 1;
1364 return 0;
1365 }
1366
1367 /* TODO: in future, this should happen via API in drivers/reset/ */
1368 static int omap8250_soft_reset(struct device *dev)
1369 {
1370 struct omap8250_priv *priv = dev_get_drvdata(dev);
1371 struct uart_8250_port *up = serial8250_get_port(priv->line);
1372 int timeout = 100;
1373 int sysc;
1374 int syss;
1375
1376 /*
1377 * At least on omap4, unused uarts may not idle after reset without
1378 * a basic scr dma configuration even with no dma in use. The
1379 * module clkctrl status bits will be 1 instead of 3 blocking idle
1380 * for the whole clockdomain. The softreset below will clear scr,
1381 * and we restore it on resume so this is safe to do on all SoCs
1382 * needing omap8250_soft_reset() quirk. Do it in two writes as
1383 * recommended in the comment for omap8250_update_scr().
1384 */
1385 serial_out(up, UART_OMAP_SCR, OMAP_UART_SCR_DMAMODE_1);
1386 serial_out(up, UART_OMAP_SCR,
1387 OMAP_UART_SCR_DMAMODE_1 | OMAP_UART_SCR_DMAMODE_CTL);
1388
1389 sysc = serial_in(up, UART_OMAP_SYSC);
1390
1391 /* softreset the UART */
1392 sysc |= OMAP_UART_SYSC_SOFTRESET;
1393 serial_out(up, UART_OMAP_SYSC, sysc);
1394
1395 /* By experiments, 1us enough for reset complete on AM335x */
1396 do {
1397 udelay(1);
1398 syss = serial_in(up, UART_OMAP_SYSS);
1399 } while (--timeout && !(syss & OMAP_UART_SYSS_RESETDONE));
1400
1401 if (!timeout) {
1402 dev_err(dev, "timed out waiting for reset done\n");
1403 return -ETIMEDOUT;
1404 }
1405
1406 return 0;
1407 }
1408
1409 static int omap8250_runtime_suspend(struct device *dev)
1410 {
1411 struct omap8250_priv *priv = dev_get_drvdata(dev);
1412 struct uart_8250_port *up;
1413
1414 /* In case runtime-pm tries this before we are setup */
1415 if (!priv)
1416 return 0;
1417
1418 up = serial8250_get_port(priv->line);
1419 /*
1420 * When using 'no_console_suspend', the console UART must not be
1421 * suspended. Since driver suspend is managed by runtime suspend,
1422 * preventing runtime suspend (by returning error) will keep device
1423 * active during suspend.
1424 */
1425 if (priv->is_suspending && !console_suspend_enabled) {
1426 if (uart_console(&up->port))
1427 return -EBUSY;
1428 }
1429
1430 if (priv->habit & UART_ERRATA_CLOCK_DISABLE) {
1431 int ret;
1432
1433 ret = omap8250_soft_reset(dev);
1434 if (ret)
1435 return ret;
1436
1437 /* Restore to UART mode after reset (for wakeup) */
1438 omap8250_update_mdr1(up, priv);
1439 /* Restore wakeup enable register */
1440 serial_out(up, UART_OMAP_WER, priv->wer);
1441 }
1442
1443 if (up->dma && up->dma->rxchan)
1444 omap_8250_rx_dma_flush(up);
1445
1446 priv->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1447 schedule_work(&priv->qos_work);
1448
1449 return 0;
1450 }
1451
1452 static int omap8250_runtime_resume(struct device *dev)
1453 {
1454 struct omap8250_priv *priv = dev_get_drvdata(dev);
1455 struct uart_8250_port *up;
1456
1457 /* In case runtime-pm tries this before we are setup */
1458 if (!priv)
1459 return 0;
1460
1461 up = serial8250_get_port(priv->line);
1462
1463 if (omap8250_lost_context(up))
1464 omap8250_restore_regs(up);
1465
1466 if (up->dma && up->dma->rxchan)
1467 omap_8250_rx_dma(up);
1468
1469 priv->latency = priv->calc_latency;
1470 schedule_work(&priv->qos_work);
1471 return 0;
1472 }
1473 #endif
1474
1475 #ifdef CONFIG_SERIAL_8250_OMAP_TTYO_FIXUP
1476 static int __init omap8250_console_fixup(void)
1477 {
1478 char *omap_str;
1479 char *options;
1480 u8 idx;
1481
1482 if (strstr(boot_command_line, "console=ttyS"))
1483 /* user set a ttyS based name for the console */
1484 return 0;
1485
1486 omap_str = strstr(boot_command_line, "console=ttyO");
1487 if (!omap_str)
1488 /* user did not set ttyO based console, so we don't care */
1489 return 0;
1490
1491 omap_str += 12;
1492 if ('0' <= *omap_str && *omap_str <= '9')
1493 idx = *omap_str - '0';
1494 else
1495 return 0;
1496
1497 omap_str++;
1498 if (omap_str[0] == ',') {
1499 omap_str++;
1500 options = omap_str;
1501 } else {
1502 options = NULL;
1503 }
1504
1505 add_preferred_console("ttyS", idx, options);
1506 pr_err("WARNING: Your 'console=ttyO%d' has been replaced by 'ttyS%d'\n",
1507 idx, idx);
1508 pr_err("This ensures that you still see kernel messages. Please\n");
1509 pr_err("update your kernel commandline.\n");
1510 return 0;
1511 }
1512 console_initcall(omap8250_console_fixup);
1513 #endif
1514
1515 static const struct dev_pm_ops omap8250_dev_pm_ops = {
1516 SET_SYSTEM_SLEEP_PM_OPS(omap8250_suspend, omap8250_resume)
1517 SET_RUNTIME_PM_OPS(omap8250_runtime_suspend,
1518 omap8250_runtime_resume, NULL)
1519 .prepare = omap8250_prepare,
1520 .complete = omap8250_complete,
1521 };
1522
1523 static struct platform_driver omap8250_platform_driver = {
1524 .driver = {
1525 .name = "omap8250",
1526 .pm = &omap8250_dev_pm_ops,
1527 .of_match_table = omap8250_dt_ids,
1528 },
1529 .probe = omap8250_probe,
1530 .remove = omap8250_remove,
1531 };
1532 module_platform_driver(omap8250_platform_driver);
1533
1534 MODULE_AUTHOR("Sebastian Andrzej Siewior");
1535 MODULE_DESCRIPTION("OMAP 8250 Driver");
1536 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support