1 // SPDX-License-Identifier: GPL-2.0+
3 * include/linux/atmel_serial.h
5 * Copyright (C) 2005 Ivan Kokshaysky
6 * Copyright (C) SAN People
9 * Based on AT91RM9200 datasheet revision E.
12 #ifndef ATMEL_SERIAL_H
13 #define ATMEL_SERIAL_H
15 #define ATMEL_US_CR 0x00 /* Control Register */
16 #define ATMEL_US_RSTRX BIT(2) /* Reset Receiver */
17 #define ATMEL_US_RSTTX BIT(3) /* Reset Transmitter */
18 #define ATMEL_US_RXEN BIT(4) /* Receiver Enable */
19 #define ATMEL_US_RXDIS BIT(5) /* Receiver Disable */
20 #define ATMEL_US_TXEN BIT(6) /* Transmitter Enable */
21 #define ATMEL_US_TXDIS BIT(7) /* Transmitter Disable */
22 #define ATMEL_US_RSTSTA BIT(8) /* Reset Status Bits */
23 #define ATMEL_US_STTBRK BIT(9) /* Start Break */
24 #define ATMEL_US_STPBRK BIT(10) /* Stop Break */
25 #define ATMEL_US_STTTO BIT(11) /* Start Time-out */
26 #define ATMEL_US_SENDA BIT(12) /* Send Address */
27 #define ATMEL_US_RSTIT BIT(13) /* Reset Iterations */
28 #define ATMEL_US_RSTNACK BIT(14) /* Reset Non Acknowledge */
29 #define ATMEL_US_RETTO BIT(15) /* Rearm Time-out */
30 #define ATMEL_US_DTREN BIT(16) /* Data Terminal Ready Enable */
31 #define ATMEL_US_DTRDIS BIT(17) /* Data Terminal Ready Disable */
32 #define ATMEL_US_RTSEN BIT(18) /* Request To Send Enable */
33 #define ATMEL_US_RTSDIS BIT(19) /* Request To Send Disable */
34 #define ATMEL_US_TXFCLR BIT(24) /* Transmit FIFO Clear */
35 #define ATMEL_US_RXFCLR BIT(25) /* Receive FIFO Clear */
36 #define ATMEL_US_TXFLCLR BIT(26) /* Transmit FIFO Lock Clear */
37 #define ATMEL_US_FIFOEN BIT(30) /* FIFO enable */
38 #define ATMEL_US_FIFODIS BIT(31) /* FIFO disable */
40 #define ATMEL_US_MR 0x04 /* Mode Register */
41 #define ATMEL_US_USMODE GENMASK(3, 0) /* Mode of the USART */
42 #define ATMEL_US_USMODE_NORMAL 0
43 #define ATMEL_US_USMODE_RS485 1
44 #define ATMEL_US_USMODE_HWHS 2
45 #define ATMEL_US_USMODE_MODEM 3
46 #define ATMEL_US_USMODE_ISO7816_T0 4
47 #define ATMEL_US_USMODE_ISO7816_T1 6
48 #define ATMEL_US_USMODE_IRDA 8
49 #define ATMEL_US_USCLKS GENMASK(5, 4) /* Clock Selection */
50 #define ATMEL_US_USCLKS_MCK (0 << 4)
51 #define ATMEL_US_USCLKS_MCK_DIV8 (1 << 4)
52 #define ATMEL_US_USCLKS_SCK (3 << 4)
53 #define ATMEL_US_CHRL GENMASK(7, 6) /* Character Length */
54 #define ATMEL_US_CHRL_5 (0 << 6)
55 #define ATMEL_US_CHRL_6 (1 << 6)
56 #define ATMEL_US_CHRL_7 (2 << 6)
57 #define ATMEL_US_CHRL_8 (3 << 6)
58 #define ATMEL_US_SYNC BIT(8) /* Synchronous Mode Select */
59 #define ATMEL_US_PAR GENMASK(11, 9) /* Parity Type */
60 #define ATMEL_US_PAR_EVEN (0 << 9)
61 #define ATMEL_US_PAR_ODD (1 << 9)
62 #define ATMEL_US_PAR_SPACE (2 << 9)
63 #define ATMEL_US_PAR_MARK (3 << 9)
64 #define ATMEL_US_PAR_NONE (4 << 9)
65 #define ATMEL_US_PAR_MULTI_DROP (6 << 9)
66 #define ATMEL_US_NBSTOP GENMASK(13, 12) /* Number of Stop Bits */
67 #define ATMEL_US_NBSTOP_1 (0 << 12)
68 #define ATMEL_US_NBSTOP_1_5 (1 << 12)
69 #define ATMEL_US_NBSTOP_2 (2 << 12)
70 #define ATMEL_US_CHMODE GENMASK(15, 14) /* Channel Mode */
71 #define ATMEL_US_CHMODE_NORMAL (0 << 14)
72 #define ATMEL_US_CHMODE_ECHO (1 << 14)
73 #define ATMEL_US_CHMODE_LOC_LOOP (2 << 14)
74 #define ATMEL_US_CHMODE_REM_LOOP (3 << 14)
75 #define ATMEL_US_MSBF BIT(16) /* Bit Order */
76 #define ATMEL_US_MODE9 BIT(17) /* 9-bit Character Length */
77 #define ATMEL_US_CLKO BIT(18) /* Clock Output Select */
78 #define ATMEL_US_OVER BIT(19) /* Oversampling Mode */
79 #define ATMEL_US_INACK BIT(20) /* Inhibit Non Acknowledge */
80 #define ATMEL_US_DSNACK BIT(21) /* Disable Successive NACK */
81 #define ATMEL_US_MAX_ITER_MASK GENMASK(26, 24) /* Max Iterations */
82 #define ATMEL_US_MAX_ITER(n) (((n) << 24) & ATMEL_US_MAX_ITER_MASK)
83 #define ATMEL_US_FILTER BIT(28) /* Infrared Receive Line Filter */
85 #define ATMEL_US_IER 0x08 /* Interrupt Enable Register */
86 #define ATMEL_US_RXRDY BIT(0) /* Receiver Ready */
87 #define ATMEL_US_TXRDY BIT(1) /* Transmitter Ready */
88 #define ATMEL_US_RXBRK BIT(2) /* Break Received / End of Break */
89 #define ATMEL_US_ENDRX BIT(3) /* End of Receiver Transfer */
90 #define ATMEL_US_ENDTX BIT(4) /* End of Transmitter Transfer */
91 #define ATMEL_US_OVRE BIT(5) /* Overrun Error */
92 #define ATMEL_US_FRAME BIT(6) /* Framing Error */
93 #define ATMEL_US_PARE BIT(7) /* Parity Error */
94 #define ATMEL_US_TIMEOUT BIT(8) /* Receiver Time-out */
95 #define ATMEL_US_TXEMPTY BIT(9) /* Transmitter Empty */
96 #define ATMEL_US_ITERATION BIT(10) /* Max number of Repetitions Reached */
97 #define ATMEL_US_TXBUFE BIT(11) /* Transmission Buffer Empty */
98 #define ATMEL_US_RXBUFF BIT(12) /* Reception Buffer Full */
99 #define ATMEL_US_NACK BIT(13) /* Non Acknowledge */
100 #define ATMEL_US_RIIC BIT(16) /* Ring Indicator Input Change */
101 #define ATMEL_US_DSRIC BIT(17) /* Data Set Ready Input Change */
102 #define ATMEL_US_DCDIC BIT(18) /* Data Carrier Detect Input Change */
103 #define ATMEL_US_CTSIC BIT(19) /* Clear to Send Input Change */
104 #define ATMEL_US_RI BIT(20) /* RI */
105 #define ATMEL_US_DSR BIT(21) /* DSR */
106 #define ATMEL_US_DCD BIT(22) /* DCD */
107 #define ATMEL_US_CTS BIT(23) /* CTS */
109 #define ATMEL_US_IDR 0x0c /* Interrupt Disable Register */
110 #define ATMEL_US_IMR 0x10 /* Interrupt Mask Register */
111 #define ATMEL_US_CSR 0x14 /* Channel Status Register */
112 #define ATMEL_US_RHR 0x18 /* Receiver Holding Register */
113 #define ATMEL_US_THR 0x1c /* Transmitter Holding Register */
114 #define ATMEL_US_SYNH BIT(15) /* Transmit/Receive Sync */
116 #define ATMEL_US_BRGR 0x20 /* Baud Rate Generator Register */
117 #define ATMEL_US_CD GENMASK(15, 0) /* Clock Divider */
118 #define ATMEL_US_FP_OFFSET 16 /* Fractional Part */
119 #define ATMEL_US_FP_MASK 0x7
121 #define ATMEL_US_RTOR 0x24 /* Receiver Time-out Register for USART */
122 #define ATMEL_UA_RTOR 0x28 /* Receiver Time-out Register for UART */
123 #define ATMEL_US_TO GENMASK(15, 0) /* Time-out Value */
125 #define ATMEL_US_TTGR 0x28 /* Transmitter Timeguard Register */
126 #define ATMEL_US_TG GENMASK(7, 0) /* Timeguard Value */
128 #define ATMEL_US_FIDI 0x40 /* FI DI Ratio Register */
129 #define ATMEL_US_NER 0x44 /* Number of Errors Register */
130 #define ATMEL_US_IF 0x4c /* IrDA Filter Register */
132 #define ATMEL_US_CMPR 0x90 /* Comparaison Register */
133 #define ATMEL_US_FMR 0xa0 /* FIFO Mode Register */
134 #define ATMEL_US_TXRDYM(data) (((data) & 0x3) << 0) /* TX Ready Mode */
135 #define ATMEL_US_RXRDYM(data) (((data) & 0x3) << 4) /* RX Ready Mode */
136 #define ATMEL_US_ONE_DATA 0x0
137 #define ATMEL_US_TWO_DATA 0x1
138 #define ATMEL_US_FOUR_DATA 0x2
139 #define ATMEL_US_FRTSC BIT(7) /* FIFO RTS pin Control */
140 #define ATMEL_US_TXFTHRES(thr) (((thr) & 0x3f) << 8) /* TX FIFO Threshold */
141 #define ATMEL_US_RXFTHRES(thr) (((thr) & 0x3f) << 16) /* RX FIFO Threshold */
142 #define ATMEL_US_RXFTHRES2(thr) (((thr) & 0x3f) << 24) /* RX FIFO Threshold2 */
144 #define ATMEL_US_FLR 0xa4 /* FIFO Level Register */
145 #define ATMEL_US_TXFL(reg) (((reg) >> 0) & 0x3f) /* TX FIFO Level */
146 #define ATMEL_US_RXFL(reg) (((reg) >> 16) & 0x3f) /* RX FIFO Level */
148 #define ATMEL_US_FIER 0xa8 /* FIFO Interrupt Enable Register */
149 #define ATMEL_US_FIDR 0xac /* FIFO Interrupt Disable Register */
150 #define ATMEL_US_FIMR 0xb0 /* FIFO Interrupt Mask Register */
151 #define ATMEL_US_FESR 0xb4 /* FIFO Event Status Register */
152 #define ATMEL_US_TXFEF BIT(0) /* Transmit FIFO Empty Flag */
153 #define ATMEL_US_TXFFF BIT(1) /* Transmit FIFO Full Flag */
154 #define ATMEL_US_TXFTHF BIT(2) /* Transmit FIFO Threshold Flag */
155 #define ATMEL_US_RXFEF BIT(3) /* Receive FIFO Empty Flag */
156 #define ATMEL_US_RXFFF BIT(4) /* Receive FIFO Full Flag */
157 #define ATMEL_US_RXFTHF BIT(5) /* Receive FIFO Threshold Flag */
158 #define ATMEL_US_TXFPTEF BIT(6) /* Transmit FIFO Pointer Error Flag */
159 #define ATMEL_US_RXFPTEF BIT(7) /* Receive FIFO Pointer Error Flag */
160 #define ATMEL_US_TXFLOCK BIT(8) /* Transmit FIFO Lock (FESR only) */
161 #define ATMEL_US_RXFTHF2 BIT(9) /* Receive FIFO Threshold Flag 2 */
163 #define ATMEL_US_NAME 0xf0 /* Ip Name */
164 #define ATMEL_US_VERSION 0xfc /* Ip Version */
