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staging: erofs: integrate decompression inplace
[linux/fpc-iii.git] / drivers / tty / serial / fsl_lpuart.c
blobea1c85e3b432c67125d3b7c365270b553a9dc053
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Freescale lpuart serial port driver
4 *
5 * Copyright 2012-2014 Freescale Semiconductor, Inc.
6 */
7
8 #if defined(CONFIG_SERIAL_FSL_LPUART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
9 #define SUPPORT_SYSRQ
10 #endif
11
12 #include <linux/clk.h>
13 #include <linux/console.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/dmaengine.h>
16 #include <linux/dmapool.h>
17 #include <linux/io.h>
18 #include <linux/irq.h>
19 #include <linux/module.h>
20 #include <linux/of.h>
21 #include <linux/of_device.h>
22 #include <linux/of_dma.h>
23 #include <linux/serial_core.h>
24 #include <linux/slab.h>
25 #include <linux/tty_flip.h>
26
27 /* All registers are 8-bit width */
28 #define UARTBDH 0x00
29 #define UARTBDL 0x01
30 #define UARTCR1 0x02
31 #define UARTCR2 0x03
32 #define UARTSR1 0x04
33 #define UARTCR3 0x06
34 #define UARTDR 0x07
35 #define UARTCR4 0x0a
36 #define UARTCR5 0x0b
37 #define UARTMODEM 0x0d
38 #define UARTPFIFO 0x10
39 #define UARTCFIFO 0x11
40 #define UARTSFIFO 0x12
41 #define UARTTWFIFO 0x13
42 #define UARTTCFIFO 0x14
43 #define UARTRWFIFO 0x15
44
45 #define UARTBDH_LBKDIE 0x80
46 #define UARTBDH_RXEDGIE 0x40
47 #define UARTBDH_SBR_MASK 0x1f
48
49 #define UARTCR1_LOOPS 0x80
50 #define UARTCR1_RSRC 0x20
51 #define UARTCR1_M 0x10
52 #define UARTCR1_WAKE 0x08
53 #define UARTCR1_ILT 0x04
54 #define UARTCR1_PE 0x02
55 #define UARTCR1_PT 0x01
56
57 #define UARTCR2_TIE 0x80
58 #define UARTCR2_TCIE 0x40
59 #define UARTCR2_RIE 0x20
60 #define UARTCR2_ILIE 0x10
61 #define UARTCR2_TE 0x08
62 #define UARTCR2_RE 0x04
63 #define UARTCR2_RWU 0x02
64 #define UARTCR2_SBK 0x01
65
66 #define UARTSR1_TDRE 0x80
67 #define UARTSR1_TC 0x40
68 #define UARTSR1_RDRF 0x20
69 #define UARTSR1_IDLE 0x10
70 #define UARTSR1_OR 0x08
71 #define UARTSR1_NF 0x04
72 #define UARTSR1_FE 0x02
73 #define UARTSR1_PE 0x01
74
75 #define UARTCR3_R8 0x80
76 #define UARTCR3_T8 0x40
77 #define UARTCR3_TXDIR 0x20
78 #define UARTCR3_TXINV 0x10
79 #define UARTCR3_ORIE 0x08
80 #define UARTCR3_NEIE 0x04
81 #define UARTCR3_FEIE 0x02
82 #define UARTCR3_PEIE 0x01
83
84 #define UARTCR4_MAEN1 0x80
85 #define UARTCR4_MAEN2 0x40
86 #define UARTCR4_M10 0x20
87 #define UARTCR4_BRFA_MASK 0x1f
88 #define UARTCR4_BRFA_OFF 0
89
90 #define UARTCR5_TDMAS 0x80
91 #define UARTCR5_RDMAS 0x20
92
93 #define UARTMODEM_RXRTSE 0x08
94 #define UARTMODEM_TXRTSPOL 0x04
95 #define UARTMODEM_TXRTSE 0x02
96 #define UARTMODEM_TXCTSE 0x01
97
98 #define UARTPFIFO_TXFE 0x80
99 #define UARTPFIFO_FIFOSIZE_MASK 0x7
100 #define UARTPFIFO_TXSIZE_OFF 4
101 #define UARTPFIFO_RXFE 0x08
102 #define UARTPFIFO_RXSIZE_OFF 0
103
104 #define UARTCFIFO_TXFLUSH 0x80
105 #define UARTCFIFO_RXFLUSH 0x40
106 #define UARTCFIFO_RXOFE 0x04
107 #define UARTCFIFO_TXOFE 0x02
108 #define UARTCFIFO_RXUFE 0x01
109
110 #define UARTSFIFO_TXEMPT 0x80
111 #define UARTSFIFO_RXEMPT 0x40
112 #define UARTSFIFO_RXOF 0x04
113 #define UARTSFIFO_TXOF 0x02
114 #define UARTSFIFO_RXUF 0x01
115
116 /* 32-bit register definition */
117 #define UARTBAUD 0x00
118 #define UARTSTAT 0x04
119 #define UARTCTRL 0x08
120 #define UARTDATA 0x0C
121 #define UARTMATCH 0x10
122 #define UARTMODIR 0x14
123 #define UARTFIFO 0x18
124 #define UARTWATER 0x1c
125
126 #define UARTBAUD_MAEN1 0x80000000
127 #define UARTBAUD_MAEN2 0x40000000
128 #define UARTBAUD_M10 0x20000000
129 #define UARTBAUD_TDMAE 0x00800000
130 #define UARTBAUD_RDMAE 0x00200000
131 #define UARTBAUD_MATCFG 0x00400000
132 #define UARTBAUD_BOTHEDGE 0x00020000
133 #define UARTBAUD_RESYNCDIS 0x00010000
134 #define UARTBAUD_LBKDIE 0x00008000
135 #define UARTBAUD_RXEDGIE 0x00004000
136 #define UARTBAUD_SBNS 0x00002000
137 #define UARTBAUD_SBR 0x00000000
138 #define UARTBAUD_SBR_MASK 0x1fff
139 #define UARTBAUD_OSR_MASK 0x1f
140 #define UARTBAUD_OSR_SHIFT 24
141
142 #define UARTSTAT_LBKDIF 0x80000000
143 #define UARTSTAT_RXEDGIF 0x40000000
144 #define UARTSTAT_MSBF 0x20000000
145 #define UARTSTAT_RXINV 0x10000000
146 #define UARTSTAT_RWUID 0x08000000
147 #define UARTSTAT_BRK13 0x04000000
148 #define UARTSTAT_LBKDE 0x02000000
149 #define UARTSTAT_RAF 0x01000000
150 #define UARTSTAT_TDRE 0x00800000
151 #define UARTSTAT_TC 0x00400000
152 #define UARTSTAT_RDRF 0x00200000
153 #define UARTSTAT_IDLE 0x00100000
154 #define UARTSTAT_OR 0x00080000
155 #define UARTSTAT_NF 0x00040000
156 #define UARTSTAT_FE 0x00020000
157 #define UARTSTAT_PE 0x00010000
158 #define UARTSTAT_MA1F 0x00008000
159 #define UARTSTAT_M21F 0x00004000
160
161 #define UARTCTRL_R8T9 0x80000000
162 #define UARTCTRL_R9T8 0x40000000
163 #define UARTCTRL_TXDIR 0x20000000
164 #define UARTCTRL_TXINV 0x10000000
165 #define UARTCTRL_ORIE 0x08000000
166 #define UARTCTRL_NEIE 0x04000000
167 #define UARTCTRL_FEIE 0x02000000
168 #define UARTCTRL_PEIE 0x01000000
169 #define UARTCTRL_TIE 0x00800000
170 #define UARTCTRL_TCIE 0x00400000
171 #define UARTCTRL_RIE 0x00200000
172 #define UARTCTRL_ILIE 0x00100000
173 #define UARTCTRL_TE 0x00080000
174 #define UARTCTRL_RE 0x00040000
175 #define UARTCTRL_RWU 0x00020000
176 #define UARTCTRL_SBK 0x00010000
177 #define UARTCTRL_MA1IE 0x00008000
178 #define UARTCTRL_MA2IE 0x00004000
179 #define UARTCTRL_IDLECFG 0x00000100
180 #define UARTCTRL_LOOPS 0x00000080
181 #define UARTCTRL_DOZEEN 0x00000040
182 #define UARTCTRL_RSRC 0x00000020
183 #define UARTCTRL_M 0x00000010
184 #define UARTCTRL_WAKE 0x00000008
185 #define UARTCTRL_ILT 0x00000004
186 #define UARTCTRL_PE 0x00000002
187 #define UARTCTRL_PT 0x00000001
188
189 #define UARTDATA_NOISY 0x00008000
190 #define UARTDATA_PARITYE 0x00004000
191 #define UARTDATA_FRETSC 0x00002000
192 #define UARTDATA_RXEMPT 0x00001000
193 #define UARTDATA_IDLINE 0x00000800
194 #define UARTDATA_MASK 0x3ff
195
196 #define UARTMODIR_IREN 0x00020000
197 #define UARTMODIR_TXCTSSRC 0x00000020
198 #define UARTMODIR_TXCTSC 0x00000010
199 #define UARTMODIR_RXRTSE 0x00000008
200 #define UARTMODIR_TXRTSPOL 0x00000004
201 #define UARTMODIR_TXRTSE 0x00000002
202 #define UARTMODIR_TXCTSE 0x00000001
203
204 #define UARTFIFO_TXEMPT 0x00800000
205 #define UARTFIFO_RXEMPT 0x00400000
206 #define UARTFIFO_TXOF 0x00020000
207 #define UARTFIFO_RXUF 0x00010000
208 #define UARTFIFO_TXFLUSH 0x00008000
209 #define UARTFIFO_RXFLUSH 0x00004000
210 #define UARTFIFO_TXOFE 0x00000200
211 #define UARTFIFO_RXUFE 0x00000100
212 #define UARTFIFO_TXFE 0x00000080
213 #define UARTFIFO_FIFOSIZE_MASK 0x7
214 #define UARTFIFO_TXSIZE_OFF 4
215 #define UARTFIFO_RXFE 0x00000008
216 #define UARTFIFO_RXSIZE_OFF 0
217
218 #define UARTWATER_COUNT_MASK 0xff
219 #define UARTWATER_TXCNT_OFF 8
220 #define UARTWATER_RXCNT_OFF 24
221 #define UARTWATER_WATER_MASK 0xff
222 #define UARTWATER_TXWATER_OFF 0
223 #define UARTWATER_RXWATER_OFF 16
224
225 /* Rx DMA timeout in ms, which is used to calculate Rx ring buffer size */
226 #define DMA_RX_TIMEOUT (10)
227
228 #define DRIVER_NAME "fsl-lpuart"
229 #define DEV_NAME "ttyLP"
230 #define UART_NR 6
231
232 /* IMX lpuart has four extra unused regs located at the beginning */
233 #define IMX_REG_OFF 0x10
234
235 static DEFINE_IDA(fsl_lpuart_ida);
236
237 struct lpuart_port {
238 struct uart_port port;
239 struct clk *clk;
240 unsigned int txfifo_size;
241 unsigned int rxfifo_size;
242
243 bool lpuart_dma_tx_use;
244 bool lpuart_dma_rx_use;
245 struct dma_chan *dma_tx_chan;
246 struct dma_chan *dma_rx_chan;
247 struct dma_async_tx_descriptor *dma_tx_desc;
248 struct dma_async_tx_descriptor *dma_rx_desc;
249 dma_cookie_t dma_tx_cookie;
250 dma_cookie_t dma_rx_cookie;
251 unsigned int dma_tx_bytes;
252 unsigned int dma_rx_bytes;
253 bool dma_tx_in_progress;
254 unsigned int dma_rx_timeout;
255 struct timer_list lpuart_timer;
256 struct scatterlist rx_sgl, tx_sgl[2];
257 struct circ_buf rx_ring;
258 int rx_dma_rng_buf_len;
259 unsigned int dma_tx_nents;
260 wait_queue_head_t dma_wait;
261 };
262
263 struct lpuart_soc_data {
264 char iotype;
265 u8 reg_off;
266 };
267
268 static const struct lpuart_soc_data vf_data = {
269 .iotype = UPIO_MEM,
270 };
271
272 static const struct lpuart_soc_data ls_data = {
273 .iotype = UPIO_MEM32BE,
274 };
275
276 static struct lpuart_soc_data imx_data = {
277 .iotype = UPIO_MEM32,
278 .reg_off = IMX_REG_OFF,
279 };
280
281 static const struct of_device_id lpuart_dt_ids[] = {
282 { .compatible = "fsl,vf610-lpuart", .data = &vf_data, },
283 { .compatible = "fsl,ls1021a-lpuart", .data = &ls_data, },
284 { .compatible = "fsl,imx7ulp-lpuart", .data = &imx_data, },
285 { /* sentinel */ }
286 };
287 MODULE_DEVICE_TABLE(of, lpuart_dt_ids);
288
289 /* Forward declare this for the dma callbacks*/
290 static void lpuart_dma_tx_complete(void *arg);
291
292 static inline u32 lpuart32_read(struct uart_port *port, u32 off)
293 {
294 switch (port->iotype) {
295 case UPIO_MEM32:
296 return readl(port->membase + off);
297 case UPIO_MEM32BE:
298 return ioread32be(port->membase + off);
299 default:
300 return 0;
301 }
302 }
303
304 static inline void lpuart32_write(struct uart_port *port, u32 val,
305 u32 off)
306 {
307 switch (port->iotype) {
308 case UPIO_MEM32:
309 writel(val, port->membase + off);
310 break;
311 case UPIO_MEM32BE:
312 iowrite32be(val, port->membase + off);
313 break;
314 }
315 }
316
317 static void lpuart_stop_tx(struct uart_port *port)
318 {
319 unsigned char temp;
320
321 temp = readb(port->membase + UARTCR2);
322 temp &= ~(UARTCR2_TIE | UARTCR2_TCIE);
323 writeb(temp, port->membase + UARTCR2);
324 }
325
326 static void lpuart32_stop_tx(struct uart_port *port)
327 {
328 unsigned long temp;
329
330 temp = lpuart32_read(port, UARTCTRL);
331 temp &= ~(UARTCTRL_TIE | UARTCTRL_TCIE);
332 lpuart32_write(port, temp, UARTCTRL);
333 }
334
335 static void lpuart_stop_rx(struct uart_port *port)
336 {
337 unsigned char temp;
338
339 temp = readb(port->membase + UARTCR2);
340 writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2);
341 }
342
343 static void lpuart32_stop_rx(struct uart_port *port)
344 {
345 unsigned long temp;
346
347 temp = lpuart32_read(port, UARTCTRL);
348 lpuart32_write(port, temp & ~UARTCTRL_RE, UARTCTRL);
349 }
350
351 static void lpuart_dma_tx(struct lpuart_port *sport)
352 {
353 struct circ_buf *xmit = &sport->port.state->xmit;
354 struct scatterlist *sgl = sport->tx_sgl;
355 struct device *dev = sport->port.dev;
356 int ret;
357
358 if (sport->dma_tx_in_progress)
359 return;
360
361 sport->dma_tx_bytes = uart_circ_chars_pending(xmit);
362
363 if (xmit->tail < xmit->head || xmit->head == 0) {
364 sport->dma_tx_nents = 1;
365 sg_init_one(sgl, xmit->buf + xmit->tail, sport->dma_tx_bytes);
366 } else {
367 sport->dma_tx_nents = 2;
368 sg_init_table(sgl, 2);
369 sg_set_buf(sgl, xmit->buf + xmit->tail,
370 UART_XMIT_SIZE - xmit->tail);
371 sg_set_buf(sgl + 1, xmit->buf, xmit->head);
372 }
373
374 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
375 if (!ret) {
376 dev_err(dev, "DMA mapping error for TX.\n");
377 return;
378 }
379
380 sport->dma_tx_desc = dmaengine_prep_slave_sg(sport->dma_tx_chan, sgl,
381 sport->dma_tx_nents,
382 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
383 if (!sport->dma_tx_desc) {
384 dma_unmap_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
385 dev_err(dev, "Cannot prepare TX slave DMA!\n");
386 return;
387 }
388
389 sport->dma_tx_desc->callback = lpuart_dma_tx_complete;
390 sport->dma_tx_desc->callback_param = sport;
391 sport->dma_tx_in_progress = true;
392 sport->dma_tx_cookie = dmaengine_submit(sport->dma_tx_desc);
393 dma_async_issue_pending(sport->dma_tx_chan);
394 }
395
396 static void lpuart_dma_tx_complete(void *arg)
397 {
398 struct lpuart_port *sport = arg;
399 struct scatterlist *sgl = &sport->tx_sgl[0];
400 struct circ_buf *xmit = &sport->port.state->xmit;
401 unsigned long flags;
402
403 spin_lock_irqsave(&sport->port.lock, flags);
404
405 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
406
407 xmit->tail = (xmit->tail + sport->dma_tx_bytes) & (UART_XMIT_SIZE - 1);
408
409 sport->port.icount.tx += sport->dma_tx_bytes;
410 sport->dma_tx_in_progress = false;
411 spin_unlock_irqrestore(&sport->port.lock, flags);
412
413 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
414 uart_write_wakeup(&sport->port);
415
416 if (waitqueue_active(&sport->dma_wait)) {
417 wake_up(&sport->dma_wait);
418 return;
419 }
420
421 spin_lock_irqsave(&sport->port.lock, flags);
422
423 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port))
424 lpuart_dma_tx(sport);
425
426 spin_unlock_irqrestore(&sport->port.lock, flags);
427 }
428
429 static dma_addr_t lpuart_dma_datareg_addr(struct lpuart_port *sport)
430 {
431 switch (sport->port.iotype) {
432 case UPIO_MEM32:
433 return sport->port.mapbase + UARTDATA;
434 case UPIO_MEM32BE:
435 return sport->port.mapbase + UARTDATA + sizeof(u32) - 1;
436 }
437 return sport->port.mapbase + UARTDR;
438 }
439
440 static int lpuart_dma_tx_request(struct uart_port *port)
441 {
442 struct lpuart_port *sport = container_of(port,
443 struct lpuart_port, port);
444 struct dma_slave_config dma_tx_sconfig = {};
445 int ret;
446
447 dma_tx_sconfig.dst_addr = lpuart_dma_datareg_addr(sport);
448 dma_tx_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
449 dma_tx_sconfig.dst_maxburst = 1;
450 dma_tx_sconfig.direction = DMA_MEM_TO_DEV;
451 ret = dmaengine_slave_config(sport->dma_tx_chan, &dma_tx_sconfig);
452
453 if (ret) {
454 dev_err(sport->port.dev,
455 "DMA slave config failed, err = %d\n", ret);
456 return ret;
457 }
458
459 return 0;
460 }
461
462 static void lpuart_flush_buffer(struct uart_port *port)
463 {
464 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
465
466 if (sport->lpuart_dma_tx_use) {
467 if (sport->dma_tx_in_progress) {
468 dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0],
469 sport->dma_tx_nents, DMA_TO_DEVICE);
470 sport->dma_tx_in_progress = false;
471 }
472 dmaengine_terminate_all(sport->dma_tx_chan);
473 }
474 }
475
476 #if defined(CONFIG_CONSOLE_POLL)
477
478 static int lpuart_poll_init(struct uart_port *port)
479 {
480 struct lpuart_port *sport = container_of(port,
481 struct lpuart_port, port);
482 unsigned long flags;
483 unsigned char temp;
484
485 sport->port.fifosize = 0;
486
487 spin_lock_irqsave(&sport->port.lock, flags);
488 /* Disable Rx & Tx */
489 writeb(0, sport->port.membase + UARTCR2);
490
491 temp = readb(sport->port.membase + UARTPFIFO);
492 /* Enable Rx and Tx FIFO */
493 writeb(temp | UARTPFIFO_RXFE | UARTPFIFO_TXFE,
494 sport->port.membase + UARTPFIFO);
495
496 /* flush Tx and Rx FIFO */
497 writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH,
498 sport->port.membase + UARTCFIFO);
499
500 /* explicitly clear RDRF */
501 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) {
502 readb(sport->port.membase + UARTDR);
503 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO);
504 }
505
506 writeb(0, sport->port.membase + UARTTWFIFO);
507 writeb(1, sport->port.membase + UARTRWFIFO);
508
509 /* Enable Rx and Tx */
510 writeb(UARTCR2_RE | UARTCR2_TE, sport->port.membase + UARTCR2);
511 spin_unlock_irqrestore(&sport->port.lock, flags);
512
513 return 0;
514 }
515
516 static void lpuart_poll_put_char(struct uart_port *port, unsigned char c)
517 {
518 /* drain */
519 while (!(readb(port->membase + UARTSR1) & UARTSR1_TDRE))
520 barrier();
521
522 writeb(c, port->membase + UARTDR);
523 }
524
525 static int lpuart_poll_get_char(struct uart_port *port)
526 {
527 if (!(readb(port->membase + UARTSR1) & UARTSR1_RDRF))
528 return NO_POLL_CHAR;
529
530 return readb(port->membase + UARTDR);
531 }
532
533 static int lpuart32_poll_init(struct uart_port *port)
534 {
535 unsigned long flags;
536 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
537 u32 temp;
538
539 sport->port.fifosize = 0;
540
541 spin_lock_irqsave(&sport->port.lock, flags);
542
543 /* Disable Rx & Tx */
544 writel(0, sport->port.membase + UARTCTRL);
545
546 temp = readl(sport->port.membase + UARTFIFO);
547
548 /* Enable Rx and Tx FIFO */
549 writel(temp | UARTFIFO_RXFE | UARTFIFO_TXFE,
550 sport->port.membase + UARTFIFO);
551
552 /* flush Tx and Rx FIFO */
553 writel(UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH,
554 sport->port.membase + UARTFIFO);
555
556 /* explicitly clear RDRF */
557 if (readl(sport->port.membase + UARTSTAT) & UARTSTAT_RDRF) {
558 readl(sport->port.membase + UARTDATA);
559 writel(UARTFIFO_RXUF, sport->port.membase + UARTFIFO);
560 }
561
562 /* Enable Rx and Tx */
563 writel(UARTCTRL_RE | UARTCTRL_TE, sport->port.membase + UARTCTRL);
564 spin_unlock_irqrestore(&sport->port.lock, flags);
565
566 return 0;
567 }
568
569 static void lpuart32_poll_put_char(struct uart_port *port, unsigned char c)
570 {
571 while (!(readl(port->membase + UARTSTAT) & UARTSTAT_TDRE))
572 barrier();
573
574 writel(c, port->membase + UARTDATA);
575 }
576
577 static int lpuart32_poll_get_char(struct uart_port *port)
578 {
579 if (!(readl(port->membase + UARTSTAT) & UARTSTAT_RDRF))
580 return NO_POLL_CHAR;
581
582 return readl(port->membase + UARTDATA);
583 }
584 #endif
585
586 static inline void lpuart_transmit_buffer(struct lpuart_port *sport)
587 {
588 struct circ_buf *xmit = &sport->port.state->xmit;
589
590 while (!uart_circ_empty(xmit) &&
591 (readb(sport->port.membase + UARTTCFIFO) < sport->txfifo_size)) {
592 writeb(xmit->buf[xmit->tail], sport->port.membase + UARTDR);
593 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
594 sport->port.icount.tx++;
595 }
596
597 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
598 uart_write_wakeup(&sport->port);
599
600 if (uart_circ_empty(xmit))
601 lpuart_stop_tx(&sport->port);
602 }
603
604 static inline void lpuart32_transmit_buffer(struct lpuart_port *sport)
605 {
606 struct circ_buf *xmit = &sport->port.state->xmit;
607 unsigned long txcnt;
608
609 txcnt = lpuart32_read(&sport->port, UARTWATER);
610 txcnt = txcnt >> UARTWATER_TXCNT_OFF;
611 txcnt &= UARTWATER_COUNT_MASK;
612 while (!uart_circ_empty(xmit) && (txcnt < sport->txfifo_size)) {
613 lpuart32_write(&sport->port, xmit->buf[xmit->tail], UARTDATA);
614 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
615 sport->port.icount.tx++;
616 txcnt = lpuart32_read(&sport->port, UARTWATER);
617 txcnt = txcnt >> UARTWATER_TXCNT_OFF;
618 txcnt &= UARTWATER_COUNT_MASK;
619 }
620
621 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
622 uart_write_wakeup(&sport->port);
623
624 if (uart_circ_empty(xmit))
625 lpuart32_stop_tx(&sport->port);
626 }
627
628 static void lpuart_start_tx(struct uart_port *port)
629 {
630 struct lpuart_port *sport = container_of(port,
631 struct lpuart_port, port);
632 struct circ_buf *xmit = &sport->port.state->xmit;
633 unsigned char temp;
634
635 temp = readb(port->membase + UARTCR2);
636 writeb(temp | UARTCR2_TIE, port->membase + UARTCR2);
637
638 if (sport->lpuart_dma_tx_use) {
639 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port))
640 lpuart_dma_tx(sport);
641 } else {
642 if (readb(port->membase + UARTSR1) & UARTSR1_TDRE)
643 lpuart_transmit_buffer(sport);
644 }
645 }
646
647 static void lpuart32_start_tx(struct uart_port *port)
648 {
649 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
650 struct circ_buf *xmit = &sport->port.state->xmit;
651 unsigned long temp;
652
653 if (sport->lpuart_dma_tx_use) {
654 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port))
655 lpuart_dma_tx(sport);
656 } else {
657 temp = lpuart32_read(port, UARTCTRL);
658 lpuart32_write(port, temp | UARTCTRL_TIE, UARTCTRL);
659
660 if (lpuart32_read(port, UARTSTAT) & UARTSTAT_TDRE)
661 lpuart32_transmit_buffer(sport);
662 }
663 }
664
665 /* return TIOCSER_TEMT when transmitter is not busy */
666 static unsigned int lpuart_tx_empty(struct uart_port *port)
667 {
668 struct lpuart_port *sport = container_of(port,
669 struct lpuart_port, port);
670 unsigned char sr1 = readb(port->membase + UARTSR1);
671 unsigned char sfifo = readb(port->membase + UARTSFIFO);
672
673 if (sport->dma_tx_in_progress)
674 return 0;
675
676 if (sr1 & UARTSR1_TC && sfifo & UARTSFIFO_TXEMPT)
677 return TIOCSER_TEMT;
678
679 return 0;
680 }
681
682 static unsigned int lpuart32_tx_empty(struct uart_port *port)
683 {
684 struct lpuart_port *sport = container_of(port,
685 struct lpuart_port, port);
686 unsigned long stat = lpuart32_read(port, UARTSTAT);
687 unsigned long sfifo = lpuart32_read(port, UARTFIFO);
688
689 if (sport->dma_tx_in_progress)
690 return 0;
691
692 if (stat & UARTSTAT_TC && sfifo & UARTFIFO_TXEMPT)
693 return TIOCSER_TEMT;
694
695 return 0;
696 }
697
698 static bool lpuart_is_32(struct lpuart_port *sport)
699 {
700 return sport->port.iotype == UPIO_MEM32 ||
701 sport->port.iotype == UPIO_MEM32BE;
702 }
703
704 static irqreturn_t lpuart_txint(int irq, void *dev_id)
705 {
706 struct lpuart_port *sport = dev_id;
707 struct circ_buf *xmit = &sport->port.state->xmit;
708 unsigned long flags;
709
710 spin_lock_irqsave(&sport->port.lock, flags);
711 if (sport->port.x_char) {
712 if (lpuart_is_32(sport))
713 lpuart32_write(&sport->port, sport->port.x_char, UARTDATA);
714 else
715 writeb(sport->port.x_char, sport->port.membase + UARTDR);
716 goto out;
717 }
718
719 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
720 if (lpuart_is_32(sport))
721 lpuart32_stop_tx(&sport->port);
722 else
723 lpuart_stop_tx(&sport->port);
724 goto out;
725 }
726
727 if (lpuart_is_32(sport))
728 lpuart32_transmit_buffer(sport);
729 else
730 lpuart_transmit_buffer(sport);
731
732 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
733 uart_write_wakeup(&sport->port);
734
735 out:
736 spin_unlock_irqrestore(&sport->port.lock, flags);
737 return IRQ_HANDLED;
738 }
739
740 static irqreturn_t lpuart_rxint(int irq, void *dev_id)
741 {
742 struct lpuart_port *sport = dev_id;
743 unsigned int flg, ignored = 0;
744 struct tty_port *port = &sport->port.state->port;
745 unsigned long flags;
746 unsigned char rx, sr;
747
748 spin_lock_irqsave(&sport->port.lock, flags);
749
750 while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) {
751 flg = TTY_NORMAL;
752 sport->port.icount.rx++;
753 /*
754 * to clear the FE, OR, NF, FE, PE flags,
755 * read SR1 then read DR
756 */
757 sr = readb(sport->port.membase + UARTSR1);
758 rx = readb(sport->port.membase + UARTDR);
759
760 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
761 continue;
762
763 if (sr & (UARTSR1_PE | UARTSR1_OR | UARTSR1_FE)) {
764 if (sr & UARTSR1_PE)
765 sport->port.icount.parity++;
766 else if (sr & UARTSR1_FE)
767 sport->port.icount.frame++;
768
769 if (sr & UARTSR1_OR)
770 sport->port.icount.overrun++;
771
772 if (sr & sport->port.ignore_status_mask) {
773 if (++ignored > 100)
774 goto out;
775 continue;
776 }
777
778 sr &= sport->port.read_status_mask;
779
780 if (sr & UARTSR1_PE)
781 flg = TTY_PARITY;
782 else if (sr & UARTSR1_FE)
783 flg = TTY_FRAME;
784
785 if (sr & UARTSR1_OR)
786 flg = TTY_OVERRUN;
787
788 #ifdef SUPPORT_SYSRQ
789 sport->port.sysrq = 0;
790 #endif
791 }
792
793 tty_insert_flip_char(port, rx, flg);
794 }
795
796 out:
797 spin_unlock_irqrestore(&sport->port.lock, flags);
798
799 tty_flip_buffer_push(port);
800 return IRQ_HANDLED;
801 }
802
803 static irqreturn_t lpuart32_rxint(int irq, void *dev_id)
804 {
805 struct lpuart_port *sport = dev_id;
806 unsigned int flg, ignored = 0;
807 struct tty_port *port = &sport->port.state->port;
808 unsigned long flags;
809 unsigned long rx, sr;
810
811 spin_lock_irqsave(&sport->port.lock, flags);
812
813 while (!(lpuart32_read(&sport->port, UARTFIFO) & UARTFIFO_RXEMPT)) {
814 flg = TTY_NORMAL;
815 sport->port.icount.rx++;
816 /*
817 * to clear the FE, OR, NF, FE, PE flags,
818 * read STAT then read DATA reg
819 */
820 sr = lpuart32_read(&sport->port, UARTSTAT);
821 rx = lpuart32_read(&sport->port, UARTDATA);
822 rx &= 0x3ff;
823
824 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
825 continue;
826
827 if (sr & (UARTSTAT_PE | UARTSTAT_OR | UARTSTAT_FE)) {
828 if (sr & UARTSTAT_PE)
829 sport->port.icount.parity++;
830 else if (sr & UARTSTAT_FE)
831 sport->port.icount.frame++;
832
833 if (sr & UARTSTAT_OR)
834 sport->port.icount.overrun++;
835
836 if (sr & sport->port.ignore_status_mask) {
837 if (++ignored > 100)
838 goto out;
839 continue;
840 }
841
842 sr &= sport->port.read_status_mask;
843
844 if (sr & UARTSTAT_PE)
845 flg = TTY_PARITY;
846 else if (sr & UARTSTAT_FE)
847 flg = TTY_FRAME;
848
849 if (sr & UARTSTAT_OR)
850 flg = TTY_OVERRUN;
851
852 #ifdef SUPPORT_SYSRQ
853 sport->port.sysrq = 0;
854 #endif
855 }
856
857 tty_insert_flip_char(port, rx, flg);
858 }
859
860 out:
861 spin_unlock_irqrestore(&sport->port.lock, flags);
862
863 tty_flip_buffer_push(port);
864 return IRQ_HANDLED;
865 }
866
867 static irqreturn_t lpuart_int(int irq, void *dev_id)
868 {
869 struct lpuart_port *sport = dev_id;
870 unsigned char sts;
871
872 sts = readb(sport->port.membase + UARTSR1);
873
874 if (sts & UARTSR1_RDRF)
875 lpuart_rxint(irq, dev_id);
876
877 if (sts & UARTSR1_TDRE)
878 lpuart_txint(irq, dev_id);
879
880 return IRQ_HANDLED;
881 }
882
883 static irqreturn_t lpuart32_int(int irq, void *dev_id)
884 {
885 struct lpuart_port *sport = dev_id;
886 unsigned long sts, rxcount;
887
888 sts = lpuart32_read(&sport->port, UARTSTAT);
889 rxcount = lpuart32_read(&sport->port, UARTWATER);
890 rxcount = rxcount >> UARTWATER_RXCNT_OFF;
891
892 if ((sts & UARTSTAT_RDRF || rxcount > 0) && !sport->lpuart_dma_rx_use)
893 lpuart32_rxint(irq, dev_id);
894
895 if ((sts & UARTSTAT_TDRE) && !sport->lpuart_dma_tx_use)
896 lpuart_txint(irq, dev_id);
897
898 lpuart32_write(&sport->port, sts, UARTSTAT);
899 return IRQ_HANDLED;
900 }
901
902 static void lpuart_copy_rx_to_tty(struct lpuart_port *sport)
903 {
904 struct tty_port *port = &sport->port.state->port;
905 struct dma_tx_state state;
906 enum dma_status dmastat;
907 struct circ_buf *ring = &sport->rx_ring;
908 unsigned long flags;
909 int count = 0;
910
911 if (lpuart_is_32(sport)) {
912 unsigned long sr = lpuart32_read(&sport->port, UARTSTAT);
913
914 if (sr & (UARTSTAT_PE | UARTSTAT_FE)) {
915 /* Read DR to clear the error flags */
916 lpuart32_read(&sport->port, UARTDATA);
917
918 if (sr & UARTSTAT_PE)
919 sport->port.icount.parity++;
920 else if (sr & UARTSTAT_FE)
921 sport->port.icount.frame++;
922 }
923 } else {
924 unsigned char sr = readb(sport->port.membase + UARTSR1);
925
926 if (sr & (UARTSR1_PE | UARTSR1_FE)) {
927 /* Read DR to clear the error flags */
928 readb(sport->port.membase + UARTDR);
929
930 if (sr & UARTSR1_PE)
931 sport->port.icount.parity++;
932 else if (sr & UARTSR1_FE)
933 sport->port.icount.frame++;
934 }
935 }
936
937 async_tx_ack(sport->dma_rx_desc);
938
939 spin_lock_irqsave(&sport->port.lock, flags);
940
941 dmastat = dmaengine_tx_status(sport->dma_rx_chan,
942 sport->dma_rx_cookie,
943 &state);
944
945 if (dmastat == DMA_ERROR) {
946 dev_err(sport->port.dev, "Rx DMA transfer failed!\n");
947 spin_unlock_irqrestore(&sport->port.lock, flags);
948 return;
949 }
950
951 /* CPU claims ownership of RX DMA buffer */
952 dma_sync_sg_for_cpu(sport->port.dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE);
953
954 /*
955 * ring->head points to the end of data already written by the DMA.
956 * ring->tail points to the beginning of data to be read by the
957 * framework.
958 * The current transfer size should not be larger than the dma buffer
959 * length.
960 */
961 ring->head = sport->rx_sgl.length - state.residue;
962 BUG_ON(ring->head > sport->rx_sgl.length);
963 /*
964 * At this point ring->head may point to the first byte right after the
965 * last byte of the dma buffer:
966 * 0 <= ring->head <= sport->rx_sgl.length
967 *
968 * However ring->tail must always points inside the dma buffer:
969 * 0 <= ring->tail <= sport->rx_sgl.length - 1
970 *
971 * Since we use a ring buffer, we have to handle the case
972 * where head is lower than tail. In such a case, we first read from
973 * tail to the end of the buffer then reset tail.
974 */
975 if (ring->head < ring->tail) {
976 count = sport->rx_sgl.length - ring->tail;
977
978 tty_insert_flip_string(port, ring->buf + ring->tail, count);
979 ring->tail = 0;
980 sport->port.icount.rx += count;
981 }
982
983 /* Finally we read data from tail to head */
984 if (ring->tail < ring->head) {
985 count = ring->head - ring->tail;
986 tty_insert_flip_string(port, ring->buf + ring->tail, count);
987 /* Wrap ring->head if needed */
988 if (ring->head >= sport->rx_sgl.length)
989 ring->head = 0;
990 ring->tail = ring->head;
991 sport->port.icount.rx += count;
992 }
993
994 dma_sync_sg_for_device(sport->port.dev, &sport->rx_sgl, 1,
995 DMA_FROM_DEVICE);
996
997 spin_unlock_irqrestore(&sport->port.lock, flags);
998
999 tty_flip_buffer_push(port);
1000 mod_timer(&sport->lpuart_timer, jiffies + sport->dma_rx_timeout);
1001 }
1002
1003 static void lpuart_dma_rx_complete(void *arg)
1004 {
1005 struct lpuart_port *sport = arg;
1006
1007 lpuart_copy_rx_to_tty(sport);
1008 }
1009
1010 static void lpuart_timer_func(struct timer_list *t)
1011 {
1012 struct lpuart_port *sport = from_timer(sport, t, lpuart_timer);
1013
1014 lpuart_copy_rx_to_tty(sport);
1015 }
1016
1017 static inline int lpuart_start_rx_dma(struct lpuart_port *sport)
1018 {
1019 struct dma_slave_config dma_rx_sconfig = {};
1020 struct circ_buf *ring = &sport->rx_ring;
1021 int ret, nent;
1022 int bits, baud;
1023 struct tty_port *port = &sport->port.state->port;
1024 struct tty_struct *tty = port->tty;
1025 struct ktermios *termios = &tty->termios;
1026
1027 baud = tty_get_baud_rate(tty);
1028
1029 bits = (termios->c_cflag & CSIZE) == CS7 ? 9 : 10;
1030 if (termios->c_cflag & PARENB)
1031 bits++;
1032
1033 /*
1034 * Calculate length of one DMA buffer size to keep latency below
1035 * 10ms at any baud rate.
1036 */
1037 sport->rx_dma_rng_buf_len = (DMA_RX_TIMEOUT * baud / bits / 1000) * 2;
1038 sport->rx_dma_rng_buf_len = (1 << (fls(sport->rx_dma_rng_buf_len) - 1));
1039 if (sport->rx_dma_rng_buf_len < 16)
1040 sport->rx_dma_rng_buf_len = 16;
1041
1042 ring->buf = kmalloc(sport->rx_dma_rng_buf_len, GFP_ATOMIC);
1043 if (!ring->buf) {
1044 dev_err(sport->port.dev, "Ring buf alloc failed\n");
1045 return -ENOMEM;
1046 }
1047
1048 sg_init_one(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len);
1049 sg_set_buf(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len);
1050 nent = dma_map_sg(sport->port.dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE);
1051
1052 if (!nent) {
1053 dev_err(sport->port.dev, "DMA Rx mapping error\n");
1054 return -EINVAL;
1055 }
1056
1057 dma_rx_sconfig.src_addr = lpuart_dma_datareg_addr(sport);
1058 dma_rx_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1059 dma_rx_sconfig.src_maxburst = 1;
1060 dma_rx_sconfig.direction = DMA_DEV_TO_MEM;
1061 ret = dmaengine_slave_config(sport->dma_rx_chan, &dma_rx_sconfig);
1062
1063 if (ret < 0) {
1064 dev_err(sport->port.dev,
1065 "DMA Rx slave config failed, err = %d\n", ret);
1066 return ret;
1067 }
1068
1069 sport->dma_rx_desc = dmaengine_prep_dma_cyclic(sport->dma_rx_chan,
1070 sg_dma_address(&sport->rx_sgl),
1071 sport->rx_sgl.length,
1072 sport->rx_sgl.length / 2,
1073 DMA_DEV_TO_MEM,
1074 DMA_PREP_INTERRUPT);
1075 if (!sport->dma_rx_desc) {
1076 dev_err(sport->port.dev, "Cannot prepare cyclic DMA\n");
1077 return -EFAULT;
1078 }
1079
1080 sport->dma_rx_desc->callback = lpuart_dma_rx_complete;
1081 sport->dma_rx_desc->callback_param = sport;
1082 sport->dma_rx_cookie = dmaengine_submit(sport->dma_rx_desc);
1083 dma_async_issue_pending(sport->dma_rx_chan);
1084
1085 if (lpuart_is_32(sport)) {
1086 unsigned long temp = lpuart32_read(&sport->port, UARTBAUD);
1087
1088 lpuart32_write(&sport->port, temp | UARTBAUD_RDMAE, UARTBAUD);
1089 } else {
1090 writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_RDMAS,
1091 sport->port.membase + UARTCR5);
1092 }
1093
1094 return 0;
1095 }
1096
1097 static void lpuart_dma_rx_free(struct uart_port *port)
1098 {
1099 struct lpuart_port *sport = container_of(port,
1100 struct lpuart_port, port);
1101
1102 if (sport->dma_rx_chan)
1103 dmaengine_terminate_all(sport->dma_rx_chan);
1104
1105 dma_unmap_sg(sport->port.dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE);
1106 kfree(sport->rx_ring.buf);
1107 sport->rx_ring.tail = 0;
1108 sport->rx_ring.head = 0;
1109 sport->dma_rx_desc = NULL;
1110 sport->dma_rx_cookie = -EINVAL;
1111 }
1112
1113 static int lpuart_config_rs485(struct uart_port *port,
1114 struct serial_rs485 *rs485)
1115 {
1116 struct lpuart_port *sport = container_of(port,
1117 struct lpuart_port, port);
1118
1119 u8 modem = readb(sport->port.membase + UARTMODEM) &
1120 ~(UARTMODEM_TXRTSPOL | UARTMODEM_TXRTSE);
1121 writeb(modem, sport->port.membase + UARTMODEM);
1122
1123 /* clear unsupported configurations */
1124 rs485->delay_rts_before_send = 0;
1125 rs485->delay_rts_after_send = 0;
1126 rs485->flags &= ~SER_RS485_RX_DURING_TX;
1127
1128 if (rs485->flags & SER_RS485_ENABLED) {
1129 /* Enable auto RS-485 RTS mode */
1130 modem |= UARTMODEM_TXRTSE;
1131
1132 /*
1133 * RTS needs to be logic HIGH either during transer _or_ after
1134 * transfer, other variants are not supported by the hardware.
1135 */
1136
1137 if (!(rs485->flags & (SER_RS485_RTS_ON_SEND |
1138 SER_RS485_RTS_AFTER_SEND)))
1139 rs485->flags |= SER_RS485_RTS_ON_SEND;
1140
1141 if (rs485->flags & SER_RS485_RTS_ON_SEND &&
1142 rs485->flags & SER_RS485_RTS_AFTER_SEND)
1143 rs485->flags &= ~SER_RS485_RTS_AFTER_SEND;
1144
1145 /*
1146 * The hardware defaults to RTS logic HIGH while transfer.
1147 * Switch polarity in case RTS shall be logic HIGH
1148 * after transfer.
1149 * Note: UART is assumed to be active high.
1150 */
1151 if (rs485->flags & SER_RS485_RTS_ON_SEND)
1152 modem &= ~UARTMODEM_TXRTSPOL;
1153 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND)
1154 modem |= UARTMODEM_TXRTSPOL;
1155 }
1156
1157 /* Store the new configuration */
1158 sport->port.rs485 = *rs485;
1159
1160 writeb(modem, sport->port.membase + UARTMODEM);
1161 return 0;
1162 }
1163
1164 static unsigned int lpuart_get_mctrl(struct uart_port *port)
1165 {
1166 unsigned int temp = 0;
1167 unsigned char reg;
1168
1169 reg = readb(port->membase + UARTMODEM);
1170 if (reg & UARTMODEM_TXCTSE)
1171 temp |= TIOCM_CTS;
1172
1173 if (reg & UARTMODEM_RXRTSE)
1174 temp |= TIOCM_RTS;
1175
1176 return temp;
1177 }
1178
1179 static unsigned int lpuart32_get_mctrl(struct uart_port *port)
1180 {
1181 unsigned int temp = 0;
1182 unsigned long reg;
1183
1184 reg = lpuart32_read(port, UARTMODIR);
1185 if (reg & UARTMODIR_TXCTSE)
1186 temp |= TIOCM_CTS;
1187
1188 if (reg & UARTMODIR_RXRTSE)
1189 temp |= TIOCM_RTS;
1190
1191 return temp;
1192 }
1193
1194 static void lpuart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1195 {
1196 unsigned char temp;
1197 struct lpuart_port *sport = container_of(port,
1198 struct lpuart_port, port);
1199
1200 /* Make sure RXRTSE bit is not set when RS485 is enabled */
1201 if (!(sport->port.rs485.flags & SER_RS485_ENABLED)) {
1202 temp = readb(sport->port.membase + UARTMODEM) &
1203 ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1204
1205 if (mctrl & TIOCM_RTS)
1206 temp |= UARTMODEM_RXRTSE;
1207
1208 if (mctrl & TIOCM_CTS)
1209 temp |= UARTMODEM_TXCTSE;
1210
1211 writeb(temp, port->membase + UARTMODEM);
1212 }
1213 }
1214
1215 static void lpuart32_set_mctrl(struct uart_port *port, unsigned int mctrl)
1216 {
1217 unsigned long temp;
1218
1219 temp = lpuart32_read(port, UARTMODIR) &
1220 ~(UARTMODIR_RXRTSE | UARTMODIR_TXCTSE);
1221
1222 if (mctrl & TIOCM_RTS)
1223 temp |= UARTMODIR_RXRTSE;
1224
1225 if (mctrl & TIOCM_CTS)
1226 temp |= UARTMODIR_TXCTSE;
1227
1228 lpuart32_write(port, temp, UARTMODIR);
1229 }
1230
1231 static void lpuart_break_ctl(struct uart_port *port, int break_state)
1232 {
1233 unsigned char temp;
1234
1235 temp = readb(port->membase + UARTCR2) & ~UARTCR2_SBK;
1236
1237 if (break_state != 0)
1238 temp |= UARTCR2_SBK;
1239
1240 writeb(temp, port->membase + UARTCR2);
1241 }
1242
1243 static void lpuart32_break_ctl(struct uart_port *port, int break_state)
1244 {
1245 unsigned long temp;
1246
1247 temp = lpuart32_read(port, UARTCTRL) & ~UARTCTRL_SBK;
1248
1249 if (break_state != 0)
1250 temp |= UARTCTRL_SBK;
1251
1252 lpuart32_write(port, temp, UARTCTRL);
1253 }
1254
1255 static void lpuart_setup_watermark(struct lpuart_port *sport)
1256 {
1257 unsigned char val, cr2;
1258 unsigned char cr2_saved;
1259
1260 cr2 = readb(sport->port.membase + UARTCR2);
1261 cr2_saved = cr2;
1262 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_TE |
1263 UARTCR2_RIE | UARTCR2_RE);
1264 writeb(cr2, sport->port.membase + UARTCR2);
1265
1266 val = readb(sport->port.membase + UARTPFIFO);
1267 writeb(val | UARTPFIFO_TXFE | UARTPFIFO_RXFE,
1268 sport->port.membase + UARTPFIFO);
1269
1270 /* flush Tx and Rx FIFO */
1271 writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH,
1272 sport->port.membase + UARTCFIFO);
1273
1274 /* explicitly clear RDRF */
1275 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) {
1276 readb(sport->port.membase + UARTDR);
1277 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO);
1278 }
1279
1280 writeb(0, sport->port.membase + UARTTWFIFO);
1281 writeb(1, sport->port.membase + UARTRWFIFO);
1282
1283 /* Restore cr2 */
1284 writeb(cr2_saved, sport->port.membase + UARTCR2);
1285 }
1286
1287 static void lpuart32_setup_watermark(struct lpuart_port *sport)
1288 {
1289 unsigned long val, ctrl;
1290 unsigned long ctrl_saved;
1291
1292 ctrl = lpuart32_read(&sport->port, UARTCTRL);
1293 ctrl_saved = ctrl;
1294 ctrl &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_TE |
1295 UARTCTRL_RIE | UARTCTRL_RE);
1296 lpuart32_write(&sport->port, ctrl, UARTCTRL);
1297
1298 /* enable FIFO mode */
1299 val = lpuart32_read(&sport->port, UARTFIFO);
1300 val |= UARTFIFO_TXFE | UARTFIFO_RXFE;
1301 val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH;
1302 lpuart32_write(&sport->port, val, UARTFIFO);
1303
1304 /* set the watermark */
1305 val = (0x1 << UARTWATER_RXWATER_OFF) | (0x0 << UARTWATER_TXWATER_OFF);
1306 lpuart32_write(&sport->port, val, UARTWATER);
1307
1308 /* Restore cr2 */
1309 lpuart32_write(&sport->port, ctrl_saved, UARTCTRL);
1310 }
1311
1312 static void rx_dma_timer_init(struct lpuart_port *sport)
1313 {
1314 timer_setup(&sport->lpuart_timer, lpuart_timer_func, 0);
1315 sport->lpuart_timer.expires = jiffies + sport->dma_rx_timeout;
1316 add_timer(&sport->lpuart_timer);
1317 }
1318
1319 static int lpuart_startup(struct uart_port *port)
1320 {
1321 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1322 unsigned long flags;
1323 unsigned char temp;
1324
1325 /* determine FIFO size and enable FIFO mode */
1326 temp = readb(sport->port.membase + UARTPFIFO);
1327
1328 sport->txfifo_size = 0x1 << (((temp >> UARTPFIFO_TXSIZE_OFF) &
1329 UARTPFIFO_FIFOSIZE_MASK) + 1);
1330
1331 sport->port.fifosize = sport->txfifo_size;
1332
1333 sport->rxfifo_size = 0x1 << (((temp >> UARTPFIFO_RXSIZE_OFF) &
1334 UARTPFIFO_FIFOSIZE_MASK) + 1);
1335
1336 spin_lock_irqsave(&sport->port.lock, flags);
1337
1338 lpuart_setup_watermark(sport);
1339
1340 temp = readb(sport->port.membase + UARTCR2);
1341 temp |= (UARTCR2_RIE | UARTCR2_TIE | UARTCR2_RE | UARTCR2_TE);
1342 writeb(temp, sport->port.membase + UARTCR2);
1343
1344 if (sport->dma_rx_chan && !lpuart_start_rx_dma(sport)) {
1345 /* set Rx DMA timeout */
1346 sport->dma_rx_timeout = msecs_to_jiffies(DMA_RX_TIMEOUT);
1347 if (!sport->dma_rx_timeout)
1348 sport->dma_rx_timeout = 1;
1349
1350 sport->lpuart_dma_rx_use = true;
1351 rx_dma_timer_init(sport);
1352 } else {
1353 sport->lpuart_dma_rx_use = false;
1354 }
1355
1356 if (sport->dma_tx_chan && !lpuart_dma_tx_request(port)) {
1357 init_waitqueue_head(&sport->dma_wait);
1358 sport->lpuart_dma_tx_use = true;
1359 temp = readb(port->membase + UARTCR5);
1360 writeb(temp | UARTCR5_TDMAS, port->membase + UARTCR5);
1361 } else {
1362 sport->lpuart_dma_tx_use = false;
1363 }
1364
1365 spin_unlock_irqrestore(&sport->port.lock, flags);
1366
1367 return 0;
1368 }
1369
1370 static int lpuart32_startup(struct uart_port *port)
1371 {
1372 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1373 unsigned long flags;
1374 unsigned long temp;
1375
1376 /* determine FIFO size */
1377 temp = lpuart32_read(&sport->port, UARTFIFO);
1378
1379 sport->txfifo_size = 0x1 << (((temp >> UARTFIFO_TXSIZE_OFF) &
1380 UARTFIFO_FIFOSIZE_MASK) - 1);
1381
1382 sport->port.fifosize = sport->txfifo_size;
1383
1384 sport->rxfifo_size = 0x1 << (((temp >> UARTFIFO_RXSIZE_OFF) &
1385 UARTFIFO_FIFOSIZE_MASK) - 1);
1386
1387 spin_lock_irqsave(&sport->port.lock, flags);
1388
1389 lpuart32_setup_watermark(sport);
1390
1391 temp = lpuart32_read(&sport->port, UARTCTRL);
1392 temp |= UARTCTRL_RE | UARTCTRL_TE | UARTCTRL_ILIE;
1393 lpuart32_write(&sport->port, temp, UARTCTRL);
1394
1395 if (sport->dma_rx_chan && !lpuart_start_rx_dma(sport)) {
1396 /* set Rx DMA timeout */
1397 sport->dma_rx_timeout = msecs_to_jiffies(DMA_RX_TIMEOUT);
1398 if (!sport->dma_rx_timeout)
1399 sport->dma_rx_timeout = 1;
1400
1401 sport->lpuart_dma_rx_use = true;
1402 rx_dma_timer_init(sport);
1403 } else {
1404 sport->lpuart_dma_rx_use = false;
1405 }
1406
1407 if (sport->dma_tx_chan && !lpuart_dma_tx_request(port)) {
1408 init_waitqueue_head(&sport->dma_wait);
1409 sport->lpuart_dma_tx_use = true;
1410 temp = lpuart32_read(&sport->port, UARTBAUD);
1411 lpuart32_write(&sport->port, temp | UARTBAUD_TDMAE, UARTBAUD);
1412 } else {
1413 sport->lpuart_dma_tx_use = false;
1414 }
1415
1416 if (sport->lpuart_dma_rx_use) {
1417 /* RXWATER must be 0 */
1418 temp = lpuart32_read(&sport->port, UARTWATER);
1419 temp &= ~(UARTWATER_WATER_MASK << UARTWATER_RXWATER_OFF);
1420 lpuart32_write(&sport->port, temp, UARTWATER);
1421 }
1422 temp = lpuart32_read(&sport->port, UARTCTRL);
1423 if (!sport->lpuart_dma_rx_use)
1424 temp |= UARTCTRL_RIE;
1425 if (!sport->lpuart_dma_tx_use)
1426 temp |= UARTCTRL_TIE;
1427 lpuart32_write(&sport->port, temp, UARTCTRL);
1428
1429 spin_unlock_irqrestore(&sport->port.lock, flags);
1430 return 0;
1431 }
1432
1433 static void lpuart_shutdown(struct uart_port *port)
1434 {
1435 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1436 unsigned char temp;
1437 unsigned long flags;
1438
1439 spin_lock_irqsave(&port->lock, flags);
1440
1441 /* disable Rx/Tx and interrupts */
1442 temp = readb(port->membase + UARTCR2);
1443 temp &= ~(UARTCR2_TE | UARTCR2_RE |
1444 UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
1445 writeb(temp, port->membase + UARTCR2);
1446
1447 spin_unlock_irqrestore(&port->lock, flags);
1448
1449 if (sport->lpuart_dma_rx_use) {
1450 del_timer_sync(&sport->lpuart_timer);
1451 lpuart_dma_rx_free(&sport->port);
1452 }
1453
1454 if (sport->lpuart_dma_tx_use) {
1455 if (wait_event_interruptible(sport->dma_wait,
1456 !sport->dma_tx_in_progress) != false) {
1457 sport->dma_tx_in_progress = false;
1458 dmaengine_terminate_all(sport->dma_tx_chan);
1459 }
1460
1461 lpuart_stop_tx(port);
1462 }
1463 }
1464
1465 static void lpuart32_shutdown(struct uart_port *port)
1466 {
1467 struct lpuart_port *sport =
1468 container_of(port, struct lpuart_port, port);
1469 unsigned long temp;
1470 unsigned long flags;
1471
1472 spin_lock_irqsave(&port->lock, flags);
1473
1474 /* disable Rx/Tx and interrupts */
1475 temp = lpuart32_read(port, UARTCTRL);
1476 temp &= ~(UARTCTRL_TE | UARTCTRL_RE |
1477 UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE);
1478 lpuart32_write(port, temp, UARTCTRL);
1479
1480 spin_unlock_irqrestore(&port->lock, flags);
1481
1482 if (sport->lpuart_dma_rx_use) {
1483 del_timer_sync(&sport->lpuart_timer);
1484 lpuart_dma_rx_free(&sport->port);
1485 }
1486
1487 if (sport->lpuart_dma_tx_use) {
1488 if (wait_event_interruptible(sport->dma_wait,
1489 !sport->dma_tx_in_progress)) {
1490 sport->dma_tx_in_progress = false;
1491 dmaengine_terminate_all(sport->dma_tx_chan);
1492 }
1493
1494 lpuart32_stop_tx(port);
1495 }
1496 }
1497
1498 static void
1499 lpuart_set_termios(struct uart_port *port, struct ktermios *termios,
1500 struct ktermios *old)
1501 {
1502 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1503 unsigned long flags;
1504 unsigned char cr1, old_cr1, old_cr2, cr3, cr4, bdh, modem;
1505 unsigned int baud;
1506 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1507 unsigned int sbr, brfa;
1508
1509 cr1 = old_cr1 = readb(sport->port.membase + UARTCR1);
1510 old_cr2 = readb(sport->port.membase + UARTCR2);
1511 cr3 = readb(sport->port.membase + UARTCR3);
1512 cr4 = readb(sport->port.membase + UARTCR4);
1513 bdh = readb(sport->port.membase + UARTBDH);
1514 modem = readb(sport->port.membase + UARTMODEM);
1515 /*
1516 * only support CS8 and CS7, and for CS7 must enable PE.
1517 * supported mode:
1518 * - (7,e/o,1)
1519 * - (8,n,1)
1520 * - (8,m/s,1)
1521 * - (8,e/o,1)
1522 */
1523 while ((termios->c_cflag & CSIZE) != CS8 &&
1524 (termios->c_cflag & CSIZE) != CS7) {
1525 termios->c_cflag &= ~CSIZE;
1526 termios->c_cflag |= old_csize;
1527 old_csize = CS8;
1528 }
1529
1530 if ((termios->c_cflag & CSIZE) == CS8 ||
1531 (termios->c_cflag & CSIZE) == CS7)
1532 cr1 = old_cr1 & ~UARTCR1_M;
1533
1534 if (termios->c_cflag & CMSPAR) {
1535 if ((termios->c_cflag & CSIZE) != CS8) {
1536 termios->c_cflag &= ~CSIZE;
1537 termios->c_cflag |= CS8;
1538 }
1539 cr1 |= UARTCR1_M;
1540 }
1541
1542 /*
1543 * When auto RS-485 RTS mode is enabled,
1544 * hardware flow control need to be disabled.
1545 */
1546 if (sport->port.rs485.flags & SER_RS485_ENABLED)
1547 termios->c_cflag &= ~CRTSCTS;
1548
1549 if (termios->c_cflag & CRTSCTS) {
1550 modem |= (UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1551 } else {
1552 termios->c_cflag &= ~CRTSCTS;
1553 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1554 }
1555
1556 if (termios->c_cflag & CSTOPB)
1557 termios->c_cflag &= ~CSTOPB;
1558
1559 /* parity must be enabled when CS7 to match 8-bits format */
1560 if ((termios->c_cflag & CSIZE) == CS7)
1561 termios->c_cflag |= PARENB;
1562
1563 if ((termios->c_cflag & PARENB)) {
1564 if (termios->c_cflag & CMSPAR) {
1565 cr1 &= ~UARTCR1_PE;
1566 if (termios->c_cflag & PARODD)
1567 cr3 |= UARTCR3_T8;
1568 else
1569 cr3 &= ~UARTCR3_T8;
1570 } else {
1571 cr1 |= UARTCR1_PE;
1572 if ((termios->c_cflag & CSIZE) == CS8)
1573 cr1 |= UARTCR1_M;
1574 if (termios->c_cflag & PARODD)
1575 cr1 |= UARTCR1_PT;
1576 else
1577 cr1 &= ~UARTCR1_PT;
1578 }
1579 } else {
1580 cr1 &= ~UARTCR1_PE;
1581 }
1582
1583 /* ask the core to calculate the divisor */
1584 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1585
1586 /*
1587 * Need to update the Ring buffer length according to the selected
1588 * baud rate and restart Rx DMA path.
1589 *
1590 * Since timer function acqures sport->port.lock, need to stop before
1591 * acquring same lock because otherwise del_timer_sync() can deadlock.
1592 */
1593 if (old && sport->lpuart_dma_rx_use) {
1594 del_timer_sync(&sport->lpuart_timer);
1595 lpuart_dma_rx_free(&sport->port);
1596 }
1597
1598 spin_lock_irqsave(&sport->port.lock, flags);
1599
1600 sport->port.read_status_mask = 0;
1601 if (termios->c_iflag & INPCK)
1602 sport->port.read_status_mask |= (UARTSR1_FE | UARTSR1_PE);
1603 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1604 sport->port.read_status_mask |= UARTSR1_FE;
1605
1606 /* characters to ignore */
1607 sport->port.ignore_status_mask = 0;
1608 if (termios->c_iflag & IGNPAR)
1609 sport->port.ignore_status_mask |= UARTSR1_PE;
1610 if (termios->c_iflag & IGNBRK) {
1611 sport->port.ignore_status_mask |= UARTSR1_FE;
1612 /*
1613 * if we're ignoring parity and break indicators,
1614 * ignore overruns too (for real raw support).
1615 */
1616 if (termios->c_iflag & IGNPAR)
1617 sport->port.ignore_status_mask |= UARTSR1_OR;
1618 }
1619
1620 /* update the per-port timeout */
1621 uart_update_timeout(port, termios->c_cflag, baud);
1622
1623 /* wait transmit engin complete */
1624 while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC))
1625 barrier();
1626
1627 /* disable transmit and receive */
1628 writeb(old_cr2 & ~(UARTCR2_TE | UARTCR2_RE),
1629 sport->port.membase + UARTCR2);
1630
1631 sbr = sport->port.uartclk / (16 * baud);
1632 brfa = ((sport->port.uartclk - (16 * sbr * baud)) * 2) / baud;
1633 bdh &= ~UARTBDH_SBR_MASK;
1634 bdh |= (sbr >> 8) & 0x1F;
1635 cr4 &= ~UARTCR4_BRFA_MASK;
1636 brfa &= UARTCR4_BRFA_MASK;
1637 writeb(cr4 | brfa, sport->port.membase + UARTCR4);
1638 writeb(bdh, sport->port.membase + UARTBDH);
1639 writeb(sbr & 0xFF, sport->port.membase + UARTBDL);
1640 writeb(cr3, sport->port.membase + UARTCR3);
1641 writeb(cr1, sport->port.membase + UARTCR1);
1642 writeb(modem, sport->port.membase + UARTMODEM);
1643
1644 /* restore control register */
1645 writeb(old_cr2, sport->port.membase + UARTCR2);
1646
1647 if (old && sport->lpuart_dma_rx_use) {
1648 if (!lpuart_start_rx_dma(sport))
1649 rx_dma_timer_init(sport);
1650 else
1651 sport->lpuart_dma_rx_use = false;
1652 }
1653
1654 spin_unlock_irqrestore(&sport->port.lock, flags);
1655 }
1656
1657 static void
1658 lpuart32_serial_setbrg(struct lpuart_port *sport, unsigned int baudrate)
1659 {
1660 u32 sbr, osr, baud_diff, tmp_osr, tmp_sbr, tmp_diff, tmp;
1661 u32 clk = sport->port.uartclk;
1662
1663 /*
1664 * The idea is to use the best OSR (over-sampling rate) possible.
1665 * Note, OSR is typically hard-set to 16 in other LPUART instantiations.
1666 * Loop to find the best OSR value possible, one that generates minimum
1667 * baud_diff iterate through the rest of the supported values of OSR.
1668 *
1669 * Calculation Formula:
1670 * Baud Rate = baud clock / ((OSR+1) × SBR)
1671 */
1672 baud_diff = baudrate;
1673 osr = 0;
1674 sbr = 0;
1675
1676 for (tmp_osr = 4; tmp_osr <= 32; tmp_osr++) {
1677 /* calculate the temporary sbr value */
1678 tmp_sbr = (clk / (baudrate * tmp_osr));
1679 if (tmp_sbr == 0)
1680 tmp_sbr = 1;
1681
1682 /*
1683 * calculate the baud rate difference based on the temporary
1684 * osr and sbr values
1685 */
1686 tmp_diff = clk / (tmp_osr * tmp_sbr) - baudrate;
1687
1688 /* select best values between sbr and sbr+1 */
1689 tmp = clk / (tmp_osr * (tmp_sbr + 1));
1690 if (tmp_diff > (baudrate - tmp)) {
1691 tmp_diff = baudrate - tmp;
1692 tmp_sbr++;
1693 }
1694
1695 if (tmp_diff <= baud_diff) {
1696 baud_diff = tmp_diff;
1697 osr = tmp_osr;
1698 sbr = tmp_sbr;
1699
1700 if (!baud_diff)
1701 break;
1702 }
1703 }
1704
1705 /* handle buadrate outside acceptable rate */
1706 if (baud_diff > ((baudrate / 100) * 3))
1707 dev_warn(sport->port.dev,
1708 "unacceptable baud rate difference of more than 3%%\n");
1709
1710 tmp = lpuart32_read(&sport->port, UARTBAUD);
1711
1712 if ((osr > 3) && (osr < 8))
1713 tmp |= UARTBAUD_BOTHEDGE;
1714
1715 tmp &= ~(UARTBAUD_OSR_MASK << UARTBAUD_OSR_SHIFT);
1716 tmp |= (((osr-1) & UARTBAUD_OSR_MASK) << UARTBAUD_OSR_SHIFT);
1717
1718 tmp &= ~UARTBAUD_SBR_MASK;
1719 tmp |= sbr & UARTBAUD_SBR_MASK;
1720
1721 if (!sport->lpuart_dma_rx_use)
1722 tmp &= ~UARTBAUD_RDMAE;
1723 if (!sport->lpuart_dma_tx_use)
1724 tmp &= ~UARTBAUD_TDMAE;
1725
1726 lpuart32_write(&sport->port, tmp, UARTBAUD);
1727 }
1728
1729 static void
1730 lpuart32_set_termios(struct uart_port *port, struct ktermios *termios,
1731 struct ktermios *old)
1732 {
1733 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1734 unsigned long flags;
1735 unsigned long ctrl, old_ctrl, modem;
1736 unsigned int baud;
1737 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1738
1739 ctrl = old_ctrl = lpuart32_read(&sport->port, UARTCTRL);
1740 modem = lpuart32_read(&sport->port, UARTMODIR);
1741 /*
1742 * only support CS8 and CS7, and for CS7 must enable PE.
1743 * supported mode:
1744 * - (7,e/o,1)
1745 * - (8,n,1)
1746 * - (8,m/s,1)
1747 * - (8,e/o,1)
1748 */
1749 while ((termios->c_cflag & CSIZE) != CS8 &&
1750 (termios->c_cflag & CSIZE) != CS7) {
1751 termios->c_cflag &= ~CSIZE;
1752 termios->c_cflag |= old_csize;
1753 old_csize = CS8;
1754 }
1755
1756 if ((termios->c_cflag & CSIZE) == CS8 ||
1757 (termios->c_cflag & CSIZE) == CS7)
1758 ctrl = old_ctrl & ~UARTCTRL_M;
1759
1760 if (termios->c_cflag & CMSPAR) {
1761 if ((termios->c_cflag & CSIZE) != CS8) {
1762 termios->c_cflag &= ~CSIZE;
1763 termios->c_cflag |= CS8;
1764 }
1765 ctrl |= UARTCTRL_M;
1766 }
1767
1768 if (termios->c_cflag & CRTSCTS) {
1769 modem |= (UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1770 } else {
1771 termios->c_cflag &= ~CRTSCTS;
1772 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1773 }
1774
1775 if (termios->c_cflag & CSTOPB)
1776 termios->c_cflag &= ~CSTOPB;
1777
1778 /* parity must be enabled when CS7 to match 8-bits format */
1779 if ((termios->c_cflag & CSIZE) == CS7)
1780 termios->c_cflag |= PARENB;
1781
1782 if ((termios->c_cflag & PARENB)) {
1783 if (termios->c_cflag & CMSPAR) {
1784 ctrl &= ~UARTCTRL_PE;
1785 ctrl |= UARTCTRL_M;
1786 } else {
1787 ctrl |= UARTCTRL_PE;
1788 if ((termios->c_cflag & CSIZE) == CS8)
1789 ctrl |= UARTCTRL_M;
1790 if (termios->c_cflag & PARODD)
1791 ctrl |= UARTCTRL_PT;
1792 else
1793 ctrl &= ~UARTCTRL_PT;
1794 }
1795 } else {
1796 ctrl &= ~UARTCTRL_PE;
1797 }
1798
1799 /* ask the core to calculate the divisor */
1800 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 4);
1801
1802 /*
1803 * Need to update the Ring buffer length according to the selected
1804 * baud rate and restart Rx DMA path.
1805 *
1806 * Since timer function acqures sport->port.lock, need to stop before
1807 * acquring same lock because otherwise del_timer_sync() can deadlock.
1808 */
1809 if (old && sport->lpuart_dma_rx_use) {
1810 del_timer_sync(&sport->lpuart_timer);
1811 lpuart_dma_rx_free(&sport->port);
1812 }
1813
1814 spin_lock_irqsave(&sport->port.lock, flags);
1815
1816 sport->port.read_status_mask = 0;
1817 if (termios->c_iflag & INPCK)
1818 sport->port.read_status_mask |= (UARTSTAT_FE | UARTSTAT_PE);
1819 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1820 sport->port.read_status_mask |= UARTSTAT_FE;
1821
1822 /* characters to ignore */
1823 sport->port.ignore_status_mask = 0;
1824 if (termios->c_iflag & IGNPAR)
1825 sport->port.ignore_status_mask |= UARTSTAT_PE;
1826 if (termios->c_iflag & IGNBRK) {
1827 sport->port.ignore_status_mask |= UARTSTAT_FE;
1828 /*
1829 * if we're ignoring parity and break indicators,
1830 * ignore overruns too (for real raw support).
1831 */
1832 if (termios->c_iflag & IGNPAR)
1833 sport->port.ignore_status_mask |= UARTSTAT_OR;
1834 }
1835
1836 /* update the per-port timeout */
1837 uart_update_timeout(port, termios->c_cflag, baud);
1838
1839 /* wait transmit engin complete */
1840 while (!(lpuart32_read(&sport->port, UARTSTAT) & UARTSTAT_TC))
1841 barrier();
1842
1843 /* disable transmit and receive */
1844 lpuart32_write(&sport->port, old_ctrl & ~(UARTCTRL_TE | UARTCTRL_RE),
1845 UARTCTRL);
1846
1847 lpuart32_serial_setbrg(sport, baud);
1848 lpuart32_write(&sport->port, modem, UARTMODIR);
1849 lpuart32_write(&sport->port, ctrl, UARTCTRL);
1850 /* restore control register */
1851
1852 if (old && sport->lpuart_dma_rx_use) {
1853 if (!lpuart_start_rx_dma(sport))
1854 rx_dma_timer_init(sport);
1855 else
1856 sport->lpuart_dma_rx_use = false;
1857 }
1858
1859 spin_unlock_irqrestore(&sport->port.lock, flags);
1860 }
1861
1862 static const char *lpuart_type(struct uart_port *port)
1863 {
1864 return "FSL_LPUART";
1865 }
1866
1867 static void lpuart_release_port(struct uart_port *port)
1868 {
1869 /* nothing to do */
1870 }
1871
1872 static int lpuart_request_port(struct uart_port *port)
1873 {
1874 return 0;
1875 }
1876
1877 /* configure/autoconfigure the port */
1878 static void lpuart_config_port(struct uart_port *port, int flags)
1879 {
1880 if (flags & UART_CONFIG_TYPE)
1881 port->type = PORT_LPUART;
1882 }
1883
1884 static int lpuart_verify_port(struct uart_port *port, struct serial_struct *ser)
1885 {
1886 int ret = 0;
1887
1888 if (ser->type != PORT_UNKNOWN && ser->type != PORT_LPUART)
1889 ret = -EINVAL;
1890 if (port->irq != ser->irq)
1891 ret = -EINVAL;
1892 if (ser->io_type != UPIO_MEM)
1893 ret = -EINVAL;
1894 if (port->uartclk / 16 != ser->baud_base)
1895 ret = -EINVAL;
1896 if (port->iobase != ser->port)
1897 ret = -EINVAL;
1898 if (ser->hub6 != 0)
1899 ret = -EINVAL;
1900 return ret;
1901 }
1902
1903 static const struct uart_ops lpuart_pops = {
1904 .tx_empty = lpuart_tx_empty,
1905 .set_mctrl = lpuart_set_mctrl,
1906 .get_mctrl = lpuart_get_mctrl,
1907 .stop_tx = lpuart_stop_tx,
1908 .start_tx = lpuart_start_tx,
1909 .stop_rx = lpuart_stop_rx,
1910 .break_ctl = lpuart_break_ctl,
1911 .startup = lpuart_startup,
1912 .shutdown = lpuart_shutdown,
1913 .set_termios = lpuart_set_termios,
1914 .type = lpuart_type,
1915 .request_port = lpuart_request_port,
1916 .release_port = lpuart_release_port,
1917 .config_port = lpuart_config_port,
1918 .verify_port = lpuart_verify_port,
1919 .flush_buffer = lpuart_flush_buffer,
1920 #if defined(CONFIG_CONSOLE_POLL)
1921 .poll_init = lpuart_poll_init,
1922 .poll_get_char = lpuart_poll_get_char,
1923 .poll_put_char = lpuart_poll_put_char,
1924 #endif
1925 };
1926
1927 static const struct uart_ops lpuart32_pops = {
1928 .tx_empty = lpuart32_tx_empty,
1929 .set_mctrl = lpuart32_set_mctrl,
1930 .get_mctrl = lpuart32_get_mctrl,
1931 .stop_tx = lpuart32_stop_tx,
1932 .start_tx = lpuart32_start_tx,
1933 .stop_rx = lpuart32_stop_rx,
1934 .break_ctl = lpuart32_break_ctl,
1935 .startup = lpuart32_startup,
1936 .shutdown = lpuart32_shutdown,
1937 .set_termios = lpuart32_set_termios,
1938 .type = lpuart_type,
1939 .request_port = lpuart_request_port,
1940 .release_port = lpuart_release_port,
1941 .config_port = lpuart_config_port,
1942 .verify_port = lpuart_verify_port,
1943 .flush_buffer = lpuart_flush_buffer,
1944 #if defined(CONFIG_CONSOLE_POLL)
1945 .poll_init = lpuart32_poll_init,
1946 .poll_get_char = lpuart32_poll_get_char,
1947 .poll_put_char = lpuart32_poll_put_char,
1948 #endif
1949 };
1950
1951 static struct lpuart_port *lpuart_ports[UART_NR];
1952
1953 #ifdef CONFIG_SERIAL_FSL_LPUART_CONSOLE
1954 static void lpuart_console_putchar(struct uart_port *port, int ch)
1955 {
1956 while (!(readb(port->membase + UARTSR1) & UARTSR1_TDRE))
1957 barrier();
1958
1959 writeb(ch, port->membase + UARTDR);
1960 }
1961
1962 static void lpuart32_console_putchar(struct uart_port *port, int ch)
1963 {
1964 while (!(lpuart32_read(port, UARTSTAT) & UARTSTAT_TDRE))
1965 barrier();
1966
1967 lpuart32_write(port, ch, UARTDATA);
1968 }
1969
1970 static void
1971 lpuart_console_write(struct console *co, const char *s, unsigned int count)
1972 {
1973 struct lpuart_port *sport = lpuart_ports[co->index];
1974 unsigned char old_cr2, cr2;
1975 unsigned long flags;
1976 int locked = 1;
1977
1978 if (sport->port.sysrq || oops_in_progress)
1979 locked = spin_trylock_irqsave(&sport->port.lock, flags);
1980 else
1981 spin_lock_irqsave(&sport->port.lock, flags);
1982
1983 /* first save CR2 and then disable interrupts */
1984 cr2 = old_cr2 = readb(sport->port.membase + UARTCR2);
1985 cr2 |= (UARTCR2_TE | UARTCR2_RE);
1986 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
1987 writeb(cr2, sport->port.membase + UARTCR2);
1988
1989 uart_console_write(&sport->port, s, count, lpuart_console_putchar);
1990
1991 /* wait for transmitter finish complete and restore CR2 */
1992 while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC))
1993 barrier();
1994
1995 writeb(old_cr2, sport->port.membase + UARTCR2);
1996
1997 if (locked)
1998 spin_unlock_irqrestore(&sport->port.lock, flags);
1999 }
2000
2001 static void
2002 lpuart32_console_write(struct console *co, const char *s, unsigned int count)
2003 {
2004 struct lpuart_port *sport = lpuart_ports[co->index];
2005 unsigned long old_cr, cr;
2006 unsigned long flags;
2007 int locked = 1;
2008
2009 if (sport->port.sysrq || oops_in_progress)
2010 locked = spin_trylock_irqsave(&sport->port.lock, flags);
2011 else
2012 spin_lock_irqsave(&sport->port.lock, flags);
2013
2014 /* first save CR2 and then disable interrupts */
2015 cr = old_cr = lpuart32_read(&sport->port, UARTCTRL);
2016 cr |= (UARTCTRL_TE | UARTCTRL_RE);
2017 cr &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE);
2018 lpuart32_write(&sport->port, cr, UARTCTRL);
2019
2020 uart_console_write(&sport->port, s, count, lpuart32_console_putchar);
2021
2022 /* wait for transmitter finish complete and restore CR2 */
2023 while (!(lpuart32_read(&sport->port, UARTSTAT) & UARTSTAT_TC))
2024 barrier();
2025
2026 lpuart32_write(&sport->port, old_cr, UARTCTRL);
2027
2028 if (locked)
2029 spin_unlock_irqrestore(&sport->port.lock, flags);
2030 }
2031
2032 /*
2033 * if the port was already initialised (eg, by a boot loader),
2034 * try to determine the current setup.
2035 */
2036 static void __init
2037 lpuart_console_get_options(struct lpuart_port *sport, int *baud,
2038 int *parity, int *bits)
2039 {
2040 unsigned char cr, bdh, bdl, brfa;
2041 unsigned int sbr, uartclk, baud_raw;
2042
2043 cr = readb(sport->port.membase + UARTCR2);
2044 cr &= UARTCR2_TE | UARTCR2_RE;
2045 if (!cr)
2046 return;
2047
2048 /* ok, the port was enabled */
2049
2050 cr = readb(sport->port.membase + UARTCR1);
2051
2052 *parity = 'n';
2053 if (cr & UARTCR1_PE) {
2054 if (cr & UARTCR1_PT)
2055 *parity = 'o';
2056 else
2057 *parity = 'e';
2058 }
2059
2060 if (cr & UARTCR1_M)
2061 *bits = 9;
2062 else
2063 *bits = 8;
2064
2065 bdh = readb(sport->port.membase + UARTBDH);
2066 bdh &= UARTBDH_SBR_MASK;
2067 bdl = readb(sport->port.membase + UARTBDL);
2068 sbr = bdh;
2069 sbr <<= 8;
2070 sbr |= bdl;
2071 brfa = readb(sport->port.membase + UARTCR4);
2072 brfa &= UARTCR4_BRFA_MASK;
2073
2074 uartclk = clk_get_rate(sport->clk);
2075 /*
2076 * baud = mod_clk/(16*(sbr[13]+(brfa)/32)
2077 */
2078 baud_raw = uartclk / (16 * (sbr + brfa / 32));
2079
2080 if (*baud != baud_raw)
2081 printk(KERN_INFO "Serial: Console lpuart rounded baud rate"
2082 "from %d to %d\n", baud_raw, *baud);
2083 }
2084
2085 static void __init
2086 lpuart32_console_get_options(struct lpuart_port *sport, int *baud,
2087 int *parity, int *bits)
2088 {
2089 unsigned long cr, bd;
2090 unsigned int sbr, uartclk, baud_raw;
2091
2092 cr = lpuart32_read(&sport->port, UARTCTRL);
2093 cr &= UARTCTRL_TE | UARTCTRL_RE;
2094 if (!cr)
2095 return;
2096
2097 /* ok, the port was enabled */
2098
2099 cr = lpuart32_read(&sport->port, UARTCTRL);
2100
2101 *parity = 'n';
2102 if (cr & UARTCTRL_PE) {
2103 if (cr & UARTCTRL_PT)
2104 *parity = 'o';
2105 else
2106 *parity = 'e';
2107 }
2108
2109 if (cr & UARTCTRL_M)
2110 *bits = 9;
2111 else
2112 *bits = 8;
2113
2114 bd = lpuart32_read(&sport->port, UARTBAUD);
2115 bd &= UARTBAUD_SBR_MASK;
2116 sbr = bd;
2117 uartclk = clk_get_rate(sport->clk);
2118 /*
2119 * baud = mod_clk/(16*(sbr[13]+(brfa)/32)
2120 */
2121 baud_raw = uartclk / (16 * sbr);
2122
2123 if (*baud != baud_raw)
2124 printk(KERN_INFO "Serial: Console lpuart rounded baud rate"
2125 "from %d to %d\n", baud_raw, *baud);
2126 }
2127
2128 static int __init lpuart_console_setup(struct console *co, char *options)
2129 {
2130 struct lpuart_port *sport;
2131 int baud = 115200;
2132 int bits = 8;
2133 int parity = 'n';
2134 int flow = 'n';
2135
2136 /*
2137 * check whether an invalid uart number has been specified, and
2138 * if so, search for the first available port that does have
2139 * console support.
2140 */
2141 if (co->index == -1 || co->index >= ARRAY_SIZE(lpuart_ports))
2142 co->index = 0;
2143
2144 sport = lpuart_ports[co->index];
2145 if (sport == NULL)
2146 return -ENODEV;
2147
2148 if (options)
2149 uart_parse_options(options, &baud, &parity, &bits, &flow);
2150 else
2151 if (lpuart_is_32(sport))
2152 lpuart32_console_get_options(sport, &baud, &parity, &bits);
2153 else
2154 lpuart_console_get_options(sport, &baud, &parity, &bits);
2155
2156 if (lpuart_is_32(sport))
2157 lpuart32_setup_watermark(sport);
2158 else
2159 lpuart_setup_watermark(sport);
2160
2161 return uart_set_options(&sport->port, co, baud, parity, bits, flow);
2162 }
2163
2164 static struct uart_driver lpuart_reg;
2165 static struct console lpuart_console = {
2166 .name = DEV_NAME,
2167 .write = lpuart_console_write,
2168 .device = uart_console_device,
2169 .setup = lpuart_console_setup,
2170 .flags = CON_PRINTBUFFER,
2171 .index = -1,
2172 .data = &lpuart_reg,
2173 };
2174
2175 static struct console lpuart32_console = {
2176 .name = DEV_NAME,
2177 .write = lpuart32_console_write,
2178 .device = uart_console_device,
2179 .setup = lpuart_console_setup,
2180 .flags = CON_PRINTBUFFER,
2181 .index = -1,
2182 .data = &lpuart_reg,
2183 };
2184
2185 static void lpuart_early_write(struct console *con, const char *s, unsigned n)
2186 {
2187 struct earlycon_device *dev = con->data;
2188
2189 uart_console_write(&dev->port, s, n, lpuart_console_putchar);
2190 }
2191
2192 static void lpuart32_early_write(struct console *con, const char *s, unsigned n)
2193 {
2194 struct earlycon_device *dev = con->data;
2195
2196 uart_console_write(&dev->port, s, n, lpuart32_console_putchar);
2197 }
2198
2199 static int __init lpuart_early_console_setup(struct earlycon_device *device,
2200 const char *opt)
2201 {
2202 if (!device->port.membase)
2203 return -ENODEV;
2204
2205 device->con->write = lpuart_early_write;
2206 return 0;
2207 }
2208
2209 static int __init lpuart32_early_console_setup(struct earlycon_device *device,
2210 const char *opt)
2211 {
2212 if (!device->port.membase)
2213 return -ENODEV;
2214
2215 device->port.iotype = UPIO_MEM32BE;
2216 device->con->write = lpuart32_early_write;
2217 return 0;
2218 }
2219
2220 static int __init lpuart32_imx_early_console_setup(struct earlycon_device *device,
2221 const char *opt)
2222 {
2223 if (!device->port.membase)
2224 return -ENODEV;
2225
2226 device->port.iotype = UPIO_MEM32;
2227 device->port.membase += IMX_REG_OFF;
2228 device->con->write = lpuart32_early_write;
2229
2230 return 0;
2231 }
2232 OF_EARLYCON_DECLARE(lpuart, "fsl,vf610-lpuart", lpuart_early_console_setup);
2233 OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1021a-lpuart", lpuart32_early_console_setup);
2234 OF_EARLYCON_DECLARE(lpuart32, "fsl,imx7ulp-lpuart", lpuart32_imx_early_console_setup);
2235 EARLYCON_DECLARE(lpuart, lpuart_early_console_setup);
2236 EARLYCON_DECLARE(lpuart32, lpuart32_early_console_setup);
2237
2238 #define LPUART_CONSOLE (&lpuart_console)
2239 #define LPUART32_CONSOLE (&lpuart32_console)
2240 #else
2241 #define LPUART_CONSOLE NULL
2242 #define LPUART32_CONSOLE NULL
2243 #endif
2244
2245 static struct uart_driver lpuart_reg = {
2246 .owner = THIS_MODULE,
2247 .driver_name = DRIVER_NAME,
2248 .dev_name = DEV_NAME,
2249 .nr = ARRAY_SIZE(lpuart_ports),
2250 .cons = LPUART_CONSOLE,
2251 };
2252
2253 static int lpuart_probe(struct platform_device *pdev)
2254 {
2255 const struct of_device_id *of_id = of_match_device(lpuart_dt_ids,
2256 &pdev->dev);
2257 const struct lpuart_soc_data *sdata = of_id->data;
2258 struct device_node *np = pdev->dev.of_node;
2259 struct lpuart_port *sport;
2260 struct resource *res;
2261 int ret;
2262
2263 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
2264 if (!sport)
2265 return -ENOMEM;
2266
2267 pdev->dev.coherent_dma_mask = 0;
2268
2269 ret = of_alias_get_id(np, "serial");
2270 if (ret < 0) {
2271 ret = ida_simple_get(&fsl_lpuart_ida, 0, UART_NR, GFP_KERNEL);
2272 if (ret < 0) {
2273 dev_err(&pdev->dev, "port line is full, add device failed\n");
2274 return ret;
2275 }
2276 }
2277 if (ret >= ARRAY_SIZE(lpuart_ports)) {
2278 dev_err(&pdev->dev, "serial%d out of range\n", ret);
2279 return -EINVAL;
2280 }
2281 sport->port.line = ret;
2282 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2283 sport->port.membase = devm_ioremap_resource(&pdev->dev, res);
2284 if (IS_ERR(sport->port.membase))
2285 return PTR_ERR(sport->port.membase);
2286
2287 sport->port.membase += sdata->reg_off;
2288 sport->port.mapbase = res->start;
2289 sport->port.dev = &pdev->dev;
2290 sport->port.type = PORT_LPUART;
2291 ret = platform_get_irq(pdev, 0);
2292 if (ret < 0) {
2293 dev_err(&pdev->dev, "cannot obtain irq\n");
2294 return ret;
2295 }
2296 sport->port.irq = ret;
2297 sport->port.iotype = sdata->iotype;
2298 if (lpuart_is_32(sport))
2299 sport->port.ops = &lpuart32_pops;
2300 else
2301 sport->port.ops = &lpuart_pops;
2302 sport->port.flags = UPF_BOOT_AUTOCONF;
2303
2304 sport->port.rs485_config = lpuart_config_rs485;
2305
2306 sport->clk = devm_clk_get(&pdev->dev, "ipg");
2307 if (IS_ERR(sport->clk)) {
2308 ret = PTR_ERR(sport->clk);
2309 dev_err(&pdev->dev, "failed to get uart clk: %d\n", ret);
2310 return ret;
2311 }
2312
2313 ret = clk_prepare_enable(sport->clk);
2314 if (ret) {
2315 dev_err(&pdev->dev, "failed to enable uart clk: %d\n", ret);
2316 return ret;
2317 }
2318
2319 sport->port.uartclk = clk_get_rate(sport->clk);
2320
2321 lpuart_ports[sport->port.line] = sport;
2322
2323 platform_set_drvdata(pdev, &sport->port);
2324
2325 if (lpuart_is_32(sport)) {
2326 lpuart_reg.cons = LPUART32_CONSOLE;
2327 ret = devm_request_irq(&pdev->dev, sport->port.irq, lpuart32_int, 0,
2328 DRIVER_NAME, sport);
2329 } else {
2330 lpuart_reg.cons = LPUART_CONSOLE;
2331 ret = devm_request_irq(&pdev->dev, sport->port.irq, lpuart_int, 0,
2332 DRIVER_NAME, sport);
2333 }
2334
2335 if (ret)
2336 goto failed_irq_request;
2337
2338 ret = uart_add_one_port(&lpuart_reg, &sport->port);
2339 if (ret)
2340 goto failed_attach_port;
2341
2342 uart_get_rs485_mode(&pdev->dev, &sport->port.rs485);
2343
2344 if (sport->port.rs485.flags & SER_RS485_RX_DURING_TX)
2345 dev_err(&pdev->dev, "driver doesn't support RX during TX\n");
2346
2347 if (sport->port.rs485.delay_rts_before_send ||
2348 sport->port.rs485.delay_rts_after_send)
2349 dev_err(&pdev->dev, "driver doesn't support RTS delays\n");
2350
2351 lpuart_config_rs485(&sport->port, &sport->port.rs485);
2352
2353 sport->dma_tx_chan = dma_request_slave_channel(sport->port.dev, "tx");
2354 if (!sport->dma_tx_chan)
2355 dev_info(sport->port.dev, "DMA tx channel request failed, "
2356 "operating without tx DMA\n");
2357
2358 sport->dma_rx_chan = dma_request_slave_channel(sport->port.dev, "rx");
2359 if (!sport->dma_rx_chan)
2360 dev_info(sport->port.dev, "DMA rx channel request failed, "
2361 "operating without rx DMA\n");
2362
2363 return 0;
2364
2365 failed_attach_port:
2366 failed_irq_request:
2367 clk_disable_unprepare(sport->clk);
2368 return ret;
2369 }
2370
2371 static int lpuart_remove(struct platform_device *pdev)
2372 {
2373 struct lpuart_port *sport = platform_get_drvdata(pdev);
2374
2375 uart_remove_one_port(&lpuart_reg, &sport->port);
2376
2377 ida_simple_remove(&fsl_lpuart_ida, sport->port.line);
2378
2379 clk_disable_unprepare(sport->clk);
2380
2381 if (sport->dma_tx_chan)
2382 dma_release_channel(sport->dma_tx_chan);
2383
2384 if (sport->dma_rx_chan)
2385 dma_release_channel(sport->dma_rx_chan);
2386
2387 return 0;
2388 }
2389
2390 #ifdef CONFIG_PM_SLEEP
2391 static int lpuart_suspend(struct device *dev)
2392 {
2393 struct lpuart_port *sport = dev_get_drvdata(dev);
2394 unsigned long temp;
2395 bool irq_wake;
2396
2397 if (lpuart_is_32(sport)) {
2398 /* disable Rx/Tx and interrupts */
2399 temp = lpuart32_read(&sport->port, UARTCTRL);
2400 temp &= ~(UARTCTRL_TE | UARTCTRL_TIE | UARTCTRL_TCIE);
2401 lpuart32_write(&sport->port, temp, UARTCTRL);
2402 } else {
2403 /* disable Rx/Tx and interrupts */
2404 temp = readb(sport->port.membase + UARTCR2);
2405 temp &= ~(UARTCR2_TE | UARTCR2_TIE | UARTCR2_TCIE);
2406 writeb(temp, sport->port.membase + UARTCR2);
2407 }
2408
2409 uart_suspend_port(&lpuart_reg, &sport->port);
2410
2411 /* uart_suspend_port() might set wakeup flag */
2412 irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq));
2413
2414 if (sport->lpuart_dma_rx_use) {
2415 /*
2416 * EDMA driver during suspend will forcefully release any
2417 * non-idle DMA channels. If port wakeup is enabled or if port
2418 * is console port or 'no_console_suspend' is set the Rx DMA
2419 * cannot resume as as expected, hence gracefully release the
2420 * Rx DMA path before suspend and start Rx DMA path on resume.
2421 */
2422 if (irq_wake) {
2423 del_timer_sync(&sport->lpuart_timer);
2424 lpuart_dma_rx_free(&sport->port);
2425 }
2426
2427 /* Disable Rx DMA to use UART port as wakeup source */
2428 if (lpuart_is_32(sport)) {
2429 temp = lpuart32_read(&sport->port, UARTBAUD);
2430 lpuart32_write(&sport->port, temp & ~UARTBAUD_RDMAE,
2431 UARTBAUD);
2432 } else {
2433 writeb(readb(sport->port.membase + UARTCR5) &
2434 ~UARTCR5_RDMAS, sport->port.membase + UARTCR5);
2435 }
2436 }
2437
2438 if (sport->lpuart_dma_tx_use) {
2439 sport->dma_tx_in_progress = false;
2440 dmaengine_terminate_all(sport->dma_tx_chan);
2441 }
2442
2443 if (sport->port.suspended && !irq_wake)
2444 clk_disable_unprepare(sport->clk);
2445
2446 return 0;
2447 }
2448
2449 static int lpuart_resume(struct device *dev)
2450 {
2451 struct lpuart_port *sport = dev_get_drvdata(dev);
2452 bool irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq));
2453 unsigned long temp;
2454
2455 if (sport->port.suspended && !irq_wake)
2456 clk_prepare_enable(sport->clk);
2457
2458 if (lpuart_is_32(sport)) {
2459 lpuart32_setup_watermark(sport);
2460 temp = lpuart32_read(&sport->port, UARTCTRL);
2461 temp |= UARTCTRL_RE | UARTCTRL_TE | UARTCTRL_ILIE;
2462 lpuart32_write(&sport->port, temp, UARTCTRL);
2463 } else {
2464 lpuart_setup_watermark(sport);
2465 temp = readb(sport->port.membase + UARTCR2);
2466 temp |= (UARTCR2_RIE | UARTCR2_TIE | UARTCR2_RE | UARTCR2_TE);
2467 writeb(temp, sport->port.membase + UARTCR2);
2468 }
2469
2470 if (sport->lpuart_dma_rx_use) {
2471 if (irq_wake) {
2472 if (!lpuart_start_rx_dma(sport))
2473 rx_dma_timer_init(sport);
2474 else
2475 sport->lpuart_dma_rx_use = false;
2476 }
2477 }
2478
2479 if (sport->dma_tx_chan && !lpuart_dma_tx_request(&sport->port)) {
2480 init_waitqueue_head(&sport->dma_wait);
2481 sport->lpuart_dma_tx_use = true;
2482 if (lpuart_is_32(sport)) {
2483 temp = lpuart32_read(&sport->port, UARTBAUD);
2484 lpuart32_write(&sport->port,
2485 temp | UARTBAUD_TDMAE, UARTBAUD);
2486 } else {
2487 writeb(readb(sport->port.membase + UARTCR5) |
2488 UARTCR5_TDMAS, sport->port.membase + UARTCR5);
2489 }
2490 } else {
2491 sport->lpuart_dma_tx_use = false;
2492 }
2493
2494 if (lpuart_is_32(sport)) {
2495 if (sport->lpuart_dma_rx_use) {
2496 /* RXWATER must be 0 */
2497 temp = lpuart32_read(&sport->port, UARTWATER);
2498 temp &= ~(UARTWATER_WATER_MASK <<
2499 UARTWATER_RXWATER_OFF);
2500 lpuart32_write(&sport->port, temp, UARTWATER);
2501 }
2502 temp = lpuart32_read(&sport->port, UARTCTRL);
2503 if (!sport->lpuart_dma_rx_use)
2504 temp |= UARTCTRL_RIE;
2505 if (!sport->lpuart_dma_tx_use)
2506 temp |= UARTCTRL_TIE;
2507 lpuart32_write(&sport->port, temp, UARTCTRL);
2508 }
2509
2510 uart_resume_port(&lpuart_reg, &sport->port);
2511
2512 return 0;
2513 }
2514 #endif
2515
2516 static SIMPLE_DEV_PM_OPS(lpuart_pm_ops, lpuart_suspend, lpuart_resume);
2517
2518 static struct platform_driver lpuart_driver = {
2519 .probe = lpuart_probe,
2520 .remove = lpuart_remove,
2521 .driver = {
2522 .name = "fsl-lpuart",
2523 .of_match_table = lpuart_dt_ids,
2524 .pm = &lpuart_pm_ops,
2525 },
2526 };
2527
2528 static int __init lpuart_serial_init(void)
2529 {
2530 int ret = uart_register_driver(&lpuart_reg);
2531
2532 if (ret)
2533 return ret;
2534
2535 ret = platform_driver_register(&lpuart_driver);
2536 if (ret)
2537 uart_unregister_driver(&lpuart_reg);
2538
2539 return ret;
2540 }
2541
2542 static void __exit lpuart_serial_exit(void)
2543 {
2544 ida_destroy(&fsl_lpuart_ida);
2545 platform_driver_unregister(&lpuart_driver);
2546 uart_unregister_driver(&lpuart_reg);
2547 }
2548
2549 module_init(lpuart_serial_init);
2550 module_exit(lpuart_serial_exit);
2551
2552 MODULE_DESCRIPTION("Freescale lpuart serial port driver");
2553 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support