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staging: erofs: integrate decompression inplace
[linux/fpc-iii.git] / drivers / tty / serial / imx.c
blob8b752e8950537d4ec706c0dace302e8b00230f53
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Driver for Motorola/Freescale IMX serial ports
4 *
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 *
7 * Author: Sascha Hauer <sascha@saschahauer.de>
8 * Copyright (C) 2004 Pengutronix
9 */
10
11 #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
12 #define SUPPORT_SYSRQ
13 #endif
14
15 #include <linux/module.h>
16 #include <linux/ioport.h>
17 #include <linux/init.h>
18 #include <linux/console.h>
19 #include <linux/sysrq.h>
20 #include <linux/platform_device.h>
21 #include <linux/tty.h>
22 #include <linux/tty_flip.h>
23 #include <linux/serial_core.h>
24 #include <linux/serial.h>
25 #include <linux/clk.h>
26 #include <linux/delay.h>
27 #include <linux/pinctrl/consumer.h>
28 #include <linux/rational.h>
29 #include <linux/slab.h>
30 #include <linux/of.h>
31 #include <linux/of_device.h>
32 #include <linux/io.h>
33 #include <linux/dma-mapping.h>
34
35 #include <asm/irq.h>
36 #include <linux/platform_data/serial-imx.h>
37 #include <linux/platform_data/dma-imx.h>
38
39 #include "serial_mctrl_gpio.h"
40
41 /* Register definitions */
42 #define URXD0 0x0 /* Receiver Register */
43 #define URTX0 0x40 /* Transmitter Register */
44 #define UCR1 0x80 /* Control Register 1 */
45 #define UCR2 0x84 /* Control Register 2 */
46 #define UCR3 0x88 /* Control Register 3 */
47 #define UCR4 0x8c /* Control Register 4 */
48 #define UFCR 0x90 /* FIFO Control Register */
49 #define USR1 0x94 /* Status Register 1 */
50 #define USR2 0x98 /* Status Register 2 */
51 #define UESC 0x9c /* Escape Character Register */
52 #define UTIM 0xa0 /* Escape Timer Register */
53 #define UBIR 0xa4 /* BRM Incremental Register */
54 #define UBMR 0xa8 /* BRM Modulator Register */
55 #define UBRC 0xac /* Baud Rate Count Register */
56 #define IMX21_ONEMS 0xb0 /* One Millisecond register */
57 #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */
58 #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/
59
60 /* UART Control Register Bit Fields.*/
61 #define URXD_DUMMY_READ (1<<16)
62 #define URXD_CHARRDY (1<<15)
63 #define URXD_ERR (1<<14)
64 #define URXD_OVRRUN (1<<13)
65 #define URXD_FRMERR (1<<12)
66 #define URXD_BRK (1<<11)
67 #define URXD_PRERR (1<<10)
68 #define URXD_RX_DATA (0xFF<<0)
69 #define UCR1_ADEN (1<<15) /* Auto detect interrupt */
70 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */
71 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
72 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */
73 #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */
74 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
75 #define UCR1_RXDMAEN (1<<8) /* Recv ready DMA enable */
76 #define UCR1_IREN (1<<7) /* Infrared interface enable */
77 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
78 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
79 #define UCR1_SNDBRK (1<<4) /* Send break */
80 #define UCR1_TXDMAEN (1<<3) /* Transmitter ready DMA enable */
81 #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
82 #define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */
83 #define UCR1_DOZE (1<<1) /* Doze */
84 #define UCR1_UARTEN (1<<0) /* UART enabled */
85 #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
86 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */
87 #define UCR2_CTSC (1<<13) /* CTS pin control */
88 #define UCR2_CTS (1<<12) /* Clear to send */
89 #define UCR2_ESCEN (1<<11) /* Escape enable */
90 #define UCR2_PREN (1<<8) /* Parity enable */
91 #define UCR2_PROE (1<<7) /* Parity odd/even */
92 #define UCR2_STPB (1<<6) /* Stop */
93 #define UCR2_WS (1<<5) /* Word size */
94 #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
95 #define UCR2_ATEN (1<<3) /* Aging Timer Enable */
96 #define UCR2_TXEN (1<<2) /* Transmitter enabled */
97 #define UCR2_RXEN (1<<1) /* Receiver enabled */
98 #define UCR2_SRST (1<<0) /* SW reset */
99 #define UCR3_DTREN (1<<13) /* DTR interrupt enable */
100 #define UCR3_PARERREN (1<<12) /* Parity enable */
101 #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
102 #define UCR3_DSR (1<<10) /* Data set ready */
103 #define UCR3_DCD (1<<9) /* Data carrier detect */
104 #define UCR3_RI (1<<8) /* Ring indicator */
105 #define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */
106 #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
107 #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
108 #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
109 #define UCR3_DTRDEN (1<<3) /* Data Terminal Ready Delta Enable. */
110 #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */
111 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
112 #define UCR3_BPEN (1<<0) /* Preset registers enable */
113 #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */
114 #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */
115 #define UCR4_INVR (1<<9) /* Inverted infrared reception */
116 #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
117 #define UCR4_WKEN (1<<7) /* Wake interrupt enable */
118 #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
119 #define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */
120 #define UCR4_IRSC (1<<5) /* IR special case */
121 #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
122 #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
123 #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
124 #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
125 #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
126 #define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */
127 #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
128 #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
129 #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
130 #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
131 #define USR1_RTSS (1<<14) /* RTS pin status */
132 #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
133 #define USR1_RTSD (1<<12) /* RTS delta */
134 #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
135 #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
136 #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
137 #define USR1_AGTIM (1<<8) /* Ageing timer interrupt flag */
138 #define USR1_DTRD (1<<7) /* DTR Delta */
139 #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
140 #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
141 #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
142 #define USR2_ADET (1<<15) /* Auto baud rate detect complete */
143 #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
144 #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
145 #define USR2_IDLE (1<<12) /* Idle condition */
146 #define USR2_RIDELT (1<<10) /* Ring Interrupt Delta */
147 #define USR2_RIIN (1<<9) /* Ring Indicator Input */
148 #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
149 #define USR2_WAKE (1<<7) /* Wake */
150 #define USR2_DCDIN (1<<5) /* Data Carrier Detect Input */
151 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
152 #define USR2_TXDC (1<<3) /* Transmitter complete */
153 #define USR2_BRCD (1<<2) /* Break condition */
154 #define USR2_ORE (1<<1) /* Overrun error */
155 #define USR2_RDR (1<<0) /* Recv data ready */
156 #define UTS_FRCPERR (1<<13) /* Force parity error */
157 #define UTS_LOOP (1<<12) /* Loop tx and rx */
158 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
159 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
160 #define UTS_TXFULL (1<<4) /* TxFIFO full */
161 #define UTS_RXFULL (1<<3) /* RxFIFO full */
162 #define UTS_SOFTRST (1<<0) /* Software reset */
163
164 /* We've been assigned a range on the "Low-density serial ports" major */
165 #define SERIAL_IMX_MAJOR 207
166 #define MINOR_START 16
167 #define DEV_NAME "ttymxc"
168
169 /*
170 * This determines how often we check the modem status signals
171 * for any change. They generally aren't connected to an IRQ
172 * so we have to poll them. We also check immediately before
173 * filling the TX fifo incase CTS has been dropped.
174 */
175 #define MCTRL_TIMEOUT (250*HZ/1000)
176
177 #define DRIVER_NAME "IMX-uart"
178
179 #define UART_NR 8
180
181 /* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */
182 enum imx_uart_type {
183 IMX1_UART,
184 IMX21_UART,
185 IMX53_UART,
186 IMX6Q_UART,
187 };
188
189 /* device type dependent stuff */
190 struct imx_uart_data {
191 unsigned uts_reg;
192 enum imx_uart_type devtype;
193 };
194
195 struct imx_port {
196 struct uart_port port;
197 struct timer_list timer;
198 unsigned int old_status;
199 unsigned int have_rtscts:1;
200 unsigned int have_rtsgpio:1;
201 unsigned int dte_mode:1;
202 struct clk *clk_ipg;
203 struct clk *clk_per;
204 const struct imx_uart_data *devdata;
205
206 struct mctrl_gpios *gpios;
207
208 /* shadow registers */
209 unsigned int ucr1;
210 unsigned int ucr2;
211 unsigned int ucr3;
212 unsigned int ucr4;
213 unsigned int ufcr;
214
215 /* DMA fields */
216 unsigned int dma_is_enabled:1;
217 unsigned int dma_is_rxing:1;
218 unsigned int dma_is_txing:1;
219 struct dma_chan *dma_chan_rx, *dma_chan_tx;
220 struct scatterlist rx_sgl, tx_sgl[2];
221 void *rx_buf;
222 struct circ_buf rx_ring;
223 unsigned int rx_periods;
224 dma_cookie_t rx_cookie;
225 unsigned int tx_bytes;
226 unsigned int dma_tx_nents;
227 unsigned int saved_reg[10];
228 bool context_saved;
229 };
230
231 struct imx_port_ucrs {
232 unsigned int ucr1;
233 unsigned int ucr2;
234 unsigned int ucr3;
235 };
236
237 static struct imx_uart_data imx_uart_devdata[] = {
238 [IMX1_UART] = {
239 .uts_reg = IMX1_UTS,
240 .devtype = IMX1_UART,
241 },
242 [IMX21_UART] = {
243 .uts_reg = IMX21_UTS,
244 .devtype = IMX21_UART,
245 },
246 [IMX53_UART] = {
247 .uts_reg = IMX21_UTS,
248 .devtype = IMX53_UART,
249 },
250 [IMX6Q_UART] = {
251 .uts_reg = IMX21_UTS,
252 .devtype = IMX6Q_UART,
253 },
254 };
255
256 static const struct platform_device_id imx_uart_devtype[] = {
257 {
258 .name = "imx1-uart",
259 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART],
260 }, {
261 .name = "imx21-uart",
262 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART],
263 }, {
264 .name = "imx53-uart",
265 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX53_UART],
266 }, {
267 .name = "imx6q-uart",
268 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX6Q_UART],
269 }, {
270 /* sentinel */
271 }
272 };
273 MODULE_DEVICE_TABLE(platform, imx_uart_devtype);
274
275 static const struct of_device_id imx_uart_dt_ids[] = {
276 { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], },
277 { .compatible = "fsl,imx53-uart", .data = &imx_uart_devdata[IMX53_UART], },
278 { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], },
279 { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], },
280 { /* sentinel */ }
281 };
282 MODULE_DEVICE_TABLE(of, imx_uart_dt_ids);
283
284 static void imx_uart_writel(struct imx_port *sport, u32 val, u32 offset)
285 {
286 switch (offset) {
287 case UCR1:
288 sport->ucr1 = val;
289 break;
290 case UCR2:
291 sport->ucr2 = val;
292 break;
293 case UCR3:
294 sport->ucr3 = val;
295 break;
296 case UCR4:
297 sport->ucr4 = val;
298 break;
299 case UFCR:
300 sport->ufcr = val;
301 break;
302 default:
303 break;
304 }
305 writel(val, sport->port.membase + offset);
306 }
307
308 static u32 imx_uart_readl(struct imx_port *sport, u32 offset)
309 {
310 switch (offset) {
311 case UCR1:
312 return sport->ucr1;
313 break;
314 case UCR2:
315 /*
316 * UCR2_SRST is the only bit in the cached registers that might
317 * differ from the value that was last written. As it only
318 * automatically becomes one after being cleared, reread
319 * conditionally.
320 */
321 if (!(sport->ucr2 & UCR2_SRST))
322 sport->ucr2 = readl(sport->port.membase + offset);
323 return sport->ucr2;
324 break;
325 case UCR3:
326 return sport->ucr3;
327 break;
328 case UCR4:
329 return sport->ucr4;
330 break;
331 case UFCR:
332 return sport->ufcr;
333 break;
334 default:
335 return readl(sport->port.membase + offset);
336 }
337 }
338
339 static inline unsigned imx_uart_uts_reg(struct imx_port *sport)
340 {
341 return sport->devdata->uts_reg;
342 }
343
344 static inline int imx_uart_is_imx1(struct imx_port *sport)
345 {
346 return sport->devdata->devtype == IMX1_UART;
347 }
348
349 static inline int imx_uart_is_imx21(struct imx_port *sport)
350 {
351 return sport->devdata->devtype == IMX21_UART;
352 }
353
354 static inline int imx_uart_is_imx53(struct imx_port *sport)
355 {
356 return sport->devdata->devtype == IMX53_UART;
357 }
358
359 static inline int imx_uart_is_imx6q(struct imx_port *sport)
360 {
361 return sport->devdata->devtype == IMX6Q_UART;
362 }
363 /*
364 * Save and restore functions for UCR1, UCR2 and UCR3 registers
365 */
366 #if defined(CONFIG_SERIAL_IMX_CONSOLE)
367 static void imx_uart_ucrs_save(struct imx_port *sport,
368 struct imx_port_ucrs *ucr)
369 {
370 /* save control registers */
371 ucr->ucr1 = imx_uart_readl(sport, UCR1);
372 ucr->ucr2 = imx_uart_readl(sport, UCR2);
373 ucr->ucr3 = imx_uart_readl(sport, UCR3);
374 }
375
376 static void imx_uart_ucrs_restore(struct imx_port *sport,
377 struct imx_port_ucrs *ucr)
378 {
379 /* restore control registers */
380 imx_uart_writel(sport, ucr->ucr1, UCR1);
381 imx_uart_writel(sport, ucr->ucr2, UCR2);
382 imx_uart_writel(sport, ucr->ucr3, UCR3);
383 }
384 #endif
385
386 static void imx_uart_rts_active(struct imx_port *sport, u32 *ucr2)
387 {
388 *ucr2 &= ~(UCR2_CTSC | UCR2_CTS);
389
390 sport->port.mctrl |= TIOCM_RTS;
391 mctrl_gpio_set(sport->gpios, sport->port.mctrl);
392 }
393
394 static void imx_uart_rts_inactive(struct imx_port *sport, u32 *ucr2)
395 {
396 *ucr2 &= ~UCR2_CTSC;
397 *ucr2 |= UCR2_CTS;
398
399 sport->port.mctrl &= ~TIOCM_RTS;
400 mctrl_gpio_set(sport->gpios, sport->port.mctrl);
401 }
402
403 static void imx_uart_rts_auto(struct imx_port *sport, u32 *ucr2)
404 {
405 *ucr2 |= UCR2_CTSC;
406 }
407
408 /* called with port.lock taken and irqs off */
409 static void imx_uart_start_rx(struct uart_port *port)
410 {
411 struct imx_port *sport = (struct imx_port *)port;
412 unsigned int ucr1, ucr2;
413
414 ucr1 = imx_uart_readl(sport, UCR1);
415 ucr2 = imx_uart_readl(sport, UCR2);
416
417 ucr2 |= UCR2_RXEN;
418
419 if (sport->dma_is_enabled) {
420 ucr1 |= UCR1_RXDMAEN | UCR1_ATDMAEN;
421 } else {
422 ucr1 |= UCR1_RRDYEN;
423 ucr2 |= UCR2_ATEN;
424 }
425
426 /* Write UCR2 first as it includes RXEN */
427 imx_uart_writel(sport, ucr2, UCR2);
428 imx_uart_writel(sport, ucr1, UCR1);
429 }
430
431 /* called with port.lock taken and irqs off */
432 static void imx_uart_stop_tx(struct uart_port *port)
433 {
434 struct imx_port *sport = (struct imx_port *)port;
435 u32 ucr1;
436
437 /*
438 * We are maybe in the SMP context, so if the DMA TX thread is running
439 * on other cpu, we have to wait for it to finish.
440 */
441 if (sport->dma_is_txing)
442 return;
443
444 ucr1 = imx_uart_readl(sport, UCR1);
445 imx_uart_writel(sport, ucr1 & ~UCR1_TXMPTYEN, UCR1);
446
447 /* in rs485 mode disable transmitter if shifter is empty */
448 if (port->rs485.flags & SER_RS485_ENABLED &&
449 imx_uart_readl(sport, USR2) & USR2_TXDC) {
450 u32 ucr2 = imx_uart_readl(sport, UCR2), ucr4;
451 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
452 imx_uart_rts_active(sport, &ucr2);
453 else
454 imx_uart_rts_inactive(sport, &ucr2);
455 imx_uart_writel(sport, ucr2, UCR2);
456
457 imx_uart_start_rx(port);
458
459 ucr4 = imx_uart_readl(sport, UCR4);
460 ucr4 &= ~UCR4_TCEN;
461 imx_uart_writel(sport, ucr4, UCR4);
462 }
463 }
464
465 /* called with port.lock taken and irqs off */
466 static void imx_uart_stop_rx(struct uart_port *port)
467 {
468 struct imx_port *sport = (struct imx_port *)port;
469 u32 ucr1, ucr2;
470
471 ucr1 = imx_uart_readl(sport, UCR1);
472 ucr2 = imx_uart_readl(sport, UCR2);
473
474 if (sport->dma_is_enabled) {
475 ucr1 &= ~(UCR1_RXDMAEN | UCR1_ATDMAEN);
476 } else {
477 ucr1 &= ~UCR1_RRDYEN;
478 ucr2 &= ~UCR2_ATEN;
479 }
480 imx_uart_writel(sport, ucr1, UCR1);
481
482 ucr2 &= ~UCR2_RXEN;
483 imx_uart_writel(sport, ucr2, UCR2);
484 }
485
486 /* called with port.lock taken and irqs off */
487 static void imx_uart_enable_ms(struct uart_port *port)
488 {
489 struct imx_port *sport = (struct imx_port *)port;
490
491 mod_timer(&sport->timer, jiffies);
492
493 mctrl_gpio_enable_ms(sport->gpios);
494 }
495
496 static void imx_uart_dma_tx(struct imx_port *sport);
497
498 /* called with port.lock taken and irqs off */
499 static inline void imx_uart_transmit_buffer(struct imx_port *sport)
500 {
501 struct circ_buf *xmit = &sport->port.state->xmit;
502
503 if (sport->port.x_char) {
504 /* Send next char */
505 imx_uart_writel(sport, sport->port.x_char, URTX0);
506 sport->port.icount.tx++;
507 sport->port.x_char = 0;
508 return;
509 }
510
511 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
512 imx_uart_stop_tx(&sport->port);
513 return;
514 }
515
516 if (sport->dma_is_enabled) {
517 u32 ucr1;
518 /*
519 * We've just sent a X-char Ensure the TX DMA is enabled
520 * and the TX IRQ is disabled.
521 **/
522 ucr1 = imx_uart_readl(sport, UCR1);
523 ucr1 &= ~UCR1_TXMPTYEN;
524 if (sport->dma_is_txing) {
525 ucr1 |= UCR1_TXDMAEN;
526 imx_uart_writel(sport, ucr1, UCR1);
527 } else {
528 imx_uart_writel(sport, ucr1, UCR1);
529 imx_uart_dma_tx(sport);
530 }
531
532 return;
533 }
534
535 while (!uart_circ_empty(xmit) &&
536 !(imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL)) {
537 /* send xmit->buf[xmit->tail]
538 * out the port here */
539 imx_uart_writel(sport, xmit->buf[xmit->tail], URTX0);
540 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
541 sport->port.icount.tx++;
542 }
543
544 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
545 uart_write_wakeup(&sport->port);
546
547 if (uart_circ_empty(xmit))
548 imx_uart_stop_tx(&sport->port);
549 }
550
551 static void imx_uart_dma_tx_callback(void *data)
552 {
553 struct imx_port *sport = data;
554 struct scatterlist *sgl = &sport->tx_sgl[0];
555 struct circ_buf *xmit = &sport->port.state->xmit;
556 unsigned long flags;
557 u32 ucr1;
558
559 spin_lock_irqsave(&sport->port.lock, flags);
560
561 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
562
563 ucr1 = imx_uart_readl(sport, UCR1);
564 ucr1 &= ~UCR1_TXDMAEN;
565 imx_uart_writel(sport, ucr1, UCR1);
566
567 /* update the stat */
568 xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1);
569 sport->port.icount.tx += sport->tx_bytes;
570
571 dev_dbg(sport->port.dev, "we finish the TX DMA.\n");
572
573 sport->dma_is_txing = 0;
574
575 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
576 uart_write_wakeup(&sport->port);
577
578 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port))
579 imx_uart_dma_tx(sport);
580 else if (sport->port.rs485.flags & SER_RS485_ENABLED) {
581 u32 ucr4 = imx_uart_readl(sport, UCR4);
582 ucr4 |= UCR4_TCEN;
583 imx_uart_writel(sport, ucr4, UCR4);
584 }
585
586 spin_unlock_irqrestore(&sport->port.lock, flags);
587 }
588
589 /* called with port.lock taken and irqs off */
590 static void imx_uart_dma_tx(struct imx_port *sport)
591 {
592 struct circ_buf *xmit = &sport->port.state->xmit;
593 struct scatterlist *sgl = sport->tx_sgl;
594 struct dma_async_tx_descriptor *desc;
595 struct dma_chan *chan = sport->dma_chan_tx;
596 struct device *dev = sport->port.dev;
597 u32 ucr1, ucr4;
598 int ret;
599
600 if (sport->dma_is_txing)
601 return;
602
603 ucr4 = imx_uart_readl(sport, UCR4);
604 ucr4 &= ~UCR4_TCEN;
605 imx_uart_writel(sport, ucr4, UCR4);
606
607 sport->tx_bytes = uart_circ_chars_pending(xmit);
608
609 if (xmit->tail < xmit->head) {
610 sport->dma_tx_nents = 1;
611 sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes);
612 } else {
613 sport->dma_tx_nents = 2;
614 sg_init_table(sgl, 2);
615 sg_set_buf(sgl, xmit->buf + xmit->tail,
616 UART_XMIT_SIZE - xmit->tail);
617 sg_set_buf(sgl + 1, xmit->buf, xmit->head);
618 }
619
620 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
621 if (ret == 0) {
622 dev_err(dev, "DMA mapping error for TX.\n");
623 return;
624 }
625 desc = dmaengine_prep_slave_sg(chan, sgl, sport->dma_tx_nents,
626 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
627 if (!desc) {
628 dma_unmap_sg(dev, sgl, sport->dma_tx_nents,
629 DMA_TO_DEVICE);
630 dev_err(dev, "We cannot prepare for the TX slave dma!\n");
631 return;
632 }
633 desc->callback = imx_uart_dma_tx_callback;
634 desc->callback_param = sport;
635
636 dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n",
637 uart_circ_chars_pending(xmit));
638
639 ucr1 = imx_uart_readl(sport, UCR1);
640 ucr1 |= UCR1_TXDMAEN;
641 imx_uart_writel(sport, ucr1, UCR1);
642
643 /* fire it */
644 sport->dma_is_txing = 1;
645 dmaengine_submit(desc);
646 dma_async_issue_pending(chan);
647 return;
648 }
649
650 /* called with port.lock taken and irqs off */
651 static void imx_uart_start_tx(struct uart_port *port)
652 {
653 struct imx_port *sport = (struct imx_port *)port;
654 u32 ucr1;
655
656 if (!sport->port.x_char && uart_circ_empty(&port->state->xmit))
657 return;
658
659 if (port->rs485.flags & SER_RS485_ENABLED) {
660 u32 ucr2;
661
662 ucr2 = imx_uart_readl(sport, UCR2);
663 if (port->rs485.flags & SER_RS485_RTS_ON_SEND)
664 imx_uart_rts_active(sport, &ucr2);
665 else
666 imx_uart_rts_inactive(sport, &ucr2);
667 imx_uart_writel(sport, ucr2, UCR2);
668
669 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX))
670 imx_uart_stop_rx(port);
671
672 /*
673 * Enable transmitter and shifter empty irq only if DMA is off.
674 * In the DMA case this is done in the tx-callback.
675 */
676 if (!sport->dma_is_enabled) {
677 u32 ucr4 = imx_uart_readl(sport, UCR4);
678 ucr4 |= UCR4_TCEN;
679 imx_uart_writel(sport, ucr4, UCR4);
680 }
681 }
682
683 if (!sport->dma_is_enabled) {
684 ucr1 = imx_uart_readl(sport, UCR1);
685 imx_uart_writel(sport, ucr1 | UCR1_TXMPTYEN, UCR1);
686 }
687
688 if (sport->dma_is_enabled) {
689 if (sport->port.x_char) {
690 /* We have X-char to send, so enable TX IRQ and
691 * disable TX DMA to let TX interrupt to send X-char */
692 ucr1 = imx_uart_readl(sport, UCR1);
693 ucr1 &= ~UCR1_TXDMAEN;
694 ucr1 |= UCR1_TXMPTYEN;
695 imx_uart_writel(sport, ucr1, UCR1);
696 return;
697 }
698
699 if (!uart_circ_empty(&port->state->xmit) &&
700 !uart_tx_stopped(port))
701 imx_uart_dma_tx(sport);
702 return;
703 }
704 }
705
706 static irqreturn_t imx_uart_rtsint(int irq, void *dev_id)
707 {
708 struct imx_port *sport = dev_id;
709 u32 usr1;
710
711 spin_lock(&sport->port.lock);
712
713 imx_uart_writel(sport, USR1_RTSD, USR1);
714 usr1 = imx_uart_readl(sport, USR1) & USR1_RTSS;
715 uart_handle_cts_change(&sport->port, !!usr1);
716 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
717
718 spin_unlock(&sport->port.lock);
719 return IRQ_HANDLED;
720 }
721
722 static irqreturn_t imx_uart_txint(int irq, void *dev_id)
723 {
724 struct imx_port *sport = dev_id;
725
726 spin_lock(&sport->port.lock);
727 imx_uart_transmit_buffer(sport);
728 spin_unlock(&sport->port.lock);
729 return IRQ_HANDLED;
730 }
731
732 static irqreturn_t imx_uart_rxint(int irq, void *dev_id)
733 {
734 struct imx_port *sport = dev_id;
735 unsigned int rx, flg, ignored = 0;
736 struct tty_port *port = &sport->port.state->port;
737
738 spin_lock(&sport->port.lock);
739
740 while (imx_uart_readl(sport, USR2) & USR2_RDR) {
741 u32 usr2;
742
743 flg = TTY_NORMAL;
744 sport->port.icount.rx++;
745
746 rx = imx_uart_readl(sport, URXD0);
747
748 usr2 = imx_uart_readl(sport, USR2);
749 if (usr2 & USR2_BRCD) {
750 imx_uart_writel(sport, USR2_BRCD, USR2);
751 if (uart_handle_break(&sport->port))
752 continue;
753 }
754
755 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
756 continue;
757
758 if (unlikely(rx & URXD_ERR)) {
759 if (rx & URXD_BRK)
760 sport->port.icount.brk++;
761 else if (rx & URXD_PRERR)
762 sport->port.icount.parity++;
763 else if (rx & URXD_FRMERR)
764 sport->port.icount.frame++;
765 if (rx & URXD_OVRRUN)
766 sport->port.icount.overrun++;
767
768 if (rx & sport->port.ignore_status_mask) {
769 if (++ignored > 100)
770 goto out;
771 continue;
772 }
773
774 rx &= (sport->port.read_status_mask | 0xFF);
775
776 if (rx & URXD_BRK)
777 flg = TTY_BREAK;
778 else if (rx & URXD_PRERR)
779 flg = TTY_PARITY;
780 else if (rx & URXD_FRMERR)
781 flg = TTY_FRAME;
782 if (rx & URXD_OVRRUN)
783 flg = TTY_OVERRUN;
784
785 #ifdef SUPPORT_SYSRQ
786 sport->port.sysrq = 0;
787 #endif
788 }
789
790 if (sport->port.ignore_status_mask & URXD_DUMMY_READ)
791 goto out;
792
793 if (tty_insert_flip_char(port, rx, flg) == 0)
794 sport->port.icount.buf_overrun++;
795 }
796
797 out:
798 spin_unlock(&sport->port.lock);
799 tty_flip_buffer_push(port);
800 return IRQ_HANDLED;
801 }
802
803 static void imx_uart_clear_rx_errors(struct imx_port *sport);
804
805 /*
806 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
807 */
808 static unsigned int imx_uart_get_hwmctrl(struct imx_port *sport)
809 {
810 unsigned int tmp = TIOCM_DSR;
811 unsigned usr1 = imx_uart_readl(sport, USR1);
812 unsigned usr2 = imx_uart_readl(sport, USR2);
813
814 if (usr1 & USR1_RTSS)
815 tmp |= TIOCM_CTS;
816
817 /* in DCE mode DCDIN is always 0 */
818 if (!(usr2 & USR2_DCDIN))
819 tmp |= TIOCM_CAR;
820
821 if (sport->dte_mode)
822 if (!(imx_uart_readl(sport, USR2) & USR2_RIIN))
823 tmp |= TIOCM_RI;
824
825 return tmp;
826 }
827
828 /*
829 * Handle any change of modem status signal since we were last called.
830 */
831 static void imx_uart_mctrl_check(struct imx_port *sport)
832 {
833 unsigned int status, changed;
834
835 status = imx_uart_get_hwmctrl(sport);
836 changed = status ^ sport->old_status;
837
838 if (changed == 0)
839 return;
840
841 sport->old_status = status;
842
843 if (changed & TIOCM_RI && status & TIOCM_RI)
844 sport->port.icount.rng++;
845 if (changed & TIOCM_DSR)
846 sport->port.icount.dsr++;
847 if (changed & TIOCM_CAR)
848 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
849 if (changed & TIOCM_CTS)
850 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
851
852 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
853 }
854
855 static irqreturn_t imx_uart_int(int irq, void *dev_id)
856 {
857 struct imx_port *sport = dev_id;
858 unsigned int usr1, usr2, ucr1, ucr2, ucr3, ucr4;
859 irqreturn_t ret = IRQ_NONE;
860
861 usr1 = imx_uart_readl(sport, USR1);
862 usr2 = imx_uart_readl(sport, USR2);
863 ucr1 = imx_uart_readl(sport, UCR1);
864 ucr2 = imx_uart_readl(sport, UCR2);
865 ucr3 = imx_uart_readl(sport, UCR3);
866 ucr4 = imx_uart_readl(sport, UCR4);
867
868 /*
869 * Even if a condition is true that can trigger an irq only handle it if
870 * the respective irq source is enabled. This prevents some undesired
871 * actions, for example if a character that sits in the RX FIFO and that
872 * should be fetched via DMA is tried to be fetched using PIO. Or the
873 * receiver is currently off and so reading from URXD0 results in an
874 * exception. So just mask the (raw) status bits for disabled irqs.
875 */
876 if ((ucr1 & UCR1_RRDYEN) == 0)
877 usr1 &= ~USR1_RRDY;
878 if ((ucr2 & UCR2_ATEN) == 0)
879 usr1 &= ~USR1_AGTIM;
880 if ((ucr1 & UCR1_TXMPTYEN) == 0)
881 usr1 &= ~USR1_TRDY;
882 if ((ucr4 & UCR4_TCEN) == 0)
883 usr2 &= ~USR2_TXDC;
884 if ((ucr3 & UCR3_DTRDEN) == 0)
885 usr1 &= ~USR1_DTRD;
886 if ((ucr1 & UCR1_RTSDEN) == 0)
887 usr1 &= ~USR1_RTSD;
888 if ((ucr3 & UCR3_AWAKEN) == 0)
889 usr1 &= ~USR1_AWAKE;
890 if ((ucr4 & UCR4_OREN) == 0)
891 usr2 &= ~USR2_ORE;
892
893 if (usr1 & (USR1_RRDY | USR1_AGTIM)) {
894 imx_uart_rxint(irq, dev_id);
895 ret = IRQ_HANDLED;
896 }
897
898 if ((usr1 & USR1_TRDY) || (usr2 & USR2_TXDC)) {
899 imx_uart_txint(irq, dev_id);
900 ret = IRQ_HANDLED;
901 }
902
903 if (usr1 & USR1_DTRD) {
904 imx_uart_writel(sport, USR1_DTRD, USR1);
905
906 spin_lock(&sport->port.lock);
907 imx_uart_mctrl_check(sport);
908 spin_unlock(&sport->port.lock);
909
910 ret = IRQ_HANDLED;
911 }
912
913 if (usr1 & USR1_RTSD) {
914 imx_uart_rtsint(irq, dev_id);
915 ret = IRQ_HANDLED;
916 }
917
918 if (usr1 & USR1_AWAKE) {
919 imx_uart_writel(sport, USR1_AWAKE, USR1);
920 ret = IRQ_HANDLED;
921 }
922
923 if (usr2 & USR2_ORE) {
924 sport->port.icount.overrun++;
925 imx_uart_writel(sport, USR2_ORE, USR2);
926 ret = IRQ_HANDLED;
927 }
928
929 return ret;
930 }
931
932 /*
933 * Return TIOCSER_TEMT when transmitter is not busy.
934 */
935 static unsigned int imx_uart_tx_empty(struct uart_port *port)
936 {
937 struct imx_port *sport = (struct imx_port *)port;
938 unsigned int ret;
939
940 ret = (imx_uart_readl(sport, USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
941
942 /* If the TX DMA is working, return 0. */
943 if (sport->dma_is_txing)
944 ret = 0;
945
946 return ret;
947 }
948
949 /* called with port.lock taken and irqs off */
950 static unsigned int imx_uart_get_mctrl(struct uart_port *port)
951 {
952 struct imx_port *sport = (struct imx_port *)port;
953 unsigned int ret = imx_uart_get_hwmctrl(sport);
954
955 mctrl_gpio_get(sport->gpios, &ret);
956
957 return ret;
958 }
959
960 /* called with port.lock taken and irqs off */
961 static void imx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
962 {
963 struct imx_port *sport = (struct imx_port *)port;
964 u32 ucr3, uts;
965
966 if (!(port->rs485.flags & SER_RS485_ENABLED)) {
967 u32 ucr2;
968
969 ucr2 = imx_uart_readl(sport, UCR2);
970 ucr2 &= ~(UCR2_CTS | UCR2_CTSC);
971 if (mctrl & TIOCM_RTS)
972 ucr2 |= UCR2_CTS | UCR2_CTSC;
973 imx_uart_writel(sport, ucr2, UCR2);
974 }
975
976 ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_DSR;
977 if (!(mctrl & TIOCM_DTR))
978 ucr3 |= UCR3_DSR;
979 imx_uart_writel(sport, ucr3, UCR3);
980
981 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport)) & ~UTS_LOOP;
982 if (mctrl & TIOCM_LOOP)
983 uts |= UTS_LOOP;
984 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
985
986 mctrl_gpio_set(sport->gpios, mctrl);
987 }
988
989 /*
990 * Interrupts always disabled.
991 */
992 static void imx_uart_break_ctl(struct uart_port *port, int break_state)
993 {
994 struct imx_port *sport = (struct imx_port *)port;
995 unsigned long flags;
996 u32 ucr1;
997
998 spin_lock_irqsave(&sport->port.lock, flags);
999
1000 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_SNDBRK;
1001
1002 if (break_state != 0)
1003 ucr1 |= UCR1_SNDBRK;
1004
1005 imx_uart_writel(sport, ucr1, UCR1);
1006
1007 spin_unlock_irqrestore(&sport->port.lock, flags);
1008 }
1009
1010 /*
1011 * This is our per-port timeout handler, for checking the
1012 * modem status signals.
1013 */
1014 static void imx_uart_timeout(struct timer_list *t)
1015 {
1016 struct imx_port *sport = from_timer(sport, t, timer);
1017 unsigned long flags;
1018
1019 if (sport->port.state) {
1020 spin_lock_irqsave(&sport->port.lock, flags);
1021 imx_uart_mctrl_check(sport);
1022 spin_unlock_irqrestore(&sport->port.lock, flags);
1023
1024 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
1025 }
1026 }
1027
1028 #define RX_BUF_SIZE (PAGE_SIZE)
1029
1030 /*
1031 * There are two kinds of RX DMA interrupts(such as in the MX6Q):
1032 * [1] the RX DMA buffer is full.
1033 * [2] the aging timer expires
1034 *
1035 * Condition [2] is triggered when a character has been sitting in the FIFO
1036 * for at least 8 byte durations.
1037 */
1038 static void imx_uart_dma_rx_callback(void *data)
1039 {
1040 struct imx_port *sport = data;
1041 struct dma_chan *chan = sport->dma_chan_rx;
1042 struct scatterlist *sgl = &sport->rx_sgl;
1043 struct tty_port *port = &sport->port.state->port;
1044 struct dma_tx_state state;
1045 struct circ_buf *rx_ring = &sport->rx_ring;
1046 enum dma_status status;
1047 unsigned int w_bytes = 0;
1048 unsigned int r_bytes;
1049 unsigned int bd_size;
1050
1051 status = dmaengine_tx_status(chan, sport->rx_cookie, &state);
1052
1053 if (status == DMA_ERROR) {
1054 imx_uart_clear_rx_errors(sport);
1055 return;
1056 }
1057
1058 if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) {
1059
1060 /*
1061 * The state-residue variable represents the empty space
1062 * relative to the entire buffer. Taking this in consideration
1063 * the head is always calculated base on the buffer total
1064 * length - DMA transaction residue. The UART script from the
1065 * SDMA firmware will jump to the next buffer descriptor,
1066 * once a DMA transaction if finalized (IMX53 RM - A.4.1.2.4).
1067 * Taking this in consideration the tail is always at the
1068 * beginning of the buffer descriptor that contains the head.
1069 */
1070
1071 /* Calculate the head */
1072 rx_ring->head = sg_dma_len(sgl) - state.residue;
1073
1074 /* Calculate the tail. */
1075 bd_size = sg_dma_len(sgl) / sport->rx_periods;
1076 rx_ring->tail = ((rx_ring->head-1) / bd_size) * bd_size;
1077
1078 if (rx_ring->head <= sg_dma_len(sgl) &&
1079 rx_ring->head > rx_ring->tail) {
1080
1081 /* Move data from tail to head */
1082 r_bytes = rx_ring->head - rx_ring->tail;
1083
1084 /* CPU claims ownership of RX DMA buffer */
1085 dma_sync_sg_for_cpu(sport->port.dev, sgl, 1,
1086 DMA_FROM_DEVICE);
1087
1088 w_bytes = tty_insert_flip_string(port,
1089 sport->rx_buf + rx_ring->tail, r_bytes);
1090
1091 /* UART retrieves ownership of RX DMA buffer */
1092 dma_sync_sg_for_device(sport->port.dev, sgl, 1,
1093 DMA_FROM_DEVICE);
1094
1095 if (w_bytes != r_bytes)
1096 sport->port.icount.buf_overrun++;
1097
1098 sport->port.icount.rx += w_bytes;
1099 } else {
1100 WARN_ON(rx_ring->head > sg_dma_len(sgl));
1101 WARN_ON(rx_ring->head <= rx_ring->tail);
1102 }
1103 }
1104
1105 if (w_bytes) {
1106 tty_flip_buffer_push(port);
1107 dev_dbg(sport->port.dev, "We get %d bytes.\n", w_bytes);
1108 }
1109 }
1110
1111 /* RX DMA buffer periods */
1112 #define RX_DMA_PERIODS 4
1113
1114 static int imx_uart_start_rx_dma(struct imx_port *sport)
1115 {
1116 struct scatterlist *sgl = &sport->rx_sgl;
1117 struct dma_chan *chan = sport->dma_chan_rx;
1118 struct device *dev = sport->port.dev;
1119 struct dma_async_tx_descriptor *desc;
1120 int ret;
1121
1122 sport->rx_ring.head = 0;
1123 sport->rx_ring.tail = 0;
1124 sport->rx_periods = RX_DMA_PERIODS;
1125
1126 sg_init_one(sgl, sport->rx_buf, RX_BUF_SIZE);
1127 ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE);
1128 if (ret == 0) {
1129 dev_err(dev, "DMA mapping error for RX.\n");
1130 return -EINVAL;
1131 }
1132
1133 desc = dmaengine_prep_dma_cyclic(chan, sg_dma_address(sgl),
1134 sg_dma_len(sgl), sg_dma_len(sgl) / sport->rx_periods,
1135 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
1136
1137 if (!desc) {
1138 dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE);
1139 dev_err(dev, "We cannot prepare for the RX slave dma!\n");
1140 return -EINVAL;
1141 }
1142 desc->callback = imx_uart_dma_rx_callback;
1143 desc->callback_param = sport;
1144
1145 dev_dbg(dev, "RX: prepare for the DMA.\n");
1146 sport->dma_is_rxing = 1;
1147 sport->rx_cookie = dmaengine_submit(desc);
1148 dma_async_issue_pending(chan);
1149 return 0;
1150 }
1151
1152 static void imx_uart_clear_rx_errors(struct imx_port *sport)
1153 {
1154 struct tty_port *port = &sport->port.state->port;
1155 u32 usr1, usr2;
1156
1157 usr1 = imx_uart_readl(sport, USR1);
1158 usr2 = imx_uart_readl(sport, USR2);
1159
1160 if (usr2 & USR2_BRCD) {
1161 sport->port.icount.brk++;
1162 imx_uart_writel(sport, USR2_BRCD, USR2);
1163 uart_handle_break(&sport->port);
1164 if (tty_insert_flip_char(port, 0, TTY_BREAK) == 0)
1165 sport->port.icount.buf_overrun++;
1166 tty_flip_buffer_push(port);
1167 } else {
1168 if (usr1 & USR1_FRAMERR) {
1169 sport->port.icount.frame++;
1170 imx_uart_writel(sport, USR1_FRAMERR, USR1);
1171 } else if (usr1 & USR1_PARITYERR) {
1172 sport->port.icount.parity++;
1173 imx_uart_writel(sport, USR1_PARITYERR, USR1);
1174 }
1175 }
1176
1177 if (usr2 & USR2_ORE) {
1178 sport->port.icount.overrun++;
1179 imx_uart_writel(sport, USR2_ORE, USR2);
1180 }
1181
1182 }
1183
1184 #define TXTL_DEFAULT 2 /* reset default */
1185 #define RXTL_DEFAULT 1 /* reset default */
1186 #define TXTL_DMA 8 /* DMA burst setting */
1187 #define RXTL_DMA 9 /* DMA burst setting */
1188
1189 static void imx_uart_setup_ufcr(struct imx_port *sport,
1190 unsigned char txwl, unsigned char rxwl)
1191 {
1192 unsigned int val;
1193
1194 /* set receiver / transmitter trigger level */
1195 val = imx_uart_readl(sport, UFCR) & (UFCR_RFDIV | UFCR_DCEDTE);
1196 val |= txwl << UFCR_TXTL_SHF | rxwl;
1197 imx_uart_writel(sport, val, UFCR);
1198 }
1199
1200 static void imx_uart_dma_exit(struct imx_port *sport)
1201 {
1202 if (sport->dma_chan_rx) {
1203 dmaengine_terminate_sync(sport->dma_chan_rx);
1204 dma_release_channel(sport->dma_chan_rx);
1205 sport->dma_chan_rx = NULL;
1206 sport->rx_cookie = -EINVAL;
1207 kfree(sport->rx_buf);
1208 sport->rx_buf = NULL;
1209 }
1210
1211 if (sport->dma_chan_tx) {
1212 dmaengine_terminate_sync(sport->dma_chan_tx);
1213 dma_release_channel(sport->dma_chan_tx);
1214 sport->dma_chan_tx = NULL;
1215 }
1216 }
1217
1218 static int imx_uart_dma_init(struct imx_port *sport)
1219 {
1220 struct dma_slave_config slave_config = {};
1221 struct device *dev = sport->port.dev;
1222 int ret;
1223
1224 /* Prepare for RX : */
1225 sport->dma_chan_rx = dma_request_slave_channel(dev, "rx");
1226 if (!sport->dma_chan_rx) {
1227 dev_dbg(dev, "cannot get the DMA channel.\n");
1228 ret = -EINVAL;
1229 goto err;
1230 }
1231
1232 slave_config.direction = DMA_DEV_TO_MEM;
1233 slave_config.src_addr = sport->port.mapbase + URXD0;
1234 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1235 /* one byte less than the watermark level to enable the aging timer */
1236 slave_config.src_maxburst = RXTL_DMA - 1;
1237 ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config);
1238 if (ret) {
1239 dev_err(dev, "error in RX dma configuration.\n");
1240 goto err;
1241 }
1242
1243 sport->rx_buf = kzalloc(RX_BUF_SIZE, GFP_KERNEL);
1244 if (!sport->rx_buf) {
1245 ret = -ENOMEM;
1246 goto err;
1247 }
1248 sport->rx_ring.buf = sport->rx_buf;
1249
1250 /* Prepare for TX : */
1251 sport->dma_chan_tx = dma_request_slave_channel(dev, "tx");
1252 if (!sport->dma_chan_tx) {
1253 dev_err(dev, "cannot get the TX DMA channel!\n");
1254 ret = -EINVAL;
1255 goto err;
1256 }
1257
1258 slave_config.direction = DMA_MEM_TO_DEV;
1259 slave_config.dst_addr = sport->port.mapbase + URTX0;
1260 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1261 slave_config.dst_maxburst = TXTL_DMA;
1262 ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config);
1263 if (ret) {
1264 dev_err(dev, "error in TX dma configuration.");
1265 goto err;
1266 }
1267
1268 return 0;
1269 err:
1270 imx_uart_dma_exit(sport);
1271 return ret;
1272 }
1273
1274 static void imx_uart_enable_dma(struct imx_port *sport)
1275 {
1276 u32 ucr1;
1277
1278 imx_uart_setup_ufcr(sport, TXTL_DMA, RXTL_DMA);
1279
1280 /* set UCR1 */
1281 ucr1 = imx_uart_readl(sport, UCR1);
1282 ucr1 |= UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN;
1283 imx_uart_writel(sport, ucr1, UCR1);
1284
1285 sport->dma_is_enabled = 1;
1286 }
1287
1288 static void imx_uart_disable_dma(struct imx_port *sport)
1289 {
1290 u32 ucr1;
1291
1292 /* clear UCR1 */
1293 ucr1 = imx_uart_readl(sport, UCR1);
1294 ucr1 &= ~(UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN);
1295 imx_uart_writel(sport, ucr1, UCR1);
1296
1297 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1298
1299 sport->dma_is_enabled = 0;
1300 }
1301
1302 /* half the RX buffer size */
1303 #define CTSTL 16
1304
1305 static int imx_uart_startup(struct uart_port *port)
1306 {
1307 struct imx_port *sport = (struct imx_port *)port;
1308 int retval, i;
1309 unsigned long flags;
1310 int dma_is_inited = 0;
1311 u32 ucr1, ucr2, ucr4;
1312
1313 retval = clk_prepare_enable(sport->clk_per);
1314 if (retval)
1315 return retval;
1316 retval = clk_prepare_enable(sport->clk_ipg);
1317 if (retval) {
1318 clk_disable_unprepare(sport->clk_per);
1319 return retval;
1320 }
1321
1322 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1323
1324 /* disable the DREN bit (Data Ready interrupt enable) before
1325 * requesting IRQs
1326 */
1327 ucr4 = imx_uart_readl(sport, UCR4);
1328
1329 /* set the trigger level for CTS */
1330 ucr4 &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF);
1331 ucr4 |= CTSTL << UCR4_CTSTL_SHF;
1332
1333 imx_uart_writel(sport, ucr4 & ~UCR4_DREN, UCR4);
1334
1335 /* Can we enable the DMA support? */
1336 if (!uart_console(port) && imx_uart_dma_init(sport) == 0)
1337 dma_is_inited = 1;
1338
1339 spin_lock_irqsave(&sport->port.lock, flags);
1340 /* Reset fifo's and state machines */
1341 i = 100;
1342
1343 ucr2 = imx_uart_readl(sport, UCR2);
1344 ucr2 &= ~UCR2_SRST;
1345 imx_uart_writel(sport, ucr2, UCR2);
1346
1347 while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0))
1348 udelay(1);
1349
1350 /*
1351 * Finally, clear and enable interrupts
1352 */
1353 imx_uart_writel(sport, USR1_RTSD | USR1_DTRD, USR1);
1354 imx_uart_writel(sport, USR2_ORE, USR2);
1355
1356 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_RRDYEN;
1357 ucr1 |= UCR1_UARTEN;
1358 if (sport->have_rtscts)
1359 ucr1 |= UCR1_RTSDEN;
1360
1361 imx_uart_writel(sport, ucr1, UCR1);
1362
1363 ucr4 = imx_uart_readl(sport, UCR4) & ~UCR4_OREN;
1364 if (!sport->dma_is_enabled)
1365 ucr4 |= UCR4_OREN;
1366 imx_uart_writel(sport, ucr4, UCR4);
1367
1368 ucr2 = imx_uart_readl(sport, UCR2) & ~UCR2_ATEN;
1369 ucr2 |= (UCR2_RXEN | UCR2_TXEN);
1370 if (!sport->have_rtscts)
1371 ucr2 |= UCR2_IRTS;
1372 /*
1373 * make sure the edge sensitive RTS-irq is disabled,
1374 * we're using RTSD instead.
1375 */
1376 if (!imx_uart_is_imx1(sport))
1377 ucr2 &= ~UCR2_RTSEN;
1378 imx_uart_writel(sport, ucr2, UCR2);
1379
1380 if (!imx_uart_is_imx1(sport)) {
1381 u32 ucr3;
1382
1383 ucr3 = imx_uart_readl(sport, UCR3);
1384
1385 ucr3 |= UCR3_DTRDEN | UCR3_RI | UCR3_DCD;
1386
1387 if (sport->dte_mode)
1388 /* disable broken interrupts */
1389 ucr3 &= ~(UCR3_RI | UCR3_DCD);
1390
1391 imx_uart_writel(sport, ucr3, UCR3);
1392 }
1393
1394 /*
1395 * Enable modem status interrupts
1396 */
1397 imx_uart_enable_ms(&sport->port);
1398
1399 if (dma_is_inited) {
1400 imx_uart_enable_dma(sport);
1401 imx_uart_start_rx_dma(sport);
1402 } else {
1403 ucr1 = imx_uart_readl(sport, UCR1);
1404 ucr1 |= UCR1_RRDYEN;
1405 imx_uart_writel(sport, ucr1, UCR1);
1406
1407 ucr2 = imx_uart_readl(sport, UCR2);
1408 ucr2 |= UCR2_ATEN;
1409 imx_uart_writel(sport, ucr2, UCR2);
1410 }
1411
1412 spin_unlock_irqrestore(&sport->port.lock, flags);
1413
1414 return 0;
1415 }
1416
1417 static void imx_uart_shutdown(struct uart_port *port)
1418 {
1419 struct imx_port *sport = (struct imx_port *)port;
1420 unsigned long flags;
1421 u32 ucr1, ucr2, ucr4;
1422
1423 if (sport->dma_is_enabled) {
1424 dmaengine_terminate_sync(sport->dma_chan_tx);
1425 if (sport->dma_is_txing) {
1426 dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0],
1427 sport->dma_tx_nents, DMA_TO_DEVICE);
1428 sport->dma_is_txing = 0;
1429 }
1430 dmaengine_terminate_sync(sport->dma_chan_rx);
1431 if (sport->dma_is_rxing) {
1432 dma_unmap_sg(sport->port.dev, &sport->rx_sgl,
1433 1, DMA_FROM_DEVICE);
1434 sport->dma_is_rxing = 0;
1435 }
1436
1437 spin_lock_irqsave(&sport->port.lock, flags);
1438 imx_uart_stop_tx(port);
1439 imx_uart_stop_rx(port);
1440 imx_uart_disable_dma(sport);
1441 spin_unlock_irqrestore(&sport->port.lock, flags);
1442 imx_uart_dma_exit(sport);
1443 }
1444
1445 mctrl_gpio_disable_ms(sport->gpios);
1446
1447 spin_lock_irqsave(&sport->port.lock, flags);
1448 ucr2 = imx_uart_readl(sport, UCR2);
1449 ucr2 &= ~(UCR2_TXEN | UCR2_ATEN);
1450 imx_uart_writel(sport, ucr2, UCR2);
1451
1452 ucr4 = imx_uart_readl(sport, UCR4);
1453 ucr4 &= ~UCR4_OREN;
1454 imx_uart_writel(sport, ucr4, UCR4);
1455 spin_unlock_irqrestore(&sport->port.lock, flags);
1456
1457 /*
1458 * Stop our timer.
1459 */
1460 del_timer_sync(&sport->timer);
1461
1462 /*
1463 * Disable all interrupts, port and break condition.
1464 */
1465
1466 spin_lock_irqsave(&sport->port.lock, flags);
1467 ucr1 = imx_uart_readl(sport, UCR1);
1468 ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN | UCR1_RXDMAEN | UCR1_ATDMAEN);
1469
1470 imx_uart_writel(sport, ucr1, UCR1);
1471 spin_unlock_irqrestore(&sport->port.lock, flags);
1472
1473 clk_disable_unprepare(sport->clk_per);
1474 clk_disable_unprepare(sport->clk_ipg);
1475 }
1476
1477 /* called with port.lock taken and irqs off */
1478 static void imx_uart_flush_buffer(struct uart_port *port)
1479 {
1480 struct imx_port *sport = (struct imx_port *)port;
1481 struct scatterlist *sgl = &sport->tx_sgl[0];
1482 u32 ucr2;
1483 int i = 100, ubir, ubmr, uts;
1484
1485 if (!sport->dma_chan_tx)
1486 return;
1487
1488 sport->tx_bytes = 0;
1489 dmaengine_terminate_all(sport->dma_chan_tx);
1490 if (sport->dma_is_txing) {
1491 u32 ucr1;
1492
1493 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents,
1494 DMA_TO_DEVICE);
1495 ucr1 = imx_uart_readl(sport, UCR1);
1496 ucr1 &= ~UCR1_TXDMAEN;
1497 imx_uart_writel(sport, ucr1, UCR1);
1498 sport->dma_is_txing = 0;
1499 }
1500
1501 /*
1502 * According to the Reference Manual description of the UART SRST bit:
1503 *
1504 * "Reset the transmit and receive state machines,
1505 * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD
1506 * and UTS[6-3]".
1507 *
1508 * We don't need to restore the old values from USR1, USR2, URXD and
1509 * UTXD. UBRC is read only, so only save/restore the other three
1510 * registers.
1511 */
1512 ubir = imx_uart_readl(sport, UBIR);
1513 ubmr = imx_uart_readl(sport, UBMR);
1514 uts = imx_uart_readl(sport, IMX21_UTS);
1515
1516 ucr2 = imx_uart_readl(sport, UCR2);
1517 ucr2 &= ~UCR2_SRST;
1518 imx_uart_writel(sport, ucr2, UCR2);
1519
1520 while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0))
1521 udelay(1);
1522
1523 /* Restore the registers */
1524 imx_uart_writel(sport, ubir, UBIR);
1525 imx_uart_writel(sport, ubmr, UBMR);
1526 imx_uart_writel(sport, uts, IMX21_UTS);
1527 }
1528
1529 static void
1530 imx_uart_set_termios(struct uart_port *port, struct ktermios *termios,
1531 struct ktermios *old)
1532 {
1533 struct imx_port *sport = (struct imx_port *)port;
1534 unsigned long flags;
1535 u32 ucr2, old_ucr1, old_ucr2, ufcr;
1536 unsigned int baud, quot;
1537 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1538 unsigned long div;
1539 unsigned long num, denom;
1540 uint64_t tdiv64;
1541
1542 /*
1543 * We only support CS7 and CS8.
1544 */
1545 while ((termios->c_cflag & CSIZE) != CS7 &&
1546 (termios->c_cflag & CSIZE) != CS8) {
1547 termios->c_cflag &= ~CSIZE;
1548 termios->c_cflag |= old_csize;
1549 old_csize = CS8;
1550 }
1551
1552 if ((termios->c_cflag & CSIZE) == CS8)
1553 ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS;
1554 else
1555 ucr2 = UCR2_SRST | UCR2_IRTS;
1556
1557 if (termios->c_cflag & CRTSCTS) {
1558 if (sport->have_rtscts) {
1559 ucr2 &= ~UCR2_IRTS;
1560
1561 if (port->rs485.flags & SER_RS485_ENABLED) {
1562 /*
1563 * RTS is mandatory for rs485 operation, so keep
1564 * it under manual control and keep transmitter
1565 * disabled.
1566 */
1567 if (port->rs485.flags &
1568 SER_RS485_RTS_AFTER_SEND)
1569 imx_uart_rts_active(sport, &ucr2);
1570 else
1571 imx_uart_rts_inactive(sport, &ucr2);
1572 } else {
1573 imx_uart_rts_auto(sport, &ucr2);
1574 }
1575 } else {
1576 termios->c_cflag &= ~CRTSCTS;
1577 }
1578 } else if (port->rs485.flags & SER_RS485_ENABLED) {
1579 /* disable transmitter */
1580 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
1581 imx_uart_rts_active(sport, &ucr2);
1582 else
1583 imx_uart_rts_inactive(sport, &ucr2);
1584 }
1585
1586
1587 if (termios->c_cflag & CSTOPB)
1588 ucr2 |= UCR2_STPB;
1589 if (termios->c_cflag & PARENB) {
1590 ucr2 |= UCR2_PREN;
1591 if (termios->c_cflag & PARODD)
1592 ucr2 |= UCR2_PROE;
1593 }
1594
1595 del_timer_sync(&sport->timer);
1596
1597 /*
1598 * Ask the core to calculate the divisor for us.
1599 */
1600 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1601 quot = uart_get_divisor(port, baud);
1602
1603 spin_lock_irqsave(&sport->port.lock, flags);
1604
1605 sport->port.read_status_mask = 0;
1606 if (termios->c_iflag & INPCK)
1607 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
1608 if (termios->c_iflag & (BRKINT | PARMRK))
1609 sport->port.read_status_mask |= URXD_BRK;
1610
1611 /*
1612 * Characters to ignore
1613 */
1614 sport->port.ignore_status_mask = 0;
1615 if (termios->c_iflag & IGNPAR)
1616 sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR;
1617 if (termios->c_iflag & IGNBRK) {
1618 sport->port.ignore_status_mask |= URXD_BRK;
1619 /*
1620 * If we're ignoring parity and break indicators,
1621 * ignore overruns too (for real raw support).
1622 */
1623 if (termios->c_iflag & IGNPAR)
1624 sport->port.ignore_status_mask |= URXD_OVRRUN;
1625 }
1626
1627 if ((termios->c_cflag & CREAD) == 0)
1628 sport->port.ignore_status_mask |= URXD_DUMMY_READ;
1629
1630 /*
1631 * Update the per-port timeout.
1632 */
1633 uart_update_timeout(port, termios->c_cflag, baud);
1634
1635 /*
1636 * disable interrupts and drain transmitter
1637 */
1638 old_ucr1 = imx_uart_readl(sport, UCR1);
1639 imx_uart_writel(sport,
1640 old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
1641 UCR1);
1642 old_ucr2 = imx_uart_readl(sport, UCR2);
1643 imx_uart_writel(sport, old_ucr2 & ~UCR2_ATEN, UCR2);
1644
1645 while (!(imx_uart_readl(sport, USR2) & USR2_TXDC))
1646 barrier();
1647
1648 /* then, disable everything */
1649 imx_uart_writel(sport, old_ucr2 & ~(UCR2_TXEN | UCR2_RXEN | UCR2_ATEN), UCR2);
1650 old_ucr2 &= (UCR2_TXEN | UCR2_RXEN | UCR2_ATEN);
1651
1652 /* custom-baudrate handling */
1653 div = sport->port.uartclk / (baud * 16);
1654 if (baud == 38400 && quot != div)
1655 baud = sport->port.uartclk / (quot * 16);
1656
1657 div = sport->port.uartclk / (baud * 16);
1658 if (div > 7)
1659 div = 7;
1660 if (!div)
1661 div = 1;
1662
1663 rational_best_approximation(16 * div * baud, sport->port.uartclk,
1664 1 << 16, 1 << 16, &num, &denom);
1665
1666 tdiv64 = sport->port.uartclk;
1667 tdiv64 *= num;
1668 do_div(tdiv64, denom * 16 * div);
1669 tty_termios_encode_baud_rate(termios,
1670 (speed_t)tdiv64, (speed_t)tdiv64);
1671
1672 num -= 1;
1673 denom -= 1;
1674
1675 ufcr = imx_uart_readl(sport, UFCR);
1676 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
1677 imx_uart_writel(sport, ufcr, UFCR);
1678
1679 imx_uart_writel(sport, num, UBIR);
1680 imx_uart_writel(sport, denom, UBMR);
1681
1682 if (!imx_uart_is_imx1(sport))
1683 imx_uart_writel(sport, sport->port.uartclk / div / 1000,
1684 IMX21_ONEMS);
1685
1686 imx_uart_writel(sport, old_ucr1, UCR1);
1687
1688 /* set the parity, stop bits and data size */
1689 imx_uart_writel(sport, ucr2 | old_ucr2, UCR2);
1690
1691 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
1692 imx_uart_enable_ms(&sport->port);
1693
1694 spin_unlock_irqrestore(&sport->port.lock, flags);
1695 }
1696
1697 static const char *imx_uart_type(struct uart_port *port)
1698 {
1699 struct imx_port *sport = (struct imx_port *)port;
1700
1701 return sport->port.type == PORT_IMX ? "IMX" : NULL;
1702 }
1703
1704 /*
1705 * Configure/autoconfigure the port.
1706 */
1707 static void imx_uart_config_port(struct uart_port *port, int flags)
1708 {
1709 struct imx_port *sport = (struct imx_port *)port;
1710
1711 if (flags & UART_CONFIG_TYPE)
1712 sport->port.type = PORT_IMX;
1713 }
1714
1715 /*
1716 * Verify the new serial_struct (for TIOCSSERIAL).
1717 * The only change we allow are to the flags and type, and
1718 * even then only between PORT_IMX and PORT_UNKNOWN
1719 */
1720 static int
1721 imx_uart_verify_port(struct uart_port *port, struct serial_struct *ser)
1722 {
1723 struct imx_port *sport = (struct imx_port *)port;
1724 int ret = 0;
1725
1726 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
1727 ret = -EINVAL;
1728 if (sport->port.irq != ser->irq)
1729 ret = -EINVAL;
1730 if (ser->io_type != UPIO_MEM)
1731 ret = -EINVAL;
1732 if (sport->port.uartclk / 16 != ser->baud_base)
1733 ret = -EINVAL;
1734 if (sport->port.mapbase != (unsigned long)ser->iomem_base)
1735 ret = -EINVAL;
1736 if (sport->port.iobase != ser->port)
1737 ret = -EINVAL;
1738 if (ser->hub6 != 0)
1739 ret = -EINVAL;
1740 return ret;
1741 }
1742
1743 #if defined(CONFIG_CONSOLE_POLL)
1744
1745 static int imx_uart_poll_init(struct uart_port *port)
1746 {
1747 struct imx_port *sport = (struct imx_port *)port;
1748 unsigned long flags;
1749 u32 ucr1, ucr2;
1750 int retval;
1751
1752 retval = clk_prepare_enable(sport->clk_ipg);
1753 if (retval)
1754 return retval;
1755 retval = clk_prepare_enable(sport->clk_per);
1756 if (retval)
1757 clk_disable_unprepare(sport->clk_ipg);
1758
1759 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1760
1761 spin_lock_irqsave(&sport->port.lock, flags);
1762
1763 /*
1764 * Be careful about the order of enabling bits here. First enable the
1765 * receiver (UARTEN + RXEN) and only then the corresponding irqs.
1766 * This prevents that a character that already sits in the RX fifo is
1767 * triggering an irq but the try to fetch it from there results in an
1768 * exception because UARTEN or RXEN is still off.
1769 */
1770 ucr1 = imx_uart_readl(sport, UCR1);
1771 ucr2 = imx_uart_readl(sport, UCR2);
1772
1773 if (imx_uart_is_imx1(sport))
1774 ucr1 |= IMX1_UCR1_UARTCLKEN;
1775
1776 ucr1 |= UCR1_UARTEN;
1777 ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RTSDEN | UCR1_RRDYEN);
1778
1779 ucr2 |= UCR2_RXEN;
1780 ucr2 &= ~UCR2_ATEN;
1781
1782 imx_uart_writel(sport, ucr1, UCR1);
1783 imx_uart_writel(sport, ucr2, UCR2);
1784
1785 /* now enable irqs */
1786 imx_uart_writel(sport, ucr1 | UCR1_RRDYEN, UCR1);
1787 imx_uart_writel(sport, ucr2 | UCR2_ATEN, UCR2);
1788
1789 spin_unlock_irqrestore(&sport->port.lock, flags);
1790
1791 return 0;
1792 }
1793
1794 static int imx_uart_poll_get_char(struct uart_port *port)
1795 {
1796 struct imx_port *sport = (struct imx_port *)port;
1797 if (!(imx_uart_readl(sport, USR2) & USR2_RDR))
1798 return NO_POLL_CHAR;
1799
1800 return imx_uart_readl(sport, URXD0) & URXD_RX_DATA;
1801 }
1802
1803 static void imx_uart_poll_put_char(struct uart_port *port, unsigned char c)
1804 {
1805 struct imx_port *sport = (struct imx_port *)port;
1806 unsigned int status;
1807
1808 /* drain */
1809 do {
1810 status = imx_uart_readl(sport, USR1);
1811 } while (~status & USR1_TRDY);
1812
1813 /* write */
1814 imx_uart_writel(sport, c, URTX0);
1815
1816 /* flush */
1817 do {
1818 status = imx_uart_readl(sport, USR2);
1819 } while (~status & USR2_TXDC);
1820 }
1821 #endif
1822
1823 /* called with port.lock taken and irqs off or from .probe without locking */
1824 static int imx_uart_rs485_config(struct uart_port *port,
1825 struct serial_rs485 *rs485conf)
1826 {
1827 struct imx_port *sport = (struct imx_port *)port;
1828 u32 ucr2;
1829
1830 /* unimplemented */
1831 rs485conf->delay_rts_before_send = 0;
1832 rs485conf->delay_rts_after_send = 0;
1833
1834 /* RTS is required to control the transmitter */
1835 if (!sport->have_rtscts && !sport->have_rtsgpio)
1836 rs485conf->flags &= ~SER_RS485_ENABLED;
1837
1838 if (rs485conf->flags & SER_RS485_ENABLED) {
1839 /* Enable receiver if low-active RTS signal is requested */
1840 if (sport->have_rtscts && !sport->have_rtsgpio &&
1841 !(rs485conf->flags & SER_RS485_RTS_ON_SEND))
1842 rs485conf->flags |= SER_RS485_RX_DURING_TX;
1843
1844 /* disable transmitter */
1845 ucr2 = imx_uart_readl(sport, UCR2);
1846 if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND)
1847 imx_uart_rts_active(sport, &ucr2);
1848 else
1849 imx_uart_rts_inactive(sport, &ucr2);
1850 imx_uart_writel(sport, ucr2, UCR2);
1851 }
1852
1853 /* Make sure Rx is enabled in case Tx is active with Rx disabled */
1854 if (!(rs485conf->flags & SER_RS485_ENABLED) ||
1855 rs485conf->flags & SER_RS485_RX_DURING_TX)
1856 imx_uart_start_rx(port);
1857
1858 port->rs485 = *rs485conf;
1859
1860 return 0;
1861 }
1862
1863 static const struct uart_ops imx_uart_pops = {
1864 .tx_empty = imx_uart_tx_empty,
1865 .set_mctrl = imx_uart_set_mctrl,
1866 .get_mctrl = imx_uart_get_mctrl,
1867 .stop_tx = imx_uart_stop_tx,
1868 .start_tx = imx_uart_start_tx,
1869 .stop_rx = imx_uart_stop_rx,
1870 .enable_ms = imx_uart_enable_ms,
1871 .break_ctl = imx_uart_break_ctl,
1872 .startup = imx_uart_startup,
1873 .shutdown = imx_uart_shutdown,
1874 .flush_buffer = imx_uart_flush_buffer,
1875 .set_termios = imx_uart_set_termios,
1876 .type = imx_uart_type,
1877 .config_port = imx_uart_config_port,
1878 .verify_port = imx_uart_verify_port,
1879 #if defined(CONFIG_CONSOLE_POLL)
1880 .poll_init = imx_uart_poll_init,
1881 .poll_get_char = imx_uart_poll_get_char,
1882 .poll_put_char = imx_uart_poll_put_char,
1883 #endif
1884 };
1885
1886 static struct imx_port *imx_uart_ports[UART_NR];
1887
1888 #ifdef CONFIG_SERIAL_IMX_CONSOLE
1889 static void imx_uart_console_putchar(struct uart_port *port, int ch)
1890 {
1891 struct imx_port *sport = (struct imx_port *)port;
1892
1893 while (imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL)
1894 barrier();
1895
1896 imx_uart_writel(sport, ch, URTX0);
1897 }
1898
1899 /*
1900 * Interrupts are disabled on entering
1901 */
1902 static void
1903 imx_uart_console_write(struct console *co, const char *s, unsigned int count)
1904 {
1905 struct imx_port *sport = imx_uart_ports[co->index];
1906 struct imx_port_ucrs old_ucr;
1907 unsigned int ucr1;
1908 unsigned long flags = 0;
1909 int locked = 1;
1910 int retval;
1911
1912 retval = clk_enable(sport->clk_per);
1913 if (retval)
1914 return;
1915 retval = clk_enable(sport->clk_ipg);
1916 if (retval) {
1917 clk_disable(sport->clk_per);
1918 return;
1919 }
1920
1921 if (sport->port.sysrq)
1922 locked = 0;
1923 else if (oops_in_progress)
1924 locked = spin_trylock_irqsave(&sport->port.lock, flags);
1925 else
1926 spin_lock_irqsave(&sport->port.lock, flags);
1927
1928 /*
1929 * First, save UCR1/2/3 and then disable interrupts
1930 */
1931 imx_uart_ucrs_save(sport, &old_ucr);
1932 ucr1 = old_ucr.ucr1;
1933
1934 if (imx_uart_is_imx1(sport))
1935 ucr1 |= IMX1_UCR1_UARTCLKEN;
1936 ucr1 |= UCR1_UARTEN;
1937 ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN);
1938
1939 imx_uart_writel(sport, ucr1, UCR1);
1940
1941 imx_uart_writel(sport, old_ucr.ucr2 | UCR2_TXEN, UCR2);
1942
1943 uart_console_write(&sport->port, s, count, imx_uart_console_putchar);
1944
1945 /*
1946 * Finally, wait for transmitter to become empty
1947 * and restore UCR1/2/3
1948 */
1949 while (!(imx_uart_readl(sport, USR2) & USR2_TXDC));
1950
1951 imx_uart_ucrs_restore(sport, &old_ucr);
1952
1953 if (locked)
1954 spin_unlock_irqrestore(&sport->port.lock, flags);
1955
1956 clk_disable(sport->clk_ipg);
1957 clk_disable(sport->clk_per);
1958 }
1959
1960 /*
1961 * If the port was already initialised (eg, by a boot loader),
1962 * try to determine the current setup.
1963 */
1964 static void __init
1965 imx_uart_console_get_options(struct imx_port *sport, int *baud,
1966 int *parity, int *bits)
1967 {
1968
1969 if (imx_uart_readl(sport, UCR1) & UCR1_UARTEN) {
1970 /* ok, the port was enabled */
1971 unsigned int ucr2, ubir, ubmr, uartclk;
1972 unsigned int baud_raw;
1973 unsigned int ucfr_rfdiv;
1974
1975 ucr2 = imx_uart_readl(sport, UCR2);
1976
1977 *parity = 'n';
1978 if (ucr2 & UCR2_PREN) {
1979 if (ucr2 & UCR2_PROE)
1980 *parity = 'o';
1981 else
1982 *parity = 'e';
1983 }
1984
1985 if (ucr2 & UCR2_WS)
1986 *bits = 8;
1987 else
1988 *bits = 7;
1989
1990 ubir = imx_uart_readl(sport, UBIR) & 0xffff;
1991 ubmr = imx_uart_readl(sport, UBMR) & 0xffff;
1992
1993 ucfr_rfdiv = (imx_uart_readl(sport, UFCR) & UFCR_RFDIV) >> 7;
1994 if (ucfr_rfdiv == 6)
1995 ucfr_rfdiv = 7;
1996 else
1997 ucfr_rfdiv = 6 - ucfr_rfdiv;
1998
1999 uartclk = clk_get_rate(sport->clk_per);
2000 uartclk /= ucfr_rfdiv;
2001
2002 { /*
2003 * The next code provides exact computation of
2004 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
2005 * without need of float support or long long division,
2006 * which would be required to prevent 32bit arithmetic overflow
2007 */
2008 unsigned int mul = ubir + 1;
2009 unsigned int div = 16 * (ubmr + 1);
2010 unsigned int rem = uartclk % div;
2011
2012 baud_raw = (uartclk / div) * mul;
2013 baud_raw += (rem * mul + div / 2) / div;
2014 *baud = (baud_raw + 50) / 100 * 100;
2015 }
2016
2017 if (*baud != baud_raw)
2018 pr_info("Console IMX rounded baud rate from %d to %d\n",
2019 baud_raw, *baud);
2020 }
2021 }
2022
2023 static int __init
2024 imx_uart_console_setup(struct console *co, char *options)
2025 {
2026 struct imx_port *sport;
2027 int baud = 9600;
2028 int bits = 8;
2029 int parity = 'n';
2030 int flow = 'n';
2031 int retval;
2032
2033 /*
2034 * Check whether an invalid uart number has been specified, and
2035 * if so, search for the first available port that does have
2036 * console support.
2037 */
2038 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_uart_ports))
2039 co->index = 0;
2040 sport = imx_uart_ports[co->index];
2041 if (sport == NULL)
2042 return -ENODEV;
2043
2044 /* For setting the registers, we only need to enable the ipg clock. */
2045 retval = clk_prepare_enable(sport->clk_ipg);
2046 if (retval)
2047 goto error_console;
2048
2049 if (options)
2050 uart_parse_options(options, &baud, &parity, &bits, &flow);
2051 else
2052 imx_uart_console_get_options(sport, &baud, &parity, &bits);
2053
2054 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
2055
2056 retval = uart_set_options(&sport->port, co, baud, parity, bits, flow);
2057
2058 clk_disable(sport->clk_ipg);
2059 if (retval) {
2060 clk_unprepare(sport->clk_ipg);
2061 goto error_console;
2062 }
2063
2064 retval = clk_prepare(sport->clk_per);
2065 if (retval)
2066 clk_unprepare(sport->clk_ipg);
2067
2068 error_console:
2069 return retval;
2070 }
2071
2072 static struct uart_driver imx_uart_uart_driver;
2073 static struct console imx_uart_console = {
2074 .name = DEV_NAME,
2075 .write = imx_uart_console_write,
2076 .device = uart_console_device,
2077 .setup = imx_uart_console_setup,
2078 .flags = CON_PRINTBUFFER,
2079 .index = -1,
2080 .data = &imx_uart_uart_driver,
2081 };
2082
2083 #define IMX_CONSOLE &imx_uart_console
2084
2085 #ifdef CONFIG_OF
2086 static void imx_uart_console_early_putchar(struct uart_port *port, int ch)
2087 {
2088 struct imx_port *sport = (struct imx_port *)port;
2089
2090 while (imx_uart_readl(sport, IMX21_UTS) & UTS_TXFULL)
2091 cpu_relax();
2092
2093 imx_uart_writel(sport, ch, URTX0);
2094 }
2095
2096 static void imx_uart_console_early_write(struct console *con, const char *s,
2097 unsigned count)
2098 {
2099 struct earlycon_device *dev = con->data;
2100
2101 uart_console_write(&dev->port, s, count, imx_uart_console_early_putchar);
2102 }
2103
2104 static int __init
2105 imx_console_early_setup(struct earlycon_device *dev, const char *opt)
2106 {
2107 if (!dev->port.membase)
2108 return -ENODEV;
2109
2110 dev->con->write = imx_uart_console_early_write;
2111
2112 return 0;
2113 }
2114 OF_EARLYCON_DECLARE(ec_imx6q, "fsl,imx6q-uart", imx_console_early_setup);
2115 OF_EARLYCON_DECLARE(ec_imx21, "fsl,imx21-uart", imx_console_early_setup);
2116 #endif
2117
2118 #else
2119 #define IMX_CONSOLE NULL
2120 #endif
2121
2122 static struct uart_driver imx_uart_uart_driver = {
2123 .owner = THIS_MODULE,
2124 .driver_name = DRIVER_NAME,
2125 .dev_name = DEV_NAME,
2126 .major = SERIAL_IMX_MAJOR,
2127 .minor = MINOR_START,
2128 .nr = ARRAY_SIZE(imx_uart_ports),
2129 .cons = IMX_CONSOLE,
2130 };
2131
2132 #ifdef CONFIG_OF
2133 /*
2134 * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it
2135 * could successfully get all information from dt or a negative errno.
2136 */
2137 static int imx_uart_probe_dt(struct imx_port *sport,
2138 struct platform_device *pdev)
2139 {
2140 struct device_node *np = pdev->dev.of_node;
2141 int ret;
2142
2143 sport->devdata = of_device_get_match_data(&pdev->dev);
2144 if (!sport->devdata)
2145 /* no device tree device */
2146 return 1;
2147
2148 ret = of_alias_get_id(np, "serial");
2149 if (ret < 0) {
2150 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
2151 return ret;
2152 }
2153 sport->port.line = ret;
2154
2155 if (of_get_property(np, "uart-has-rtscts", NULL) ||
2156 of_get_property(np, "fsl,uart-has-rtscts", NULL) /* deprecated */)
2157 sport->have_rtscts = 1;
2158
2159 if (of_get_property(np, "fsl,dte-mode", NULL))
2160 sport->dte_mode = 1;
2161
2162 if (of_get_property(np, "rts-gpios", NULL))
2163 sport->have_rtsgpio = 1;
2164
2165 return 0;
2166 }
2167 #else
2168 static inline int imx_uart_probe_dt(struct imx_port *sport,
2169 struct platform_device *pdev)
2170 {
2171 return 1;
2172 }
2173 #endif
2174
2175 static void imx_uart_probe_pdata(struct imx_port *sport,
2176 struct platform_device *pdev)
2177 {
2178 struct imxuart_platform_data *pdata = dev_get_platdata(&pdev->dev);
2179
2180 sport->port.line = pdev->id;
2181 sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data;
2182
2183 if (!pdata)
2184 return;
2185
2186 if (pdata->flags & IMXUART_HAVE_RTSCTS)
2187 sport->have_rtscts = 1;
2188 }
2189
2190 static int imx_uart_probe(struct platform_device *pdev)
2191 {
2192 struct imx_port *sport;
2193 void __iomem *base;
2194 int ret = 0;
2195 u32 ucr1;
2196 struct resource *res;
2197 int txirq, rxirq, rtsirq;
2198
2199 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
2200 if (!sport)
2201 return -ENOMEM;
2202
2203 ret = imx_uart_probe_dt(sport, pdev);
2204 if (ret > 0)
2205 imx_uart_probe_pdata(sport, pdev);
2206 else if (ret < 0)
2207 return ret;
2208
2209 if (sport->port.line >= ARRAY_SIZE(imx_uart_ports)) {
2210 dev_err(&pdev->dev, "serial%d out of range\n",
2211 sport->port.line);
2212 return -EINVAL;
2213 }
2214
2215 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2216 base = devm_ioremap_resource(&pdev->dev, res);
2217 if (IS_ERR(base))
2218 return PTR_ERR(base);
2219
2220 rxirq = platform_get_irq(pdev, 0);
2221 txirq = platform_get_irq(pdev, 1);
2222 rtsirq = platform_get_irq(pdev, 2);
2223
2224 sport->port.dev = &pdev->dev;
2225 sport->port.mapbase = res->start;
2226 sport->port.membase = base;
2227 sport->port.type = PORT_IMX,
2228 sport->port.iotype = UPIO_MEM;
2229 sport->port.irq = rxirq;
2230 sport->port.fifosize = 32;
2231 sport->port.ops = &imx_uart_pops;
2232 sport->port.rs485_config = imx_uart_rs485_config;
2233 sport->port.flags = UPF_BOOT_AUTOCONF;
2234 timer_setup(&sport->timer, imx_uart_timeout, 0);
2235
2236 sport->gpios = mctrl_gpio_init(&sport->port, 0);
2237 if (IS_ERR(sport->gpios))
2238 return PTR_ERR(sport->gpios);
2239
2240 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
2241 if (IS_ERR(sport->clk_ipg)) {
2242 ret = PTR_ERR(sport->clk_ipg);
2243 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret);
2244 return ret;
2245 }
2246
2247 sport->clk_per = devm_clk_get(&pdev->dev, "per");
2248 if (IS_ERR(sport->clk_per)) {
2249 ret = PTR_ERR(sport->clk_per);
2250 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret);
2251 return ret;
2252 }
2253
2254 sport->port.uartclk = clk_get_rate(sport->clk_per);
2255
2256 /* For register access, we only need to enable the ipg clock. */
2257 ret = clk_prepare_enable(sport->clk_ipg);
2258 if (ret) {
2259 dev_err(&pdev->dev, "failed to enable per clk: %d\n", ret);
2260 return ret;
2261 }
2262
2263 /* initialize shadow register values */
2264 sport->ucr1 = readl(sport->port.membase + UCR1);
2265 sport->ucr2 = readl(sport->port.membase + UCR2);
2266 sport->ucr3 = readl(sport->port.membase + UCR3);
2267 sport->ucr4 = readl(sport->port.membase + UCR4);
2268 sport->ufcr = readl(sport->port.membase + UFCR);
2269
2270 uart_get_rs485_mode(&pdev->dev, &sport->port.rs485);
2271
2272 if (sport->port.rs485.flags & SER_RS485_ENABLED &&
2273 (!sport->have_rtscts && !sport->have_rtsgpio))
2274 dev_err(&pdev->dev, "no RTS control, disabling rs485\n");
2275
2276 /*
2277 * If using the i.MX UART RTS/CTS control then the RTS (CTS_B)
2278 * signal cannot be set low during transmission in case the
2279 * receiver is off (limitation of the i.MX UART IP).
2280 */
2281 if (sport->port.rs485.flags & SER_RS485_ENABLED &&
2282 sport->have_rtscts && !sport->have_rtsgpio &&
2283 (!(sport->port.rs485.flags & SER_RS485_RTS_ON_SEND) &&
2284 !(sport->port.rs485.flags & SER_RS485_RX_DURING_TX)))
2285 dev_err(&pdev->dev,
2286 "low-active RTS not possible when receiver is off, enabling receiver\n");
2287
2288 imx_uart_rs485_config(&sport->port, &sport->port.rs485);
2289
2290 /* Disable interrupts before requesting them */
2291 ucr1 = imx_uart_readl(sport, UCR1);
2292 ucr1 &= ~(UCR1_ADEN | UCR1_TRDYEN | UCR1_IDEN | UCR1_RRDYEN |
2293 UCR1_TXMPTYEN | UCR1_RTSDEN);
2294 imx_uart_writel(sport, ucr1, UCR1);
2295
2296 if (!imx_uart_is_imx1(sport) && sport->dte_mode) {
2297 /*
2298 * The DCEDTE bit changes the direction of DSR, DCD, DTR and RI
2299 * and influences if UCR3_RI and UCR3_DCD changes the level of RI
2300 * and DCD (when they are outputs) or enables the respective
2301 * irqs. So set this bit early, i.e. before requesting irqs.
2302 */
2303 u32 ufcr = imx_uart_readl(sport, UFCR);
2304 if (!(ufcr & UFCR_DCEDTE))
2305 imx_uart_writel(sport, ufcr | UFCR_DCEDTE, UFCR);
2306
2307 /*
2308 * Disable UCR3_RI and UCR3_DCD irqs. They are also not
2309 * enabled later because they cannot be cleared
2310 * (confirmed on i.MX25) which makes them unusable.
2311 */
2312 imx_uart_writel(sport,
2313 IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP | UCR3_DSR,
2314 UCR3);
2315
2316 } else {
2317 u32 ucr3 = UCR3_DSR;
2318 u32 ufcr = imx_uart_readl(sport, UFCR);
2319 if (ufcr & UFCR_DCEDTE)
2320 imx_uart_writel(sport, ufcr & ~UFCR_DCEDTE, UFCR);
2321
2322 if (!imx_uart_is_imx1(sport))
2323 ucr3 |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP;
2324 imx_uart_writel(sport, ucr3, UCR3);
2325 }
2326
2327 clk_disable_unprepare(sport->clk_ipg);
2328
2329 /*
2330 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
2331 * chips only have one interrupt.
2332 */
2333 if (txirq > 0) {
2334 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_rxint, 0,
2335 dev_name(&pdev->dev), sport);
2336 if (ret) {
2337 dev_err(&pdev->dev, "failed to request rx irq: %d\n",
2338 ret);
2339 return ret;
2340 }
2341
2342 ret = devm_request_irq(&pdev->dev, txirq, imx_uart_txint, 0,
2343 dev_name(&pdev->dev), sport);
2344 if (ret) {
2345 dev_err(&pdev->dev, "failed to request tx irq: %d\n",
2346 ret);
2347 return ret;
2348 }
2349
2350 ret = devm_request_irq(&pdev->dev, rtsirq, imx_uart_rtsint, 0,
2351 dev_name(&pdev->dev), sport);
2352 if (ret) {
2353 dev_err(&pdev->dev, "failed to request rts irq: %d\n",
2354 ret);
2355 return ret;
2356 }
2357 } else {
2358 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_int, 0,
2359 dev_name(&pdev->dev), sport);
2360 if (ret) {
2361 dev_err(&pdev->dev, "failed to request irq: %d\n", ret);
2362 return ret;
2363 }
2364 }
2365
2366 imx_uart_ports[sport->port.line] = sport;
2367
2368 platform_set_drvdata(pdev, sport);
2369
2370 return uart_add_one_port(&imx_uart_uart_driver, &sport->port);
2371 }
2372
2373 static int imx_uart_remove(struct platform_device *pdev)
2374 {
2375 struct imx_port *sport = platform_get_drvdata(pdev);
2376
2377 return uart_remove_one_port(&imx_uart_uart_driver, &sport->port);
2378 }
2379
2380 static void imx_uart_restore_context(struct imx_port *sport)
2381 {
2382 unsigned long flags;
2383
2384 spin_lock_irqsave(&sport->port.lock, flags);
2385 if (!sport->context_saved) {
2386 spin_unlock_irqrestore(&sport->port.lock, flags);
2387 return;
2388 }
2389
2390 imx_uart_writel(sport, sport->saved_reg[4], UFCR);
2391 imx_uart_writel(sport, sport->saved_reg[5], UESC);
2392 imx_uart_writel(sport, sport->saved_reg[6], UTIM);
2393 imx_uart_writel(sport, sport->saved_reg[7], UBIR);
2394 imx_uart_writel(sport, sport->saved_reg[8], UBMR);
2395 imx_uart_writel(sport, sport->saved_reg[9], IMX21_UTS);
2396 imx_uart_writel(sport, sport->saved_reg[0], UCR1);
2397 imx_uart_writel(sport, sport->saved_reg[1] | UCR2_SRST, UCR2);
2398 imx_uart_writel(sport, sport->saved_reg[2], UCR3);
2399 imx_uart_writel(sport, sport->saved_reg[3], UCR4);
2400 sport->context_saved = false;
2401 spin_unlock_irqrestore(&sport->port.lock, flags);
2402 }
2403
2404 static void imx_uart_save_context(struct imx_port *sport)
2405 {
2406 unsigned long flags;
2407
2408 /* Save necessary regs */
2409 spin_lock_irqsave(&sport->port.lock, flags);
2410 sport->saved_reg[0] = imx_uart_readl(sport, UCR1);
2411 sport->saved_reg[1] = imx_uart_readl(sport, UCR2);
2412 sport->saved_reg[2] = imx_uart_readl(sport, UCR3);
2413 sport->saved_reg[3] = imx_uart_readl(sport, UCR4);
2414 sport->saved_reg[4] = imx_uart_readl(sport, UFCR);
2415 sport->saved_reg[5] = imx_uart_readl(sport, UESC);
2416 sport->saved_reg[6] = imx_uart_readl(sport, UTIM);
2417 sport->saved_reg[7] = imx_uart_readl(sport, UBIR);
2418 sport->saved_reg[8] = imx_uart_readl(sport, UBMR);
2419 sport->saved_reg[9] = imx_uart_readl(sport, IMX21_UTS);
2420 sport->context_saved = true;
2421 spin_unlock_irqrestore(&sport->port.lock, flags);
2422 }
2423
2424 static void imx_uart_enable_wakeup(struct imx_port *sport, bool on)
2425 {
2426 u32 ucr3;
2427
2428 ucr3 = imx_uart_readl(sport, UCR3);
2429 if (on) {
2430 imx_uart_writel(sport, USR1_AWAKE, USR1);
2431 ucr3 |= UCR3_AWAKEN;
2432 } else {
2433 ucr3 &= ~UCR3_AWAKEN;
2434 }
2435 imx_uart_writel(sport, ucr3, UCR3);
2436
2437 if (sport->have_rtscts) {
2438 u32 ucr1 = imx_uart_readl(sport, UCR1);
2439 if (on)
2440 ucr1 |= UCR1_RTSDEN;
2441 else
2442 ucr1 &= ~UCR1_RTSDEN;
2443 imx_uart_writel(sport, ucr1, UCR1);
2444 }
2445 }
2446
2447 static int imx_uart_suspend_noirq(struct device *dev)
2448 {
2449 struct imx_port *sport = dev_get_drvdata(dev);
2450
2451 imx_uart_save_context(sport);
2452
2453 clk_disable(sport->clk_ipg);
2454
2455 pinctrl_pm_select_sleep_state(dev);
2456
2457 return 0;
2458 }
2459
2460 static int imx_uart_resume_noirq(struct device *dev)
2461 {
2462 struct imx_port *sport = dev_get_drvdata(dev);
2463 int ret;
2464
2465 pinctrl_pm_select_default_state(dev);
2466
2467 ret = clk_enable(sport->clk_ipg);
2468 if (ret)
2469 return ret;
2470
2471 imx_uart_restore_context(sport);
2472
2473 return 0;
2474 }
2475
2476 static int imx_uart_suspend(struct device *dev)
2477 {
2478 struct imx_port *sport = dev_get_drvdata(dev);
2479 int ret;
2480
2481 uart_suspend_port(&imx_uart_uart_driver, &sport->port);
2482 disable_irq(sport->port.irq);
2483
2484 ret = clk_prepare_enable(sport->clk_ipg);
2485 if (ret)
2486 return ret;
2487
2488 /* enable wakeup from i.MX UART */
2489 imx_uart_enable_wakeup(sport, true);
2490
2491 return 0;
2492 }
2493
2494 static int imx_uart_resume(struct device *dev)
2495 {
2496 struct imx_port *sport = dev_get_drvdata(dev);
2497
2498 /* disable wakeup from i.MX UART */
2499 imx_uart_enable_wakeup(sport, false);
2500
2501 uart_resume_port(&imx_uart_uart_driver, &sport->port);
2502 enable_irq(sport->port.irq);
2503
2504 clk_disable_unprepare(sport->clk_ipg);
2505
2506 return 0;
2507 }
2508
2509 static int imx_uart_freeze(struct device *dev)
2510 {
2511 struct imx_port *sport = dev_get_drvdata(dev);
2512
2513 uart_suspend_port(&imx_uart_uart_driver, &sport->port);
2514
2515 return clk_prepare_enable(sport->clk_ipg);
2516 }
2517
2518 static int imx_uart_thaw(struct device *dev)
2519 {
2520 struct imx_port *sport = dev_get_drvdata(dev);
2521
2522 uart_resume_port(&imx_uart_uart_driver, &sport->port);
2523
2524 clk_disable_unprepare(sport->clk_ipg);
2525
2526 return 0;
2527 }
2528
2529 static const struct dev_pm_ops imx_uart_pm_ops = {
2530 .suspend_noirq = imx_uart_suspend_noirq,
2531 .resume_noirq = imx_uart_resume_noirq,
2532 .freeze_noirq = imx_uart_suspend_noirq,
2533 .restore_noirq = imx_uart_resume_noirq,
2534 .suspend = imx_uart_suspend,
2535 .resume = imx_uart_resume,
2536 .freeze = imx_uart_freeze,
2537 .thaw = imx_uart_thaw,
2538 .restore = imx_uart_thaw,
2539 };
2540
2541 static struct platform_driver imx_uart_platform_driver = {
2542 .probe = imx_uart_probe,
2543 .remove = imx_uart_remove,
2544
2545 .id_table = imx_uart_devtype,
2546 .driver = {
2547 .name = "imx-uart",
2548 .of_match_table = imx_uart_dt_ids,
2549 .pm = &imx_uart_pm_ops,
2550 },
2551 };
2552
2553 static int __init imx_uart_init(void)
2554 {
2555 int ret = uart_register_driver(&imx_uart_uart_driver);
2556
2557 if (ret)
2558 return ret;
2559
2560 ret = platform_driver_register(&imx_uart_platform_driver);
2561 if (ret != 0)
2562 uart_unregister_driver(&imx_uart_uart_driver);
2563
2564 return ret;
2565 }
2566
2567 static void __exit imx_uart_exit(void)
2568 {
2569 platform_driver_unregister(&imx_uart_platform_driver);
2570 uart_unregister_driver(&imx_uart_uart_driver);
2571 }
2572
2573 module_init(imx_uart_init);
2574 module_exit(imx_uart_exit);
2575
2576 MODULE_AUTHOR("Sascha Hauer");
2577 MODULE_DESCRIPTION("IMX generic serial port driver");
2578 MODULE_LICENSE("GPL");
2579 MODULE_ALIAS("platform:imx-uart");
Linux with added FPC-III support