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staging: erofs: integrate decompression inplace
[linux/fpc-iii.git] / drivers / tty / serial / msm_serial.c
blob23833ad952ba3aa7ad64d1314618536790f8af19
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Driver for msm7k serial device and console
4 *
5 * Copyright (C) 2007 Google, Inc.
6 * Author: Robert Love <rlove@google.com>
7 * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
8 */
9
10 #if defined(CONFIG_SERIAL_MSM_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
11 # define SUPPORT_SYSRQ
12 #endif
13
14 #include <linux/kernel.h>
15 #include <linux/atomic.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/dmaengine.h>
18 #include <linux/module.h>
19 #include <linux/io.h>
20 #include <linux/ioport.h>
21 #include <linux/interrupt.h>
22 #include <linux/init.h>
23 #include <linux/console.h>
24 #include <linux/tty.h>
25 #include <linux/tty_flip.h>
26 #include <linux/serial_core.h>
27 #include <linux/slab.h>
28 #include <linux/clk.h>
29 #include <linux/platform_device.h>
30 #include <linux/delay.h>
31 #include <linux/of.h>
32 #include <linux/of_device.h>
33 #include <linux/wait.h>
34
35 #define UART_MR1 0x0000
36
37 #define UART_MR1_AUTO_RFR_LEVEL0 0x3F
38 #define UART_MR1_AUTO_RFR_LEVEL1 0x3FF00
39 #define UART_DM_MR1_AUTO_RFR_LEVEL1 0xFFFFFF00
40 #define UART_MR1_RX_RDY_CTL BIT(7)
41 #define UART_MR1_CTS_CTL BIT(6)
42
43 #define UART_MR2 0x0004
44 #define UART_MR2_ERROR_MODE BIT(6)
45 #define UART_MR2_BITS_PER_CHAR 0x30
46 #define UART_MR2_BITS_PER_CHAR_5 (0x0 << 4)
47 #define UART_MR2_BITS_PER_CHAR_6 (0x1 << 4)
48 #define UART_MR2_BITS_PER_CHAR_7 (0x2 << 4)
49 #define UART_MR2_BITS_PER_CHAR_8 (0x3 << 4)
50 #define UART_MR2_STOP_BIT_LEN_ONE (0x1 << 2)
51 #define UART_MR2_STOP_BIT_LEN_TWO (0x3 << 2)
52 #define UART_MR2_PARITY_MODE_NONE 0x0
53 #define UART_MR2_PARITY_MODE_ODD 0x1
54 #define UART_MR2_PARITY_MODE_EVEN 0x2
55 #define UART_MR2_PARITY_MODE_SPACE 0x3
56 #define UART_MR2_PARITY_MODE 0x3
57
58 #define UART_CSR 0x0008
59
60 #define UART_TF 0x000C
61 #define UARTDM_TF 0x0070
62
63 #define UART_CR 0x0010
64 #define UART_CR_CMD_NULL (0 << 4)
65 #define UART_CR_CMD_RESET_RX (1 << 4)
66 #define UART_CR_CMD_RESET_TX (2 << 4)
67 #define UART_CR_CMD_RESET_ERR (3 << 4)
68 #define UART_CR_CMD_RESET_BREAK_INT (4 << 4)
69 #define UART_CR_CMD_START_BREAK (5 << 4)
70 #define UART_CR_CMD_STOP_BREAK (6 << 4)
71 #define UART_CR_CMD_RESET_CTS (7 << 4)
72 #define UART_CR_CMD_RESET_STALE_INT (8 << 4)
73 #define UART_CR_CMD_PACKET_MODE (9 << 4)
74 #define UART_CR_CMD_MODE_RESET (12 << 4)
75 #define UART_CR_CMD_SET_RFR (13 << 4)
76 #define UART_CR_CMD_RESET_RFR (14 << 4)
77 #define UART_CR_CMD_PROTECTION_EN (16 << 4)
78 #define UART_CR_CMD_STALE_EVENT_DISABLE (6 << 8)
79 #define UART_CR_CMD_STALE_EVENT_ENABLE (80 << 4)
80 #define UART_CR_CMD_FORCE_STALE (4 << 8)
81 #define UART_CR_CMD_RESET_TX_READY (3 << 8)
82 #define UART_CR_TX_DISABLE BIT(3)
83 #define UART_CR_TX_ENABLE BIT(2)
84 #define UART_CR_RX_DISABLE BIT(1)
85 #define UART_CR_RX_ENABLE BIT(0)
86 #define UART_CR_CMD_RESET_RXBREAK_START ((1 << 11) | (2 << 4))
87
88 #define UART_IMR 0x0014
89 #define UART_IMR_TXLEV BIT(0)
90 #define UART_IMR_RXSTALE BIT(3)
91 #define UART_IMR_RXLEV BIT(4)
92 #define UART_IMR_DELTA_CTS BIT(5)
93 #define UART_IMR_CURRENT_CTS BIT(6)
94 #define UART_IMR_RXBREAK_START BIT(10)
95
96 #define UART_IPR_RXSTALE_LAST 0x20
97 #define UART_IPR_STALE_LSB 0x1F
98 #define UART_IPR_STALE_TIMEOUT_MSB 0x3FF80
99 #define UART_DM_IPR_STALE_TIMEOUT_MSB 0xFFFFFF80
100
101 #define UART_IPR 0x0018
102 #define UART_TFWR 0x001C
103 #define UART_RFWR 0x0020
104 #define UART_HCR 0x0024
105
106 #define UART_MREG 0x0028
107 #define UART_NREG 0x002C
108 #define UART_DREG 0x0030
109 #define UART_MNDREG 0x0034
110 #define UART_IRDA 0x0038
111 #define UART_MISR_MODE 0x0040
112 #define UART_MISR_RESET 0x0044
113 #define UART_MISR_EXPORT 0x0048
114 #define UART_MISR_VAL 0x004C
115 #define UART_TEST_CTRL 0x0050
116
117 #define UART_SR 0x0008
118 #define UART_SR_HUNT_CHAR BIT(7)
119 #define UART_SR_RX_BREAK BIT(6)
120 #define UART_SR_PAR_FRAME_ERR BIT(5)
121 #define UART_SR_OVERRUN BIT(4)
122 #define UART_SR_TX_EMPTY BIT(3)
123 #define UART_SR_TX_READY BIT(2)
124 #define UART_SR_RX_FULL BIT(1)
125 #define UART_SR_RX_READY BIT(0)
126
127 #define UART_RF 0x000C
128 #define UARTDM_RF 0x0070
129 #define UART_MISR 0x0010
130 #define UART_ISR 0x0014
131 #define UART_ISR_TX_READY BIT(7)
132
133 #define UARTDM_RXFS 0x50
134 #define UARTDM_RXFS_BUF_SHIFT 0x7
135 #define UARTDM_RXFS_BUF_MASK 0x7
136
137 #define UARTDM_DMEN 0x3C
138 #define UARTDM_DMEN_RX_SC_ENABLE BIT(5)
139 #define UARTDM_DMEN_TX_SC_ENABLE BIT(4)
140
141 #define UARTDM_DMEN_TX_BAM_ENABLE BIT(2) /* UARTDM_1P4 */
142 #define UARTDM_DMEN_TX_DM_ENABLE BIT(0) /* < UARTDM_1P4 */
143
144 #define UARTDM_DMEN_RX_BAM_ENABLE BIT(3) /* UARTDM_1P4 */
145 #define UARTDM_DMEN_RX_DM_ENABLE BIT(1) /* < UARTDM_1P4 */
146
147 #define UARTDM_DMRX 0x34
148 #define UARTDM_NCF_TX 0x40
149 #define UARTDM_RX_TOTAL_SNAP 0x38
150
151 #define UARTDM_BURST_SIZE 16 /* in bytes */
152 #define UARTDM_TX_AIGN(x) ((x) & ~0x3) /* valid for > 1p3 */
153 #define UARTDM_TX_MAX 256 /* in bytes, valid for <= 1p3 */
154 #define UARTDM_RX_SIZE (UART_XMIT_SIZE / 4)
155
156 enum {
157 UARTDM_1P1 = 1,
158 UARTDM_1P2,
159 UARTDM_1P3,
160 UARTDM_1P4,
161 };
162
163 struct msm_dma {
164 struct dma_chan *chan;
165 enum dma_data_direction dir;
166 dma_addr_t phys;
167 unsigned char *virt;
168 dma_cookie_t cookie;
169 u32 enable_bit;
170 unsigned int count;
171 struct dma_async_tx_descriptor *desc;
172 };
173
174 struct msm_port {
175 struct uart_port uart;
176 char name[16];
177 struct clk *clk;
178 struct clk *pclk;
179 unsigned int imr;
180 int is_uartdm;
181 unsigned int old_snap_state;
182 bool break_detected;
183 struct msm_dma tx_dma;
184 struct msm_dma rx_dma;
185 };
186
187 #define UART_TO_MSM(uart_port) container_of(uart_port, struct msm_port, uart)
188
189 static
190 void msm_write(struct uart_port *port, unsigned int val, unsigned int off)
191 {
192 writel_relaxed(val, port->membase + off);
193 }
194
195 static
196 unsigned int msm_read(struct uart_port *port, unsigned int off)
197 {
198 return readl_relaxed(port->membase + off);
199 }
200
201 /*
202 * Setup the MND registers to use the TCXO clock.
203 */
204 static void msm_serial_set_mnd_regs_tcxo(struct uart_port *port)
205 {
206 msm_write(port, 0x06, UART_MREG);
207 msm_write(port, 0xF1, UART_NREG);
208 msm_write(port, 0x0F, UART_DREG);
209 msm_write(port, 0x1A, UART_MNDREG);
210 port->uartclk = 1843200;
211 }
212
213 /*
214 * Setup the MND registers to use the TCXO clock divided by 4.
215 */
216 static void msm_serial_set_mnd_regs_tcxoby4(struct uart_port *port)
217 {
218 msm_write(port, 0x18, UART_MREG);
219 msm_write(port, 0xF6, UART_NREG);
220 msm_write(port, 0x0F, UART_DREG);
221 msm_write(port, 0x0A, UART_MNDREG);
222 port->uartclk = 1843200;
223 }
224
225 static void msm_serial_set_mnd_regs(struct uart_port *port)
226 {
227 struct msm_port *msm_port = UART_TO_MSM(port);
228
229 /*
230 * These registers don't exist so we change the clk input rate
231 * on uartdm hardware instead
232 */
233 if (msm_port->is_uartdm)
234 return;
235
236 if (port->uartclk == 19200000)
237 msm_serial_set_mnd_regs_tcxo(port);
238 else if (port->uartclk == 4800000)
239 msm_serial_set_mnd_regs_tcxoby4(port);
240 }
241
242 static void msm_handle_tx(struct uart_port *port);
243 static void msm_start_rx_dma(struct msm_port *msm_port);
244
245 static void msm_stop_dma(struct uart_port *port, struct msm_dma *dma)
246 {
247 struct device *dev = port->dev;
248 unsigned int mapped;
249 u32 val;
250
251 mapped = dma->count;
252 dma->count = 0;
253
254 dmaengine_terminate_all(dma->chan);
255
256 /*
257 * DMA Stall happens if enqueue and flush command happens concurrently.
258 * For example before changing the baud rate/protocol configuration and
259 * sending flush command to ADM, disable the channel of UARTDM.
260 * Note: should not reset the receiver here immediately as it is not
261 * suggested to do disable/reset or reset/disable at the same time.
262 */
263 val = msm_read(port, UARTDM_DMEN);
264 val &= ~dma->enable_bit;
265 msm_write(port, val, UARTDM_DMEN);
266
267 if (mapped)
268 dma_unmap_single(dev, dma->phys, mapped, dma->dir);
269 }
270
271 static void msm_release_dma(struct msm_port *msm_port)
272 {
273 struct msm_dma *dma;
274
275 dma = &msm_port->tx_dma;
276 if (dma->chan) {
277 msm_stop_dma(&msm_port->uart, dma);
278 dma_release_channel(dma->chan);
279 }
280
281 memset(dma, 0, sizeof(*dma));
282
283 dma = &msm_port->rx_dma;
284 if (dma->chan) {
285 msm_stop_dma(&msm_port->uart, dma);
286 dma_release_channel(dma->chan);
287 kfree(dma->virt);
288 }
289
290 memset(dma, 0, sizeof(*dma));
291 }
292
293 static void msm_request_tx_dma(struct msm_port *msm_port, resource_size_t base)
294 {
295 struct device *dev = msm_port->uart.dev;
296 struct dma_slave_config conf;
297 struct msm_dma *dma;
298 u32 crci = 0;
299 int ret;
300
301 dma = &msm_port->tx_dma;
302
303 /* allocate DMA resources, if available */
304 dma->chan = dma_request_slave_channel_reason(dev, "tx");
305 if (IS_ERR(dma->chan))
306 goto no_tx;
307
308 of_property_read_u32(dev->of_node, "qcom,tx-crci", &crci);
309
310 memset(&conf, 0, sizeof(conf));
311 conf.direction = DMA_MEM_TO_DEV;
312 conf.device_fc = true;
313 conf.dst_addr = base + UARTDM_TF;
314 conf.dst_maxburst = UARTDM_BURST_SIZE;
315 conf.slave_id = crci;
316
317 ret = dmaengine_slave_config(dma->chan, &conf);
318 if (ret)
319 goto rel_tx;
320
321 dma->dir = DMA_TO_DEVICE;
322
323 if (msm_port->is_uartdm < UARTDM_1P4)
324 dma->enable_bit = UARTDM_DMEN_TX_DM_ENABLE;
325 else
326 dma->enable_bit = UARTDM_DMEN_TX_BAM_ENABLE;
327
328 return;
329
330 rel_tx:
331 dma_release_channel(dma->chan);
332 no_tx:
333 memset(dma, 0, sizeof(*dma));
334 }
335
336 static void msm_request_rx_dma(struct msm_port *msm_port, resource_size_t base)
337 {
338 struct device *dev = msm_port->uart.dev;
339 struct dma_slave_config conf;
340 struct msm_dma *dma;
341 u32 crci = 0;
342 int ret;
343
344 dma = &msm_port->rx_dma;
345
346 /* allocate DMA resources, if available */
347 dma->chan = dma_request_slave_channel_reason(dev, "rx");
348 if (IS_ERR(dma->chan))
349 goto no_rx;
350
351 of_property_read_u32(dev->of_node, "qcom,rx-crci", &crci);
352
353 dma->virt = kzalloc(UARTDM_RX_SIZE, GFP_KERNEL);
354 if (!dma->virt)
355 goto rel_rx;
356
357 memset(&conf, 0, sizeof(conf));
358 conf.direction = DMA_DEV_TO_MEM;
359 conf.device_fc = true;
360 conf.src_addr = base + UARTDM_RF;
361 conf.src_maxburst = UARTDM_BURST_SIZE;
362 conf.slave_id = crci;
363
364 ret = dmaengine_slave_config(dma->chan, &conf);
365 if (ret)
366 goto err;
367
368 dma->dir = DMA_FROM_DEVICE;
369
370 if (msm_port->is_uartdm < UARTDM_1P4)
371 dma->enable_bit = UARTDM_DMEN_RX_DM_ENABLE;
372 else
373 dma->enable_bit = UARTDM_DMEN_RX_BAM_ENABLE;
374
375 return;
376 err:
377 kfree(dma->virt);
378 rel_rx:
379 dma_release_channel(dma->chan);
380 no_rx:
381 memset(dma, 0, sizeof(*dma));
382 }
383
384 static inline void msm_wait_for_xmitr(struct uart_port *port)
385 {
386 while (!(msm_read(port, UART_SR) & UART_SR_TX_EMPTY)) {
387 if (msm_read(port, UART_ISR) & UART_ISR_TX_READY)
388 break;
389 udelay(1);
390 }
391 msm_write(port, UART_CR_CMD_RESET_TX_READY, UART_CR);
392 }
393
394 static void msm_stop_tx(struct uart_port *port)
395 {
396 struct msm_port *msm_port = UART_TO_MSM(port);
397
398 msm_port->imr &= ~UART_IMR_TXLEV;
399 msm_write(port, msm_port->imr, UART_IMR);
400 }
401
402 static void msm_start_tx(struct uart_port *port)
403 {
404 struct msm_port *msm_port = UART_TO_MSM(port);
405 struct msm_dma *dma = &msm_port->tx_dma;
406
407 /* Already started in DMA mode */
408 if (dma->count)
409 return;
410
411 msm_port->imr |= UART_IMR_TXLEV;
412 msm_write(port, msm_port->imr, UART_IMR);
413 }
414
415 static void msm_reset_dm_count(struct uart_port *port, int count)
416 {
417 msm_wait_for_xmitr(port);
418 msm_write(port, count, UARTDM_NCF_TX);
419 msm_read(port, UARTDM_NCF_TX);
420 }
421
422 static void msm_complete_tx_dma(void *args)
423 {
424 struct msm_port *msm_port = args;
425 struct uart_port *port = &msm_port->uart;
426 struct circ_buf *xmit = &port->state->xmit;
427 struct msm_dma *dma = &msm_port->tx_dma;
428 struct dma_tx_state state;
429 enum dma_status status;
430 unsigned long flags;
431 unsigned int count;
432 u32 val;
433
434 spin_lock_irqsave(&port->lock, flags);
435
436 /* Already stopped */
437 if (!dma->count)
438 goto done;
439
440 status = dmaengine_tx_status(dma->chan, dma->cookie, &state);
441
442 dma_unmap_single(port->dev, dma->phys, dma->count, dma->dir);
443
444 val = msm_read(port, UARTDM_DMEN);
445 val &= ~dma->enable_bit;
446 msm_write(port, val, UARTDM_DMEN);
447
448 if (msm_port->is_uartdm > UARTDM_1P3) {
449 msm_write(port, UART_CR_CMD_RESET_TX, UART_CR);
450 msm_write(port, UART_CR_TX_ENABLE, UART_CR);
451 }
452
453 count = dma->count - state.residue;
454 port->icount.tx += count;
455 dma->count = 0;
456
457 xmit->tail += count;
458 xmit->tail &= UART_XMIT_SIZE - 1;
459
460 /* Restore "Tx FIFO below watermark" interrupt */
461 msm_port->imr |= UART_IMR_TXLEV;
462 msm_write(port, msm_port->imr, UART_IMR);
463
464 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
465 uart_write_wakeup(port);
466
467 msm_handle_tx(port);
468 done:
469 spin_unlock_irqrestore(&port->lock, flags);
470 }
471
472 static int msm_handle_tx_dma(struct msm_port *msm_port, unsigned int count)
473 {
474 struct circ_buf *xmit = &msm_port->uart.state->xmit;
475 struct uart_port *port = &msm_port->uart;
476 struct msm_dma *dma = &msm_port->tx_dma;
477 void *cpu_addr;
478 int ret;
479 u32 val;
480
481 cpu_addr = &xmit->buf[xmit->tail];
482
483 dma->phys = dma_map_single(port->dev, cpu_addr, count, dma->dir);
484 ret = dma_mapping_error(port->dev, dma->phys);
485 if (ret)
486 return ret;
487
488 dma->desc = dmaengine_prep_slave_single(dma->chan, dma->phys,
489 count, DMA_MEM_TO_DEV,
490 DMA_PREP_INTERRUPT |
491 DMA_PREP_FENCE);
492 if (!dma->desc) {
493 ret = -EIO;
494 goto unmap;
495 }
496
497 dma->desc->callback = msm_complete_tx_dma;
498 dma->desc->callback_param = msm_port;
499
500 dma->cookie = dmaengine_submit(dma->desc);
501 ret = dma_submit_error(dma->cookie);
502 if (ret)
503 goto unmap;
504
505 /*
506 * Using DMA complete for Tx FIFO reload, no need for
507 * "Tx FIFO below watermark" one, disable it
508 */
509 msm_port->imr &= ~UART_IMR_TXLEV;
510 msm_write(port, msm_port->imr, UART_IMR);
511
512 dma->count = count;
513
514 val = msm_read(port, UARTDM_DMEN);
515 val |= dma->enable_bit;
516
517 if (msm_port->is_uartdm < UARTDM_1P4)
518 msm_write(port, val, UARTDM_DMEN);
519
520 msm_reset_dm_count(port, count);
521
522 if (msm_port->is_uartdm > UARTDM_1P3)
523 msm_write(port, val, UARTDM_DMEN);
524
525 dma_async_issue_pending(dma->chan);
526 return 0;
527 unmap:
528 dma_unmap_single(port->dev, dma->phys, count, dma->dir);
529 return ret;
530 }
531
532 static void msm_complete_rx_dma(void *args)
533 {
534 struct msm_port *msm_port = args;
535 struct uart_port *port = &msm_port->uart;
536 struct tty_port *tport = &port->state->port;
537 struct msm_dma *dma = &msm_port->rx_dma;
538 int count = 0, i, sysrq;
539 unsigned long flags;
540 u32 val;
541
542 spin_lock_irqsave(&port->lock, flags);
543
544 /* Already stopped */
545 if (!dma->count)
546 goto done;
547
548 val = msm_read(port, UARTDM_DMEN);
549 val &= ~dma->enable_bit;
550 msm_write(port, val, UARTDM_DMEN);
551
552 if (msm_read(port, UART_SR) & UART_SR_OVERRUN) {
553 port->icount.overrun++;
554 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
555 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
556 }
557
558 count = msm_read(port, UARTDM_RX_TOTAL_SNAP);
559
560 port->icount.rx += count;
561
562 dma->count = 0;
563
564 dma_unmap_single(port->dev, dma->phys, UARTDM_RX_SIZE, dma->dir);
565
566 for (i = 0; i < count; i++) {
567 char flag = TTY_NORMAL;
568
569 if (msm_port->break_detected && dma->virt[i] == 0) {
570 port->icount.brk++;
571 flag = TTY_BREAK;
572 msm_port->break_detected = false;
573 if (uart_handle_break(port))
574 continue;
575 }
576
577 if (!(port->read_status_mask & UART_SR_RX_BREAK))
578 flag = TTY_NORMAL;
579
580 spin_unlock_irqrestore(&port->lock, flags);
581 sysrq = uart_handle_sysrq_char(port, dma->virt[i]);
582 spin_lock_irqsave(&port->lock, flags);
583 if (!sysrq)
584 tty_insert_flip_char(tport, dma->virt[i], flag);
585 }
586
587 msm_start_rx_dma(msm_port);
588 done:
589 spin_unlock_irqrestore(&port->lock, flags);
590
591 if (count)
592 tty_flip_buffer_push(tport);
593 }
594
595 static void msm_start_rx_dma(struct msm_port *msm_port)
596 {
597 struct msm_dma *dma = &msm_port->rx_dma;
598 struct uart_port *uart = &msm_port->uart;
599 u32 val;
600 int ret;
601
602 if (!dma->chan)
603 return;
604
605 dma->phys = dma_map_single(uart->dev, dma->virt,
606 UARTDM_RX_SIZE, dma->dir);
607 ret = dma_mapping_error(uart->dev, dma->phys);
608 if (ret)
609 return;
610
611 dma->desc = dmaengine_prep_slave_single(dma->chan, dma->phys,
612 UARTDM_RX_SIZE, DMA_DEV_TO_MEM,
613 DMA_PREP_INTERRUPT);
614 if (!dma->desc)
615 goto unmap;
616
617 dma->desc->callback = msm_complete_rx_dma;
618 dma->desc->callback_param = msm_port;
619
620 dma->cookie = dmaengine_submit(dma->desc);
621 ret = dma_submit_error(dma->cookie);
622 if (ret)
623 goto unmap;
624 /*
625 * Using DMA for FIFO off-load, no need for "Rx FIFO over
626 * watermark" or "stale" interrupts, disable them
627 */
628 msm_port->imr &= ~(UART_IMR_RXLEV | UART_IMR_RXSTALE);
629
630 /*
631 * Well, when DMA is ADM3 engine(implied by <= UARTDM v1.3),
632 * we need RXSTALE to flush input DMA fifo to memory
633 */
634 if (msm_port->is_uartdm < UARTDM_1P4)
635 msm_port->imr |= UART_IMR_RXSTALE;
636
637 msm_write(uart, msm_port->imr, UART_IMR);
638
639 dma->count = UARTDM_RX_SIZE;
640
641 dma_async_issue_pending(dma->chan);
642
643 msm_write(uart, UART_CR_CMD_RESET_STALE_INT, UART_CR);
644 msm_write(uart, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
645
646 val = msm_read(uart, UARTDM_DMEN);
647 val |= dma->enable_bit;
648
649 if (msm_port->is_uartdm < UARTDM_1P4)
650 msm_write(uart, val, UARTDM_DMEN);
651
652 msm_write(uart, UARTDM_RX_SIZE, UARTDM_DMRX);
653
654 if (msm_port->is_uartdm > UARTDM_1P3)
655 msm_write(uart, val, UARTDM_DMEN);
656
657 return;
658 unmap:
659 dma_unmap_single(uart->dev, dma->phys, UARTDM_RX_SIZE, dma->dir);
660 }
661
662 static void msm_stop_rx(struct uart_port *port)
663 {
664 struct msm_port *msm_port = UART_TO_MSM(port);
665 struct msm_dma *dma = &msm_port->rx_dma;
666
667 msm_port->imr &= ~(UART_IMR_RXLEV | UART_IMR_RXSTALE);
668 msm_write(port, msm_port->imr, UART_IMR);
669
670 if (dma->chan)
671 msm_stop_dma(port, dma);
672 }
673
674 static void msm_enable_ms(struct uart_port *port)
675 {
676 struct msm_port *msm_port = UART_TO_MSM(port);
677
678 msm_port->imr |= UART_IMR_DELTA_CTS;
679 msm_write(port, msm_port->imr, UART_IMR);
680 }
681
682 static void msm_handle_rx_dm(struct uart_port *port, unsigned int misr)
683 {
684 struct tty_port *tport = &port->state->port;
685 unsigned int sr;
686 int count = 0;
687 struct msm_port *msm_port = UART_TO_MSM(port);
688
689 if ((msm_read(port, UART_SR) & UART_SR_OVERRUN)) {
690 port->icount.overrun++;
691 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
692 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
693 }
694
695 if (misr & UART_IMR_RXSTALE) {
696 count = msm_read(port, UARTDM_RX_TOTAL_SNAP) -
697 msm_port->old_snap_state;
698 msm_port->old_snap_state = 0;
699 } else {
700 count = 4 * (msm_read(port, UART_RFWR));
701 msm_port->old_snap_state += count;
702 }
703
704 /* TODO: Precise error reporting */
705
706 port->icount.rx += count;
707
708 while (count > 0) {
709 unsigned char buf[4];
710 int sysrq, r_count, i;
711
712 sr = msm_read(port, UART_SR);
713 if ((sr & UART_SR_RX_READY) == 0) {
714 msm_port->old_snap_state -= count;
715 break;
716 }
717
718 ioread32_rep(port->membase + UARTDM_RF, buf, 1);
719 r_count = min_t(int, count, sizeof(buf));
720
721 for (i = 0; i < r_count; i++) {
722 char flag = TTY_NORMAL;
723
724 if (msm_port->break_detected && buf[i] == 0) {
725 port->icount.brk++;
726 flag = TTY_BREAK;
727 msm_port->break_detected = false;
728 if (uart_handle_break(port))
729 continue;
730 }
731
732 if (!(port->read_status_mask & UART_SR_RX_BREAK))
733 flag = TTY_NORMAL;
734
735 spin_unlock(&port->lock);
736 sysrq = uart_handle_sysrq_char(port, buf[i]);
737 spin_lock(&port->lock);
738 if (!sysrq)
739 tty_insert_flip_char(tport, buf[i], flag);
740 }
741 count -= r_count;
742 }
743
744 spin_unlock(&port->lock);
745 tty_flip_buffer_push(tport);
746 spin_lock(&port->lock);
747
748 if (misr & (UART_IMR_RXSTALE))
749 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
750 msm_write(port, 0xFFFFFF, UARTDM_DMRX);
751 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
752
753 /* Try to use DMA */
754 msm_start_rx_dma(msm_port);
755 }
756
757 static void msm_handle_rx(struct uart_port *port)
758 {
759 struct tty_port *tport = &port->state->port;
760 unsigned int sr;
761
762 /*
763 * Handle overrun. My understanding of the hardware is that overrun
764 * is not tied to the RX buffer, so we handle the case out of band.
765 */
766 if ((msm_read(port, UART_SR) & UART_SR_OVERRUN)) {
767 port->icount.overrun++;
768 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
769 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
770 }
771
772 /* and now the main RX loop */
773 while ((sr = msm_read(port, UART_SR)) & UART_SR_RX_READY) {
774 unsigned int c;
775 char flag = TTY_NORMAL;
776 int sysrq;
777
778 c = msm_read(port, UART_RF);
779
780 if (sr & UART_SR_RX_BREAK) {
781 port->icount.brk++;
782 if (uart_handle_break(port))
783 continue;
784 } else if (sr & UART_SR_PAR_FRAME_ERR) {
785 port->icount.frame++;
786 } else {
787 port->icount.rx++;
788 }
789
790 /* Mask conditions we're ignorning. */
791 sr &= port->read_status_mask;
792
793 if (sr & UART_SR_RX_BREAK)
794 flag = TTY_BREAK;
795 else if (sr & UART_SR_PAR_FRAME_ERR)
796 flag = TTY_FRAME;
797
798 spin_unlock(&port->lock);
799 sysrq = uart_handle_sysrq_char(port, c);
800 spin_lock(&port->lock);
801 if (!sysrq)
802 tty_insert_flip_char(tport, c, flag);
803 }
804
805 spin_unlock(&port->lock);
806 tty_flip_buffer_push(tport);
807 spin_lock(&port->lock);
808 }
809
810 static void msm_handle_tx_pio(struct uart_port *port, unsigned int tx_count)
811 {
812 struct circ_buf *xmit = &port->state->xmit;
813 struct msm_port *msm_port = UART_TO_MSM(port);
814 unsigned int num_chars;
815 unsigned int tf_pointer = 0;
816 void __iomem *tf;
817
818 if (msm_port->is_uartdm)
819 tf = port->membase + UARTDM_TF;
820 else
821 tf = port->membase + UART_TF;
822
823 if (tx_count && msm_port->is_uartdm)
824 msm_reset_dm_count(port, tx_count);
825
826 while (tf_pointer < tx_count) {
827 int i;
828 char buf[4] = { 0 };
829
830 if (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
831 break;
832
833 if (msm_port->is_uartdm)
834 num_chars = min(tx_count - tf_pointer,
835 (unsigned int)sizeof(buf));
836 else
837 num_chars = 1;
838
839 for (i = 0; i < num_chars; i++) {
840 buf[i] = xmit->buf[xmit->tail + i];
841 port->icount.tx++;
842 }
843
844 iowrite32_rep(tf, buf, 1);
845 xmit->tail = (xmit->tail + num_chars) & (UART_XMIT_SIZE - 1);
846 tf_pointer += num_chars;
847 }
848
849 /* disable tx interrupts if nothing more to send */
850 if (uart_circ_empty(xmit))
851 msm_stop_tx(port);
852
853 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
854 uart_write_wakeup(port);
855 }
856
857 static void msm_handle_tx(struct uart_port *port)
858 {
859 struct msm_port *msm_port = UART_TO_MSM(port);
860 struct circ_buf *xmit = &msm_port->uart.state->xmit;
861 struct msm_dma *dma = &msm_port->tx_dma;
862 unsigned int pio_count, dma_count, dma_min;
863 char buf[4] = { 0 };
864 void __iomem *tf;
865 int err = 0;
866
867 if (port->x_char) {
868 if (msm_port->is_uartdm)
869 tf = port->membase + UARTDM_TF;
870 else
871 tf = port->membase + UART_TF;
872
873 buf[0] = port->x_char;
874
875 if (msm_port->is_uartdm)
876 msm_reset_dm_count(port, 1);
877
878 iowrite32_rep(tf, buf, 1);
879 port->icount.tx++;
880 port->x_char = 0;
881 return;
882 }
883
884 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
885 msm_stop_tx(port);
886 return;
887 }
888
889 pio_count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
890 dma_count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
891
892 dma_min = 1; /* Always DMA */
893 if (msm_port->is_uartdm > UARTDM_1P3) {
894 dma_count = UARTDM_TX_AIGN(dma_count);
895 dma_min = UARTDM_BURST_SIZE;
896 } else {
897 if (dma_count > UARTDM_TX_MAX)
898 dma_count = UARTDM_TX_MAX;
899 }
900
901 if (pio_count > port->fifosize)
902 pio_count = port->fifosize;
903
904 if (!dma->chan || dma_count < dma_min)
905 msm_handle_tx_pio(port, pio_count);
906 else
907 err = msm_handle_tx_dma(msm_port, dma_count);
908
909 if (err) /* fall back to PIO mode */
910 msm_handle_tx_pio(port, pio_count);
911 }
912
913 static void msm_handle_delta_cts(struct uart_port *port)
914 {
915 msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);
916 port->icount.cts++;
917 wake_up_interruptible(&port->state->port.delta_msr_wait);
918 }
919
920 static irqreturn_t msm_uart_irq(int irq, void *dev_id)
921 {
922 struct uart_port *port = dev_id;
923 struct msm_port *msm_port = UART_TO_MSM(port);
924 struct msm_dma *dma = &msm_port->rx_dma;
925 unsigned long flags;
926 unsigned int misr;
927 u32 val;
928
929 spin_lock_irqsave(&port->lock, flags);
930 misr = msm_read(port, UART_MISR);
931 msm_write(port, 0, UART_IMR); /* disable interrupt */
932
933 if (misr & UART_IMR_RXBREAK_START) {
934 msm_port->break_detected = true;
935 msm_write(port, UART_CR_CMD_RESET_RXBREAK_START, UART_CR);
936 }
937
938 if (misr & (UART_IMR_RXLEV | UART_IMR_RXSTALE)) {
939 if (dma->count) {
940 val = UART_CR_CMD_STALE_EVENT_DISABLE;
941 msm_write(port, val, UART_CR);
942 val = UART_CR_CMD_RESET_STALE_INT;
943 msm_write(port, val, UART_CR);
944 /*
945 * Flush DMA input fifo to memory, this will also
946 * trigger DMA RX completion
947 */
948 dmaengine_terminate_all(dma->chan);
949 } else if (msm_port->is_uartdm) {
950 msm_handle_rx_dm(port, misr);
951 } else {
952 msm_handle_rx(port);
953 }
954 }
955 if (misr & UART_IMR_TXLEV)
956 msm_handle_tx(port);
957 if (misr & UART_IMR_DELTA_CTS)
958 msm_handle_delta_cts(port);
959
960 msm_write(port, msm_port->imr, UART_IMR); /* restore interrupt */
961 spin_unlock_irqrestore(&port->lock, flags);
962
963 return IRQ_HANDLED;
964 }
965
966 static unsigned int msm_tx_empty(struct uart_port *port)
967 {
968 return (msm_read(port, UART_SR) & UART_SR_TX_EMPTY) ? TIOCSER_TEMT : 0;
969 }
970
971 static unsigned int msm_get_mctrl(struct uart_port *port)
972 {
973 return TIOCM_CAR | TIOCM_CTS | TIOCM_DSR | TIOCM_RTS;
974 }
975
976 static void msm_reset(struct uart_port *port)
977 {
978 struct msm_port *msm_port = UART_TO_MSM(port);
979
980 /* reset everything */
981 msm_write(port, UART_CR_CMD_RESET_RX, UART_CR);
982 msm_write(port, UART_CR_CMD_RESET_TX, UART_CR);
983 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
984 msm_write(port, UART_CR_CMD_RESET_BREAK_INT, UART_CR);
985 msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);
986 msm_write(port, UART_CR_CMD_SET_RFR, UART_CR);
987
988 /* Disable DM modes */
989 if (msm_port->is_uartdm)
990 msm_write(port, 0, UARTDM_DMEN);
991 }
992
993 static void msm_set_mctrl(struct uart_port *port, unsigned int mctrl)
994 {
995 unsigned int mr;
996
997 mr = msm_read(port, UART_MR1);
998
999 if (!(mctrl & TIOCM_RTS)) {
1000 mr &= ~UART_MR1_RX_RDY_CTL;
1001 msm_write(port, mr, UART_MR1);
1002 msm_write(port, UART_CR_CMD_RESET_RFR, UART_CR);
1003 } else {
1004 mr |= UART_MR1_RX_RDY_CTL;
1005 msm_write(port, mr, UART_MR1);
1006 }
1007 }
1008
1009 static void msm_break_ctl(struct uart_port *port, int break_ctl)
1010 {
1011 if (break_ctl)
1012 msm_write(port, UART_CR_CMD_START_BREAK, UART_CR);
1013 else
1014 msm_write(port, UART_CR_CMD_STOP_BREAK, UART_CR);
1015 }
1016
1017 struct msm_baud_map {
1018 u16 divisor;
1019 u8 code;
1020 u8 rxstale;
1021 };
1022
1023 static const struct msm_baud_map *
1024 msm_find_best_baud(struct uart_port *port, unsigned int baud,
1025 unsigned long *rate)
1026 {
1027 struct msm_port *msm_port = UART_TO_MSM(port);
1028 unsigned int divisor, result;
1029 unsigned long target, old, best_rate = 0, diff, best_diff = ULONG_MAX;
1030 const struct msm_baud_map *entry, *end, *best;
1031 static const struct msm_baud_map table[] = {
1032 { 1, 0xff, 31 },
1033 { 2, 0xee, 16 },
1034 { 3, 0xdd, 8 },
1035 { 4, 0xcc, 6 },
1036 { 6, 0xbb, 6 },
1037 { 8, 0xaa, 6 },
1038 { 12, 0x99, 6 },
1039 { 16, 0x88, 1 },
1040 { 24, 0x77, 1 },
1041 { 32, 0x66, 1 },
1042 { 48, 0x55, 1 },
1043 { 96, 0x44, 1 },
1044 { 192, 0x33, 1 },
1045 { 384, 0x22, 1 },
1046 { 768, 0x11, 1 },
1047 { 1536, 0x00, 1 },
1048 };
1049
1050 best = table; /* Default to smallest divider */
1051 target = clk_round_rate(msm_port->clk, 16 * baud);
1052 divisor = DIV_ROUND_CLOSEST(target, 16 * baud);
1053
1054 end = table + ARRAY_SIZE(table);
1055 entry = table;
1056 while (entry < end) {
1057 if (entry->divisor <= divisor) {
1058 result = target / entry->divisor / 16;
1059 diff = abs(result - baud);
1060
1061 /* Keep track of best entry */
1062 if (diff < best_diff) {
1063 best_diff = diff;
1064 best = entry;
1065 best_rate = target;
1066 }
1067
1068 if (result == baud)
1069 break;
1070 } else if (entry->divisor > divisor) {
1071 old = target;
1072 target = clk_round_rate(msm_port->clk, old + 1);
1073 /*
1074 * The rate didn't get any faster so we can't do
1075 * better at dividing it down
1076 */
1077 if (target == old)
1078 break;
1079
1080 /* Start the divisor search over at this new rate */
1081 entry = table;
1082 divisor = DIV_ROUND_CLOSEST(target, 16 * baud);
1083 continue;
1084 }
1085 entry++;
1086 }
1087
1088 *rate = best_rate;
1089 return best;
1090 }
1091
1092 static int msm_set_baud_rate(struct uart_port *port, unsigned int baud,
1093 unsigned long *saved_flags)
1094 {
1095 unsigned int rxstale, watermark, mask;
1096 struct msm_port *msm_port = UART_TO_MSM(port);
1097 const struct msm_baud_map *entry;
1098 unsigned long flags, rate;
1099
1100 flags = *saved_flags;
1101 spin_unlock_irqrestore(&port->lock, flags);
1102
1103 entry = msm_find_best_baud(port, baud, &rate);
1104 clk_set_rate(msm_port->clk, rate);
1105 baud = rate / 16 / entry->divisor;
1106
1107 spin_lock_irqsave(&port->lock, flags);
1108 *saved_flags = flags;
1109 port->uartclk = rate;
1110
1111 msm_write(port, entry->code, UART_CSR);
1112
1113 /* RX stale watermark */
1114 rxstale = entry->rxstale;
1115 watermark = UART_IPR_STALE_LSB & rxstale;
1116 if (msm_port->is_uartdm) {
1117 mask = UART_DM_IPR_STALE_TIMEOUT_MSB;
1118 } else {
1119 watermark |= UART_IPR_RXSTALE_LAST;
1120 mask = UART_IPR_STALE_TIMEOUT_MSB;
1121 }
1122
1123 watermark |= mask & (rxstale << 2);
1124
1125 msm_write(port, watermark, UART_IPR);
1126
1127 /* set RX watermark */
1128 watermark = (port->fifosize * 3) / 4;
1129 msm_write(port, watermark, UART_RFWR);
1130
1131 /* set TX watermark */
1132 msm_write(port, 10, UART_TFWR);
1133
1134 msm_write(port, UART_CR_CMD_PROTECTION_EN, UART_CR);
1135 msm_reset(port);
1136
1137 /* Enable RX and TX */
1138 msm_write(port, UART_CR_TX_ENABLE | UART_CR_RX_ENABLE, UART_CR);
1139
1140 /* turn on RX and CTS interrupts */
1141 msm_port->imr = UART_IMR_RXLEV | UART_IMR_RXSTALE |
1142 UART_IMR_CURRENT_CTS | UART_IMR_RXBREAK_START;
1143
1144 msm_write(port, msm_port->imr, UART_IMR);
1145
1146 if (msm_port->is_uartdm) {
1147 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
1148 msm_write(port, 0xFFFFFF, UARTDM_DMRX);
1149 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
1150 }
1151
1152 return baud;
1153 }
1154
1155 static void msm_init_clock(struct uart_port *port)
1156 {
1157 struct msm_port *msm_port = UART_TO_MSM(port);
1158
1159 clk_prepare_enable(msm_port->clk);
1160 clk_prepare_enable(msm_port->pclk);
1161 msm_serial_set_mnd_regs(port);
1162 }
1163
1164 static int msm_startup(struct uart_port *port)
1165 {
1166 struct msm_port *msm_port = UART_TO_MSM(port);
1167 unsigned int data, rfr_level, mask;
1168 int ret;
1169
1170 snprintf(msm_port->name, sizeof(msm_port->name),
1171 "msm_serial%d", port->line);
1172
1173 msm_init_clock(port);
1174
1175 if (likely(port->fifosize > 12))
1176 rfr_level = port->fifosize - 12;
1177 else
1178 rfr_level = port->fifosize;
1179
1180 /* set automatic RFR level */
1181 data = msm_read(port, UART_MR1);
1182
1183 if (msm_port->is_uartdm)
1184 mask = UART_DM_MR1_AUTO_RFR_LEVEL1;
1185 else
1186 mask = UART_MR1_AUTO_RFR_LEVEL1;
1187
1188 data &= ~mask;
1189 data &= ~UART_MR1_AUTO_RFR_LEVEL0;
1190 data |= mask & (rfr_level << 2);
1191 data |= UART_MR1_AUTO_RFR_LEVEL0 & rfr_level;
1192 msm_write(port, data, UART_MR1);
1193
1194 if (msm_port->is_uartdm) {
1195 msm_request_tx_dma(msm_port, msm_port->uart.mapbase);
1196 msm_request_rx_dma(msm_port, msm_port->uart.mapbase);
1197 }
1198
1199 ret = request_irq(port->irq, msm_uart_irq, IRQF_TRIGGER_HIGH,
1200 msm_port->name, port);
1201 if (unlikely(ret))
1202 goto err_irq;
1203
1204 return 0;
1205
1206 err_irq:
1207 if (msm_port->is_uartdm)
1208 msm_release_dma(msm_port);
1209
1210 clk_disable_unprepare(msm_port->pclk);
1211 clk_disable_unprepare(msm_port->clk);
1212
1213 return ret;
1214 }
1215
1216 static void msm_shutdown(struct uart_port *port)
1217 {
1218 struct msm_port *msm_port = UART_TO_MSM(port);
1219
1220 msm_port->imr = 0;
1221 msm_write(port, 0, UART_IMR); /* disable interrupts */
1222
1223 if (msm_port->is_uartdm)
1224 msm_release_dma(msm_port);
1225
1226 clk_disable_unprepare(msm_port->clk);
1227
1228 free_irq(port->irq, port);
1229 }
1230
1231 static void msm_set_termios(struct uart_port *port, struct ktermios *termios,
1232 struct ktermios *old)
1233 {
1234 struct msm_port *msm_port = UART_TO_MSM(port);
1235 struct msm_dma *dma = &msm_port->rx_dma;
1236 unsigned long flags;
1237 unsigned int baud, mr;
1238
1239 spin_lock_irqsave(&port->lock, flags);
1240
1241 if (dma->chan) /* Terminate if any */
1242 msm_stop_dma(port, dma);
1243
1244 /* calculate and set baud rate */
1245 baud = uart_get_baud_rate(port, termios, old, 300, 4000000);
1246 baud = msm_set_baud_rate(port, baud, &flags);
1247 if (tty_termios_baud_rate(termios))
1248 tty_termios_encode_baud_rate(termios, baud, baud);
1249
1250 /* calculate parity */
1251 mr = msm_read(port, UART_MR2);
1252 mr &= ~UART_MR2_PARITY_MODE;
1253 if (termios->c_cflag & PARENB) {
1254 if (termios->c_cflag & PARODD)
1255 mr |= UART_MR2_PARITY_MODE_ODD;
1256 else if (termios->c_cflag & CMSPAR)
1257 mr |= UART_MR2_PARITY_MODE_SPACE;
1258 else
1259 mr |= UART_MR2_PARITY_MODE_EVEN;
1260 }
1261
1262 /* calculate bits per char */
1263 mr &= ~UART_MR2_BITS_PER_CHAR;
1264 switch (termios->c_cflag & CSIZE) {
1265 case CS5:
1266 mr |= UART_MR2_BITS_PER_CHAR_5;
1267 break;
1268 case CS6:
1269 mr |= UART_MR2_BITS_PER_CHAR_6;
1270 break;
1271 case CS7:
1272 mr |= UART_MR2_BITS_PER_CHAR_7;
1273 break;
1274 case CS8:
1275 default:
1276 mr |= UART_MR2_BITS_PER_CHAR_8;
1277 break;
1278 }
1279
1280 /* calculate stop bits */
1281 mr &= ~(UART_MR2_STOP_BIT_LEN_ONE | UART_MR2_STOP_BIT_LEN_TWO);
1282 if (termios->c_cflag & CSTOPB)
1283 mr |= UART_MR2_STOP_BIT_LEN_TWO;
1284 else
1285 mr |= UART_MR2_STOP_BIT_LEN_ONE;
1286
1287 /* set parity, bits per char, and stop bit */
1288 msm_write(port, mr, UART_MR2);
1289
1290 /* calculate and set hardware flow control */
1291 mr = msm_read(port, UART_MR1);
1292 mr &= ~(UART_MR1_CTS_CTL | UART_MR1_RX_RDY_CTL);
1293 if (termios->c_cflag & CRTSCTS) {
1294 mr |= UART_MR1_CTS_CTL;
1295 mr |= UART_MR1_RX_RDY_CTL;
1296 }
1297 msm_write(port, mr, UART_MR1);
1298
1299 /* Configure status bits to ignore based on termio flags. */
1300 port->read_status_mask = 0;
1301 if (termios->c_iflag & INPCK)
1302 port->read_status_mask |= UART_SR_PAR_FRAME_ERR;
1303 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1304 port->read_status_mask |= UART_SR_RX_BREAK;
1305
1306 uart_update_timeout(port, termios->c_cflag, baud);
1307
1308 /* Try to use DMA */
1309 msm_start_rx_dma(msm_port);
1310
1311 spin_unlock_irqrestore(&port->lock, flags);
1312 }
1313
1314 static const char *msm_type(struct uart_port *port)
1315 {
1316 return "MSM";
1317 }
1318
1319 static void msm_release_port(struct uart_port *port)
1320 {
1321 struct platform_device *pdev = to_platform_device(port->dev);
1322 struct resource *uart_resource;
1323 resource_size_t size;
1324
1325 uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1326 if (unlikely(!uart_resource))
1327 return;
1328 size = resource_size(uart_resource);
1329
1330 release_mem_region(port->mapbase, size);
1331 iounmap(port->membase);
1332 port->membase = NULL;
1333 }
1334
1335 static int msm_request_port(struct uart_port *port)
1336 {
1337 struct platform_device *pdev = to_platform_device(port->dev);
1338 struct resource *uart_resource;
1339 resource_size_t size;
1340 int ret;
1341
1342 uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1343 if (unlikely(!uart_resource))
1344 return -ENXIO;
1345
1346 size = resource_size(uart_resource);
1347
1348 if (!request_mem_region(port->mapbase, size, "msm_serial"))
1349 return -EBUSY;
1350
1351 port->membase = ioremap(port->mapbase, size);
1352 if (!port->membase) {
1353 ret = -EBUSY;
1354 goto fail_release_port;
1355 }
1356
1357 return 0;
1358
1359 fail_release_port:
1360 release_mem_region(port->mapbase, size);
1361 return ret;
1362 }
1363
1364 static void msm_config_port(struct uart_port *port, int flags)
1365 {
1366 int ret;
1367
1368 if (flags & UART_CONFIG_TYPE) {
1369 port->type = PORT_MSM;
1370 ret = msm_request_port(port);
1371 if (ret)
1372 return;
1373 }
1374 }
1375
1376 static int msm_verify_port(struct uart_port *port, struct serial_struct *ser)
1377 {
1378 if (unlikely(ser->type != PORT_UNKNOWN && ser->type != PORT_MSM))
1379 return -EINVAL;
1380 if (unlikely(port->irq != ser->irq))
1381 return -EINVAL;
1382 return 0;
1383 }
1384
1385 static void msm_power(struct uart_port *port, unsigned int state,
1386 unsigned int oldstate)
1387 {
1388 struct msm_port *msm_port = UART_TO_MSM(port);
1389
1390 switch (state) {
1391 case 0:
1392 clk_prepare_enable(msm_port->clk);
1393 clk_prepare_enable(msm_port->pclk);
1394 break;
1395 case 3:
1396 clk_disable_unprepare(msm_port->clk);
1397 clk_disable_unprepare(msm_port->pclk);
1398 break;
1399 default:
1400 pr_err("msm_serial: Unknown PM state %d\n", state);
1401 }
1402 }
1403
1404 #ifdef CONFIG_CONSOLE_POLL
1405 static int msm_poll_get_char_single(struct uart_port *port)
1406 {
1407 struct msm_port *msm_port = UART_TO_MSM(port);
1408 unsigned int rf_reg = msm_port->is_uartdm ? UARTDM_RF : UART_RF;
1409
1410 if (!(msm_read(port, UART_SR) & UART_SR_RX_READY))
1411 return NO_POLL_CHAR;
1412
1413 return msm_read(port, rf_reg) & 0xff;
1414 }
1415
1416 static int msm_poll_get_char_dm(struct uart_port *port)
1417 {
1418 int c;
1419 static u32 slop;
1420 static int count;
1421 unsigned char *sp = (unsigned char *)&slop;
1422
1423 /* Check if a previous read had more than one char */
1424 if (count) {
1425 c = sp[sizeof(slop) - count];
1426 count--;
1427 /* Or if FIFO is empty */
1428 } else if (!(msm_read(port, UART_SR) & UART_SR_RX_READY)) {
1429 /*
1430 * If RX packing buffer has less than a word, force stale to
1431 * push contents into RX FIFO
1432 */
1433 count = msm_read(port, UARTDM_RXFS);
1434 count = (count >> UARTDM_RXFS_BUF_SHIFT) & UARTDM_RXFS_BUF_MASK;
1435 if (count) {
1436 msm_write(port, UART_CR_CMD_FORCE_STALE, UART_CR);
1437 slop = msm_read(port, UARTDM_RF);
1438 c = sp[0];
1439 count--;
1440 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
1441 msm_write(port, 0xFFFFFF, UARTDM_DMRX);
1442 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE,
1443 UART_CR);
1444 } else {
1445 c = NO_POLL_CHAR;
1446 }
1447 /* FIFO has a word */
1448 } else {
1449 slop = msm_read(port, UARTDM_RF);
1450 c = sp[0];
1451 count = sizeof(slop) - 1;
1452 }
1453
1454 return c;
1455 }
1456
1457 static int msm_poll_get_char(struct uart_port *port)
1458 {
1459 u32 imr;
1460 int c;
1461 struct msm_port *msm_port = UART_TO_MSM(port);
1462
1463 /* Disable all interrupts */
1464 imr = msm_read(port, UART_IMR);
1465 msm_write(port, 0, UART_IMR);
1466
1467 if (msm_port->is_uartdm)
1468 c = msm_poll_get_char_dm(port);
1469 else
1470 c = msm_poll_get_char_single(port);
1471
1472 /* Enable interrupts */
1473 msm_write(port, imr, UART_IMR);
1474
1475 return c;
1476 }
1477
1478 static void msm_poll_put_char(struct uart_port *port, unsigned char c)
1479 {
1480 u32 imr;
1481 struct msm_port *msm_port = UART_TO_MSM(port);
1482
1483 /* Disable all interrupts */
1484 imr = msm_read(port, UART_IMR);
1485 msm_write(port, 0, UART_IMR);
1486
1487 if (msm_port->is_uartdm)
1488 msm_reset_dm_count(port, 1);
1489
1490 /* Wait until FIFO is empty */
1491 while (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
1492 cpu_relax();
1493
1494 /* Write a character */
1495 msm_write(port, c, msm_port->is_uartdm ? UARTDM_TF : UART_TF);
1496
1497 /* Wait until FIFO is empty */
1498 while (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
1499 cpu_relax();
1500
1501 /* Enable interrupts */
1502 msm_write(port, imr, UART_IMR);
1503 }
1504 #endif
1505
1506 static struct uart_ops msm_uart_pops = {
1507 .tx_empty = msm_tx_empty,
1508 .set_mctrl = msm_set_mctrl,
1509 .get_mctrl = msm_get_mctrl,
1510 .stop_tx = msm_stop_tx,
1511 .start_tx = msm_start_tx,
1512 .stop_rx = msm_stop_rx,
1513 .enable_ms = msm_enable_ms,
1514 .break_ctl = msm_break_ctl,
1515 .startup = msm_startup,
1516 .shutdown = msm_shutdown,
1517 .set_termios = msm_set_termios,
1518 .type = msm_type,
1519 .release_port = msm_release_port,
1520 .request_port = msm_request_port,
1521 .config_port = msm_config_port,
1522 .verify_port = msm_verify_port,
1523 .pm = msm_power,
1524 #ifdef CONFIG_CONSOLE_POLL
1525 .poll_get_char = msm_poll_get_char,
1526 .poll_put_char = msm_poll_put_char,
1527 #endif
1528 };
1529
1530 static struct msm_port msm_uart_ports[] = {
1531 {
1532 .uart = {
1533 .iotype = UPIO_MEM,
1534 .ops = &msm_uart_pops,
1535 .flags = UPF_BOOT_AUTOCONF,
1536 .fifosize = 64,
1537 .line = 0,
1538 },
1539 },
1540 {
1541 .uart = {
1542 .iotype = UPIO_MEM,
1543 .ops = &msm_uart_pops,
1544 .flags = UPF_BOOT_AUTOCONF,
1545 .fifosize = 64,
1546 .line = 1,
1547 },
1548 },
1549 {
1550 .uart = {
1551 .iotype = UPIO_MEM,
1552 .ops = &msm_uart_pops,
1553 .flags = UPF_BOOT_AUTOCONF,
1554 .fifosize = 64,
1555 .line = 2,
1556 },
1557 },
1558 };
1559
1560 #define UART_NR ARRAY_SIZE(msm_uart_ports)
1561
1562 static inline struct uart_port *msm_get_port_from_line(unsigned int line)
1563 {
1564 return &msm_uart_ports[line].uart;
1565 }
1566
1567 #ifdef CONFIG_SERIAL_MSM_CONSOLE
1568 static void __msm_console_write(struct uart_port *port, const char *s,
1569 unsigned int count, bool is_uartdm)
1570 {
1571 int i;
1572 int num_newlines = 0;
1573 bool replaced = false;
1574 void __iomem *tf;
1575
1576 if (is_uartdm)
1577 tf = port->membase + UARTDM_TF;
1578 else
1579 tf = port->membase + UART_TF;
1580
1581 /* Account for newlines that will get a carriage return added */
1582 for (i = 0; i < count; i++)
1583 if (s[i] == '\n')
1584 num_newlines++;
1585 count += num_newlines;
1586
1587 spin_lock(&port->lock);
1588 if (is_uartdm)
1589 msm_reset_dm_count(port, count);
1590
1591 i = 0;
1592 while (i < count) {
1593 int j;
1594 unsigned int num_chars;
1595 char buf[4] = { 0 };
1596
1597 if (is_uartdm)
1598 num_chars = min(count - i, (unsigned int)sizeof(buf));
1599 else
1600 num_chars = 1;
1601
1602 for (j = 0; j < num_chars; j++) {
1603 char c = *s;
1604
1605 if (c == '\n' && !replaced) {
1606 buf[j] = '\r';
1607 j++;
1608 replaced = true;
1609 }
1610 if (j < num_chars) {
1611 buf[j] = c;
1612 s++;
1613 replaced = false;
1614 }
1615 }
1616
1617 while (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
1618 cpu_relax();
1619
1620 iowrite32_rep(tf, buf, 1);
1621 i += num_chars;
1622 }
1623 spin_unlock(&port->lock);
1624 }
1625
1626 static void msm_console_write(struct console *co, const char *s,
1627 unsigned int count)
1628 {
1629 struct uart_port *port;
1630 struct msm_port *msm_port;
1631
1632 BUG_ON(co->index < 0 || co->index >= UART_NR);
1633
1634 port = msm_get_port_from_line(co->index);
1635 msm_port = UART_TO_MSM(port);
1636
1637 __msm_console_write(port, s, count, msm_port->is_uartdm);
1638 }
1639
1640 static int msm_console_setup(struct console *co, char *options)
1641 {
1642 struct uart_port *port;
1643 int baud = 115200;
1644 int bits = 8;
1645 int parity = 'n';
1646 int flow = 'n';
1647
1648 if (unlikely(co->index >= UART_NR || co->index < 0))
1649 return -ENXIO;
1650
1651 port = msm_get_port_from_line(co->index);
1652
1653 if (unlikely(!port->membase))
1654 return -ENXIO;
1655
1656 msm_init_clock(port);
1657
1658 if (options)
1659 uart_parse_options(options, &baud, &parity, &bits, &flow);
1660
1661 pr_info("msm_serial: console setup on port #%d\n", port->line);
1662
1663 return uart_set_options(port, co, baud, parity, bits, flow);
1664 }
1665
1666 static void
1667 msm_serial_early_write(struct console *con, const char *s, unsigned n)
1668 {
1669 struct earlycon_device *dev = con->data;
1670
1671 __msm_console_write(&dev->port, s, n, false);
1672 }
1673
1674 static int __init
1675 msm_serial_early_console_setup(struct earlycon_device *device, const char *opt)
1676 {
1677 if (!device->port.membase)
1678 return -ENODEV;
1679
1680 device->con->write = msm_serial_early_write;
1681 return 0;
1682 }
1683 OF_EARLYCON_DECLARE(msm_serial, "qcom,msm-uart",
1684 msm_serial_early_console_setup);
1685
1686 static void
1687 msm_serial_early_write_dm(struct console *con, const char *s, unsigned n)
1688 {
1689 struct earlycon_device *dev = con->data;
1690
1691 __msm_console_write(&dev->port, s, n, true);
1692 }
1693
1694 static int __init
1695 msm_serial_early_console_setup_dm(struct earlycon_device *device,
1696 const char *opt)
1697 {
1698 if (!device->port.membase)
1699 return -ENODEV;
1700
1701 device->con->write = msm_serial_early_write_dm;
1702 return 0;
1703 }
1704 OF_EARLYCON_DECLARE(msm_serial_dm, "qcom,msm-uartdm",
1705 msm_serial_early_console_setup_dm);
1706
1707 static struct uart_driver msm_uart_driver;
1708
1709 static struct console msm_console = {
1710 .name = "ttyMSM",
1711 .write = msm_console_write,
1712 .device = uart_console_device,
1713 .setup = msm_console_setup,
1714 .flags = CON_PRINTBUFFER,
1715 .index = -1,
1716 .data = &msm_uart_driver,
1717 };
1718
1719 #define MSM_CONSOLE (&msm_console)
1720
1721 #else
1722 #define MSM_CONSOLE NULL
1723 #endif
1724
1725 static struct uart_driver msm_uart_driver = {
1726 .owner = THIS_MODULE,
1727 .driver_name = "msm_serial",
1728 .dev_name = "ttyMSM",
1729 .nr = UART_NR,
1730 .cons = MSM_CONSOLE,
1731 };
1732
1733 static atomic_t msm_uart_next_id = ATOMIC_INIT(0);
1734
1735 static const struct of_device_id msm_uartdm_table[] = {
1736 { .compatible = "qcom,msm-uartdm-v1.1", .data = (void *)UARTDM_1P1 },
1737 { .compatible = "qcom,msm-uartdm-v1.2", .data = (void *)UARTDM_1P2 },
1738 { .compatible = "qcom,msm-uartdm-v1.3", .data = (void *)UARTDM_1P3 },
1739 { .compatible = "qcom,msm-uartdm-v1.4", .data = (void *)UARTDM_1P4 },
1740 { }
1741 };
1742
1743 static int msm_serial_probe(struct platform_device *pdev)
1744 {
1745 struct msm_port *msm_port;
1746 struct resource *resource;
1747 struct uart_port *port;
1748 const struct of_device_id *id;
1749 int irq, line;
1750
1751 if (pdev->dev.of_node)
1752 line = of_alias_get_id(pdev->dev.of_node, "serial");
1753 else
1754 line = pdev->id;
1755
1756 if (line < 0)
1757 line = atomic_inc_return(&msm_uart_next_id) - 1;
1758
1759 if (unlikely(line < 0 || line >= UART_NR))
1760 return -ENXIO;
1761
1762 dev_info(&pdev->dev, "msm_serial: detected port #%d\n", line);
1763
1764 port = msm_get_port_from_line(line);
1765 port->dev = &pdev->dev;
1766 msm_port = UART_TO_MSM(port);
1767
1768 id = of_match_device(msm_uartdm_table, &pdev->dev);
1769 if (id)
1770 msm_port->is_uartdm = (unsigned long)id->data;
1771 else
1772 msm_port->is_uartdm = 0;
1773
1774 msm_port->clk = devm_clk_get(&pdev->dev, "core");
1775 if (IS_ERR(msm_port->clk))
1776 return PTR_ERR(msm_port->clk);
1777
1778 if (msm_port->is_uartdm) {
1779 msm_port->pclk = devm_clk_get(&pdev->dev, "iface");
1780 if (IS_ERR(msm_port->pclk))
1781 return PTR_ERR(msm_port->pclk);
1782 }
1783
1784 port->uartclk = clk_get_rate(msm_port->clk);
1785 dev_info(&pdev->dev, "uartclk = %d\n", port->uartclk);
1786
1787 resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1788 if (unlikely(!resource))
1789 return -ENXIO;
1790 port->mapbase = resource->start;
1791
1792 irq = platform_get_irq(pdev, 0);
1793 if (unlikely(irq < 0))
1794 return -ENXIO;
1795 port->irq = irq;
1796
1797 platform_set_drvdata(pdev, port);
1798
1799 return uart_add_one_port(&msm_uart_driver, port);
1800 }
1801
1802 static int msm_serial_remove(struct platform_device *pdev)
1803 {
1804 struct uart_port *port = platform_get_drvdata(pdev);
1805
1806 uart_remove_one_port(&msm_uart_driver, port);
1807
1808 return 0;
1809 }
1810
1811 static const struct of_device_id msm_match_table[] = {
1812 { .compatible = "qcom,msm-uart" },
1813 { .compatible = "qcom,msm-uartdm" },
1814 {}
1815 };
1816 MODULE_DEVICE_TABLE(of, msm_match_table);
1817
1818 static int __maybe_unused msm_serial_suspend(struct device *dev)
1819 {
1820 struct msm_port *port = dev_get_drvdata(dev);
1821
1822 uart_suspend_port(&msm_uart_driver, &port->uart);
1823
1824 return 0;
1825 }
1826
1827 static int __maybe_unused msm_serial_resume(struct device *dev)
1828 {
1829 struct msm_port *port = dev_get_drvdata(dev);
1830
1831 uart_resume_port(&msm_uart_driver, &port->uart);
1832
1833 return 0;
1834 }
1835
1836 static const struct dev_pm_ops msm_serial_dev_pm_ops = {
1837 SET_SYSTEM_SLEEP_PM_OPS(msm_serial_suspend, msm_serial_resume)
1838 };
1839
1840 static struct platform_driver msm_platform_driver = {
1841 .remove = msm_serial_remove,
1842 .probe = msm_serial_probe,
1843 .driver = {
1844 .name = "msm_serial",
1845 .pm = &msm_serial_dev_pm_ops,
1846 .of_match_table = msm_match_table,
1847 },
1848 };
1849
1850 static int __init msm_serial_init(void)
1851 {
1852 int ret;
1853
1854 ret = uart_register_driver(&msm_uart_driver);
1855 if (unlikely(ret))
1856 return ret;
1857
1858 ret = platform_driver_register(&msm_platform_driver);
1859 if (unlikely(ret))
1860 uart_unregister_driver(&msm_uart_driver);
1861
1862 pr_info("msm_serial: driver initialized\n");
1863
1864 return ret;
1865 }
1866
1867 static void __exit msm_serial_exit(void)
1868 {
1869 platform_driver_unregister(&msm_platform_driver);
1870 uart_unregister_driver(&msm_uart_driver);
1871 }
1872
1873 module_init(msm_serial_init);
1874 module_exit(msm_serial_exit);
1875
1876 MODULE_AUTHOR("Robert Love <rlove@google.com>");
1877 MODULE_DESCRIPTION("Driver for msm7x serial device");
1878 MODULE_LICENSE("GPL");
Linux with added FPC-III support