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staging: erofs: integrate decompression inplace
[linux/fpc-iii.git] / drivers / tty / serial / serial-tegra.c
blobd5269aaaf9b238235239be10c2440d8af70bb23d
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * serial_tegra.c
4 *
5 * High-speed serial driver for NVIDIA Tegra SoCs
6 *
7 * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved.
8 *
9 * Author: Laxman Dewangan <ldewangan@nvidia.com>
10 */
11
12 #include <linux/clk.h>
13 #include <linux/debugfs.h>
14 #include <linux/delay.h>
15 #include <linux/dmaengine.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/dmapool.h>
18 #include <linux/err.h>
19 #include <linux/io.h>
20 #include <linux/irq.h>
21 #include <linux/module.h>
22 #include <linux/of.h>
23 #include <linux/of_device.h>
24 #include <linux/pagemap.h>
25 #include <linux/platform_device.h>
26 #include <linux/reset.h>
27 #include <linux/serial.h>
28 #include <linux/serial_8250.h>
29 #include <linux/serial_core.h>
30 #include <linux/serial_reg.h>
31 #include <linux/slab.h>
32 #include <linux/string.h>
33 #include <linux/termios.h>
34 #include <linux/tty.h>
35 #include <linux/tty_flip.h>
36
37 #define TEGRA_UART_TYPE "TEGRA_UART"
38 #define TX_EMPTY_STATUS (UART_LSR_TEMT | UART_LSR_THRE)
39 #define BYTES_TO_ALIGN(x) ((unsigned long)(x) & 0x3)
40
41 #define TEGRA_UART_RX_DMA_BUFFER_SIZE 4096
42 #define TEGRA_UART_LSR_TXFIFO_FULL 0x100
43 #define TEGRA_UART_IER_EORD 0x20
44 #define TEGRA_UART_MCR_RTS_EN 0x40
45 #define TEGRA_UART_MCR_CTS_EN 0x20
46 #define TEGRA_UART_LSR_ANY (UART_LSR_OE | UART_LSR_BI | \
47 UART_LSR_PE | UART_LSR_FE)
48 #define TEGRA_UART_IRDA_CSR 0x08
49 #define TEGRA_UART_SIR_ENABLED 0x80
50
51 #define TEGRA_UART_TX_PIO 1
52 #define TEGRA_UART_TX_DMA 2
53 #define TEGRA_UART_MIN_DMA 16
54 #define TEGRA_UART_FIFO_SIZE 32
55
56 /*
57 * Tx fifo trigger level setting in tegra uart is in
58 * reverse way then conventional uart.
59 */
60 #define TEGRA_UART_TX_TRIG_16B 0x00
61 #define TEGRA_UART_TX_TRIG_8B 0x10
62 #define TEGRA_UART_TX_TRIG_4B 0x20
63 #define TEGRA_UART_TX_TRIG_1B 0x30
64
65 #define TEGRA_UART_MAXIMUM 5
66
67 /* Default UART setting when started: 115200 no parity, stop, 8 data bits */
68 #define TEGRA_UART_DEFAULT_BAUD 115200
69 #define TEGRA_UART_DEFAULT_LSR UART_LCR_WLEN8
70
71 /* Tx transfer mode */
72 #define TEGRA_TX_PIO 1
73 #define TEGRA_TX_DMA 2
74
75 /**
76 * tegra_uart_chip_data: SOC specific data.
77 *
78 * @tx_fifo_full_status: Status flag available for checking tx fifo full.
79 * @allow_txfifo_reset_fifo_mode: allow_tx fifo reset with fifo mode or not.
80 * Tegra30 does not allow this.
81 * @support_clk_src_div: Clock source support the clock divider.
82 */
83 struct tegra_uart_chip_data {
84 bool tx_fifo_full_status;
85 bool allow_txfifo_reset_fifo_mode;
86 bool support_clk_src_div;
87 };
88
89 struct tegra_uart_port {
90 struct uart_port uport;
91 const struct tegra_uart_chip_data *cdata;
92
93 struct clk *uart_clk;
94 struct reset_control *rst;
95 unsigned int current_baud;
96
97 /* Register shadow */
98 unsigned long fcr_shadow;
99 unsigned long mcr_shadow;
100 unsigned long lcr_shadow;
101 unsigned long ier_shadow;
102 bool rts_active;
103
104 int tx_in_progress;
105 unsigned int tx_bytes;
106
107 bool enable_modem_interrupt;
108
109 bool rx_timeout;
110 int rx_in_progress;
111 int symb_bit;
112
113 struct dma_chan *rx_dma_chan;
114 struct dma_chan *tx_dma_chan;
115 dma_addr_t rx_dma_buf_phys;
116 dma_addr_t tx_dma_buf_phys;
117 unsigned char *rx_dma_buf_virt;
118 unsigned char *tx_dma_buf_virt;
119 struct dma_async_tx_descriptor *tx_dma_desc;
120 struct dma_async_tx_descriptor *rx_dma_desc;
121 dma_cookie_t tx_cookie;
122 dma_cookie_t rx_cookie;
123 unsigned int tx_bytes_requested;
124 unsigned int rx_bytes_requested;
125 };
126
127 static void tegra_uart_start_next_tx(struct tegra_uart_port *tup);
128 static int tegra_uart_start_rx_dma(struct tegra_uart_port *tup);
129
130 static inline unsigned long tegra_uart_read(struct tegra_uart_port *tup,
131 unsigned long reg)
132 {
133 return readl(tup->uport.membase + (reg << tup->uport.regshift));
134 }
135
136 static inline void tegra_uart_write(struct tegra_uart_port *tup, unsigned val,
137 unsigned long reg)
138 {
139 writel(val, tup->uport.membase + (reg << tup->uport.regshift));
140 }
141
142 static inline struct tegra_uart_port *to_tegra_uport(struct uart_port *u)
143 {
144 return container_of(u, struct tegra_uart_port, uport);
145 }
146
147 static unsigned int tegra_uart_get_mctrl(struct uart_port *u)
148 {
149 struct tegra_uart_port *tup = to_tegra_uport(u);
150
151 /*
152 * RI - Ring detector is active
153 * CD/DCD/CAR - Carrier detect is always active. For some reason
154 * linux has different names for carrier detect.
155 * DSR - Data Set ready is active as the hardware doesn't support it.
156 * Don't know if the linux support this yet?
157 * CTS - Clear to send. Always set to active, as the hardware handles
158 * CTS automatically.
159 */
160 if (tup->enable_modem_interrupt)
161 return TIOCM_RI | TIOCM_CD | TIOCM_DSR | TIOCM_CTS;
162 return TIOCM_CTS;
163 }
164
165 static void set_rts(struct tegra_uart_port *tup, bool active)
166 {
167 unsigned long mcr;
168
169 mcr = tup->mcr_shadow;
170 if (active)
171 mcr |= TEGRA_UART_MCR_RTS_EN;
172 else
173 mcr &= ~TEGRA_UART_MCR_RTS_EN;
174 if (mcr != tup->mcr_shadow) {
175 tegra_uart_write(tup, mcr, UART_MCR);
176 tup->mcr_shadow = mcr;
177 }
178 }
179
180 static void set_dtr(struct tegra_uart_port *tup, bool active)
181 {
182 unsigned long mcr;
183
184 mcr = tup->mcr_shadow;
185 if (active)
186 mcr |= UART_MCR_DTR;
187 else
188 mcr &= ~UART_MCR_DTR;
189 if (mcr != tup->mcr_shadow) {
190 tegra_uart_write(tup, mcr, UART_MCR);
191 tup->mcr_shadow = mcr;
192 }
193 }
194
195 static void tegra_uart_set_mctrl(struct uart_port *u, unsigned int mctrl)
196 {
197 struct tegra_uart_port *tup = to_tegra_uport(u);
198 int dtr_enable;
199
200 tup->rts_active = !!(mctrl & TIOCM_RTS);
201 set_rts(tup, tup->rts_active);
202
203 dtr_enable = !!(mctrl & TIOCM_DTR);
204 set_dtr(tup, dtr_enable);
205 }
206
207 static void tegra_uart_break_ctl(struct uart_port *u, int break_ctl)
208 {
209 struct tegra_uart_port *tup = to_tegra_uport(u);
210 unsigned long lcr;
211
212 lcr = tup->lcr_shadow;
213 if (break_ctl)
214 lcr |= UART_LCR_SBC;
215 else
216 lcr &= ~UART_LCR_SBC;
217 tegra_uart_write(tup, lcr, UART_LCR);
218 tup->lcr_shadow = lcr;
219 }
220
221 /**
222 * tegra_uart_wait_cycle_time: Wait for N UART clock periods
223 *
224 * @tup: Tegra serial port data structure.
225 * @cycles: Number of clock periods to wait.
226 *
227 * Tegra UARTs are clocked at 16X the baud/bit rate and hence the UART
228 * clock speed is 16X the current baud rate.
229 */
230 static void tegra_uart_wait_cycle_time(struct tegra_uart_port *tup,
231 unsigned int cycles)
232 {
233 if (tup->current_baud)
234 udelay(DIV_ROUND_UP(cycles * 1000000, tup->current_baud * 16));
235 }
236
237 /* Wait for a symbol-time. */
238 static void tegra_uart_wait_sym_time(struct tegra_uart_port *tup,
239 unsigned int syms)
240 {
241 if (tup->current_baud)
242 udelay(DIV_ROUND_UP(syms * tup->symb_bit * 1000000,
243 tup->current_baud));
244 }
245
246 static void tegra_uart_fifo_reset(struct tegra_uart_port *tup, u8 fcr_bits)
247 {
248 unsigned long fcr = tup->fcr_shadow;
249
250 if (tup->cdata->allow_txfifo_reset_fifo_mode) {
251 fcr |= fcr_bits & (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
252 tegra_uart_write(tup, fcr, UART_FCR);
253 } else {
254 fcr &= ~UART_FCR_ENABLE_FIFO;
255 tegra_uart_write(tup, fcr, UART_FCR);
256 udelay(60);
257 fcr |= fcr_bits & (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
258 tegra_uart_write(tup, fcr, UART_FCR);
259 fcr |= UART_FCR_ENABLE_FIFO;
260 tegra_uart_write(tup, fcr, UART_FCR);
261 }
262
263 /* Dummy read to ensure the write is posted */
264 tegra_uart_read(tup, UART_SCR);
265
266 /*
267 * For all tegra devices (up to t210), there is a hardware issue that
268 * requires software to wait for 32 UART clock periods for the flush
269 * to propagate, otherwise data could be lost.
270 */
271 tegra_uart_wait_cycle_time(tup, 32);
272 }
273
274 static int tegra_set_baudrate(struct tegra_uart_port *tup, unsigned int baud)
275 {
276 unsigned long rate;
277 unsigned int divisor;
278 unsigned long lcr;
279 int ret;
280
281 if (tup->current_baud == baud)
282 return 0;
283
284 if (tup->cdata->support_clk_src_div) {
285 rate = baud * 16;
286 ret = clk_set_rate(tup->uart_clk, rate);
287 if (ret < 0) {
288 dev_err(tup->uport.dev,
289 "clk_set_rate() failed for rate %lu\n", rate);
290 return ret;
291 }
292 divisor = 1;
293 } else {
294 rate = clk_get_rate(tup->uart_clk);
295 divisor = DIV_ROUND_CLOSEST(rate, baud * 16);
296 }
297
298 lcr = tup->lcr_shadow;
299 lcr |= UART_LCR_DLAB;
300 tegra_uart_write(tup, lcr, UART_LCR);
301
302 tegra_uart_write(tup, divisor & 0xFF, UART_TX);
303 tegra_uart_write(tup, ((divisor >> 8) & 0xFF), UART_IER);
304
305 lcr &= ~UART_LCR_DLAB;
306 tegra_uart_write(tup, lcr, UART_LCR);
307
308 /* Dummy read to ensure the write is posted */
309 tegra_uart_read(tup, UART_SCR);
310
311 tup->current_baud = baud;
312
313 /* wait two character intervals at new rate */
314 tegra_uart_wait_sym_time(tup, 2);
315 return 0;
316 }
317
318 static char tegra_uart_decode_rx_error(struct tegra_uart_port *tup,
319 unsigned long lsr)
320 {
321 char flag = TTY_NORMAL;
322
323 if (unlikely(lsr & TEGRA_UART_LSR_ANY)) {
324 if (lsr & UART_LSR_OE) {
325 /* Overrrun error */
326 flag = TTY_OVERRUN;
327 tup->uport.icount.overrun++;
328 dev_err(tup->uport.dev, "Got overrun errors\n");
329 } else if (lsr & UART_LSR_PE) {
330 /* Parity error */
331 flag = TTY_PARITY;
332 tup->uport.icount.parity++;
333 dev_err(tup->uport.dev, "Got Parity errors\n");
334 } else if (lsr & UART_LSR_FE) {
335 flag = TTY_FRAME;
336 tup->uport.icount.frame++;
337 dev_err(tup->uport.dev, "Got frame errors\n");
338 } else if (lsr & UART_LSR_BI) {
339 dev_err(tup->uport.dev, "Got Break\n");
340 tup->uport.icount.brk++;
341 /* If FIFO read error without any data, reset Rx FIFO */
342 if (!(lsr & UART_LSR_DR) && (lsr & UART_LSR_FIFOE))
343 tegra_uart_fifo_reset(tup, UART_FCR_CLEAR_RCVR);
344 }
345 }
346 return flag;
347 }
348
349 static int tegra_uart_request_port(struct uart_port *u)
350 {
351 return 0;
352 }
353
354 static void tegra_uart_release_port(struct uart_port *u)
355 {
356 /* Nothing to do here */
357 }
358
359 static void tegra_uart_fill_tx_fifo(struct tegra_uart_port *tup, int max_bytes)
360 {
361 struct circ_buf *xmit = &tup->uport.state->xmit;
362 int i;
363
364 for (i = 0; i < max_bytes; i++) {
365 BUG_ON(uart_circ_empty(xmit));
366 if (tup->cdata->tx_fifo_full_status) {
367 unsigned long lsr = tegra_uart_read(tup, UART_LSR);
368 if ((lsr & TEGRA_UART_LSR_TXFIFO_FULL))
369 break;
370 }
371 tegra_uart_write(tup, xmit->buf[xmit->tail], UART_TX);
372 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
373 tup->uport.icount.tx++;
374 }
375 }
376
377 static void tegra_uart_start_pio_tx(struct tegra_uart_port *tup,
378 unsigned int bytes)
379 {
380 if (bytes > TEGRA_UART_MIN_DMA)
381 bytes = TEGRA_UART_MIN_DMA;
382
383 tup->tx_in_progress = TEGRA_UART_TX_PIO;
384 tup->tx_bytes = bytes;
385 tup->ier_shadow |= UART_IER_THRI;
386 tegra_uart_write(tup, tup->ier_shadow, UART_IER);
387 }
388
389 static void tegra_uart_tx_dma_complete(void *args)
390 {
391 struct tegra_uart_port *tup = args;
392 struct circ_buf *xmit = &tup->uport.state->xmit;
393 struct dma_tx_state state;
394 unsigned long flags;
395 unsigned int count;
396
397 dmaengine_tx_status(tup->tx_dma_chan, tup->tx_cookie, &state);
398 count = tup->tx_bytes_requested - state.residue;
399 async_tx_ack(tup->tx_dma_desc);
400 spin_lock_irqsave(&tup->uport.lock, flags);
401 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
402 tup->tx_in_progress = 0;
403 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
404 uart_write_wakeup(&tup->uport);
405 tegra_uart_start_next_tx(tup);
406 spin_unlock_irqrestore(&tup->uport.lock, flags);
407 }
408
409 static int tegra_uart_start_tx_dma(struct tegra_uart_port *tup,
410 unsigned long count)
411 {
412 struct circ_buf *xmit = &tup->uport.state->xmit;
413 dma_addr_t tx_phys_addr;
414
415 dma_sync_single_for_device(tup->uport.dev, tup->tx_dma_buf_phys,
416 UART_XMIT_SIZE, DMA_TO_DEVICE);
417
418 tup->tx_bytes = count & ~(0xF);
419 tx_phys_addr = tup->tx_dma_buf_phys + xmit->tail;
420 tup->tx_dma_desc = dmaengine_prep_slave_single(tup->tx_dma_chan,
421 tx_phys_addr, tup->tx_bytes, DMA_MEM_TO_DEV,
422 DMA_PREP_INTERRUPT);
423 if (!tup->tx_dma_desc) {
424 dev_err(tup->uport.dev, "Not able to get desc for Tx\n");
425 return -EIO;
426 }
427
428 tup->tx_dma_desc->callback = tegra_uart_tx_dma_complete;
429 tup->tx_dma_desc->callback_param = tup;
430 tup->tx_in_progress = TEGRA_UART_TX_DMA;
431 tup->tx_bytes_requested = tup->tx_bytes;
432 tup->tx_cookie = dmaengine_submit(tup->tx_dma_desc);
433 dma_async_issue_pending(tup->tx_dma_chan);
434 return 0;
435 }
436
437 static void tegra_uart_start_next_tx(struct tegra_uart_port *tup)
438 {
439 unsigned long tail;
440 unsigned long count;
441 struct circ_buf *xmit = &tup->uport.state->xmit;
442
443 tail = (unsigned long)&xmit->buf[xmit->tail];
444 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
445 if (!count)
446 return;
447
448 if (count < TEGRA_UART_MIN_DMA)
449 tegra_uart_start_pio_tx(tup, count);
450 else if (BYTES_TO_ALIGN(tail) > 0)
451 tegra_uart_start_pio_tx(tup, BYTES_TO_ALIGN(tail));
452 else
453 tegra_uart_start_tx_dma(tup, count);
454 }
455
456 /* Called by serial core driver with u->lock taken. */
457 static void tegra_uart_start_tx(struct uart_port *u)
458 {
459 struct tegra_uart_port *tup = to_tegra_uport(u);
460 struct circ_buf *xmit = &u->state->xmit;
461
462 if (!uart_circ_empty(xmit) && !tup->tx_in_progress)
463 tegra_uart_start_next_tx(tup);
464 }
465
466 static unsigned int tegra_uart_tx_empty(struct uart_port *u)
467 {
468 struct tegra_uart_port *tup = to_tegra_uport(u);
469 unsigned int ret = 0;
470 unsigned long flags;
471
472 spin_lock_irqsave(&u->lock, flags);
473 if (!tup->tx_in_progress) {
474 unsigned long lsr = tegra_uart_read(tup, UART_LSR);
475 if ((lsr & TX_EMPTY_STATUS) == TX_EMPTY_STATUS)
476 ret = TIOCSER_TEMT;
477 }
478 spin_unlock_irqrestore(&u->lock, flags);
479 return ret;
480 }
481
482 static void tegra_uart_stop_tx(struct uart_port *u)
483 {
484 struct tegra_uart_port *tup = to_tegra_uport(u);
485 struct circ_buf *xmit = &tup->uport.state->xmit;
486 struct dma_tx_state state;
487 unsigned int count;
488
489 if (tup->tx_in_progress != TEGRA_UART_TX_DMA)
490 return;
491
492 dmaengine_terminate_all(tup->tx_dma_chan);
493 dmaengine_tx_status(tup->tx_dma_chan, tup->tx_cookie, &state);
494 count = tup->tx_bytes_requested - state.residue;
495 async_tx_ack(tup->tx_dma_desc);
496 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
497 tup->tx_in_progress = 0;
498 }
499
500 static void tegra_uart_handle_tx_pio(struct tegra_uart_port *tup)
501 {
502 struct circ_buf *xmit = &tup->uport.state->xmit;
503
504 tegra_uart_fill_tx_fifo(tup, tup->tx_bytes);
505 tup->tx_in_progress = 0;
506 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
507 uart_write_wakeup(&tup->uport);
508 tegra_uart_start_next_tx(tup);
509 }
510
511 static void tegra_uart_handle_rx_pio(struct tegra_uart_port *tup,
512 struct tty_port *tty)
513 {
514 do {
515 char flag = TTY_NORMAL;
516 unsigned long lsr = 0;
517 unsigned char ch;
518
519 lsr = tegra_uart_read(tup, UART_LSR);
520 if (!(lsr & UART_LSR_DR))
521 break;
522
523 flag = tegra_uart_decode_rx_error(tup, lsr);
524 ch = (unsigned char) tegra_uart_read(tup, UART_RX);
525 tup->uport.icount.rx++;
526
527 if (!uart_handle_sysrq_char(&tup->uport, ch) && tty)
528 tty_insert_flip_char(tty, ch, flag);
529 } while (1);
530 }
531
532 static void tegra_uart_copy_rx_to_tty(struct tegra_uart_port *tup,
533 struct tty_port *tty,
534 unsigned int count)
535 {
536 int copied;
537
538 /* If count is zero, then there is no data to be copied */
539 if (!count)
540 return;
541
542 tup->uport.icount.rx += count;
543 if (!tty) {
544 dev_err(tup->uport.dev, "No tty port\n");
545 return;
546 }
547 dma_sync_single_for_cpu(tup->uport.dev, tup->rx_dma_buf_phys,
548 TEGRA_UART_RX_DMA_BUFFER_SIZE, DMA_FROM_DEVICE);
549 copied = tty_insert_flip_string(tty,
550 ((unsigned char *)(tup->rx_dma_buf_virt)), count);
551 if (copied != count) {
552 WARN_ON(1);
553 dev_err(tup->uport.dev, "RxData copy to tty layer failed\n");
554 }
555 dma_sync_single_for_device(tup->uport.dev, tup->rx_dma_buf_phys,
556 TEGRA_UART_RX_DMA_BUFFER_SIZE, DMA_TO_DEVICE);
557 }
558
559 static void tegra_uart_rx_buffer_push(struct tegra_uart_port *tup,
560 unsigned int residue)
561 {
562 struct tty_port *port = &tup->uport.state->port;
563 struct tty_struct *tty = tty_port_tty_get(port);
564 unsigned int count;
565
566 async_tx_ack(tup->rx_dma_desc);
567 count = tup->rx_bytes_requested - residue;
568
569 /* If we are here, DMA is stopped */
570 tegra_uart_copy_rx_to_tty(tup, port, count);
571
572 tegra_uart_handle_rx_pio(tup, port);
573 if (tty) {
574 tty_flip_buffer_push(port);
575 tty_kref_put(tty);
576 }
577 }
578
579 static void tegra_uart_rx_dma_complete(void *args)
580 {
581 struct tegra_uart_port *tup = args;
582 struct uart_port *u = &tup->uport;
583 unsigned long flags;
584 struct dma_tx_state state;
585 enum dma_status status;
586
587 spin_lock_irqsave(&u->lock, flags);
588
589 status = dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state);
590
591 if (status == DMA_IN_PROGRESS) {
592 dev_dbg(tup->uport.dev, "RX DMA is in progress\n");
593 goto done;
594 }
595
596 /* Deactivate flow control to stop sender */
597 if (tup->rts_active)
598 set_rts(tup, false);
599
600 tegra_uart_rx_buffer_push(tup, 0);
601 tegra_uart_start_rx_dma(tup);
602
603 /* Activate flow control to start transfer */
604 if (tup->rts_active)
605 set_rts(tup, true);
606
607 done:
608 spin_unlock_irqrestore(&u->lock, flags);
609 }
610
611 static void tegra_uart_handle_rx_dma(struct tegra_uart_port *tup)
612 {
613 struct dma_tx_state state;
614
615 /* Deactivate flow control to stop sender */
616 if (tup->rts_active)
617 set_rts(tup, false);
618
619 dmaengine_terminate_all(tup->rx_dma_chan);
620 dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state);
621 tegra_uart_rx_buffer_push(tup, state.residue);
622 tegra_uart_start_rx_dma(tup);
623
624 if (tup->rts_active)
625 set_rts(tup, true);
626 }
627
628 static int tegra_uart_start_rx_dma(struct tegra_uart_port *tup)
629 {
630 unsigned int count = TEGRA_UART_RX_DMA_BUFFER_SIZE;
631
632 tup->rx_dma_desc = dmaengine_prep_slave_single(tup->rx_dma_chan,
633 tup->rx_dma_buf_phys, count, DMA_DEV_TO_MEM,
634 DMA_PREP_INTERRUPT);
635 if (!tup->rx_dma_desc) {
636 dev_err(tup->uport.dev, "Not able to get desc for Rx\n");
637 return -EIO;
638 }
639
640 tup->rx_dma_desc->callback = tegra_uart_rx_dma_complete;
641 tup->rx_dma_desc->callback_param = tup;
642 dma_sync_single_for_device(tup->uport.dev, tup->rx_dma_buf_phys,
643 count, DMA_TO_DEVICE);
644 tup->rx_bytes_requested = count;
645 tup->rx_cookie = dmaengine_submit(tup->rx_dma_desc);
646 dma_async_issue_pending(tup->rx_dma_chan);
647 return 0;
648 }
649
650 static void tegra_uart_handle_modem_signal_change(struct uart_port *u)
651 {
652 struct tegra_uart_port *tup = to_tegra_uport(u);
653 unsigned long msr;
654
655 msr = tegra_uart_read(tup, UART_MSR);
656 if (!(msr & UART_MSR_ANY_DELTA))
657 return;
658
659 if (msr & UART_MSR_TERI)
660 tup->uport.icount.rng++;
661 if (msr & UART_MSR_DDSR)
662 tup->uport.icount.dsr++;
663 /* We may only get DDCD when HW init and reset */
664 if (msr & UART_MSR_DDCD)
665 uart_handle_dcd_change(&tup->uport, msr & UART_MSR_DCD);
666 /* Will start/stop_tx accordingly */
667 if (msr & UART_MSR_DCTS)
668 uart_handle_cts_change(&tup->uport, msr & UART_MSR_CTS);
669 }
670
671 static irqreturn_t tegra_uart_isr(int irq, void *data)
672 {
673 struct tegra_uart_port *tup = data;
674 struct uart_port *u = &tup->uport;
675 unsigned long iir;
676 unsigned long ier;
677 bool is_rx_int = false;
678 unsigned long flags;
679
680 spin_lock_irqsave(&u->lock, flags);
681 while (1) {
682 iir = tegra_uart_read(tup, UART_IIR);
683 if (iir & UART_IIR_NO_INT) {
684 if (is_rx_int) {
685 tegra_uart_handle_rx_dma(tup);
686 if (tup->rx_in_progress) {
687 ier = tup->ier_shadow;
688 ier |= (UART_IER_RLSI | UART_IER_RTOIE |
689 TEGRA_UART_IER_EORD);
690 tup->ier_shadow = ier;
691 tegra_uart_write(tup, ier, UART_IER);
692 }
693 }
694 spin_unlock_irqrestore(&u->lock, flags);
695 return IRQ_HANDLED;
696 }
697
698 switch ((iir >> 1) & 0x7) {
699 case 0: /* Modem signal change interrupt */
700 tegra_uart_handle_modem_signal_change(u);
701 break;
702
703 case 1: /* Transmit interrupt only triggered when using PIO */
704 tup->ier_shadow &= ~UART_IER_THRI;
705 tegra_uart_write(tup, tup->ier_shadow, UART_IER);
706 tegra_uart_handle_tx_pio(tup);
707 break;
708
709 case 4: /* End of data */
710 case 6: /* Rx timeout */
711 case 2: /* Receive */
712 if (!is_rx_int) {
713 is_rx_int = true;
714 /* Disable Rx interrupts */
715 ier = tup->ier_shadow;
716 ier |= UART_IER_RDI;
717 tegra_uart_write(tup, ier, UART_IER);
718 ier &= ~(UART_IER_RDI | UART_IER_RLSI |
719 UART_IER_RTOIE | TEGRA_UART_IER_EORD);
720 tup->ier_shadow = ier;
721 tegra_uart_write(tup, ier, UART_IER);
722 }
723 break;
724
725 case 3: /* Receive error */
726 tegra_uart_decode_rx_error(tup,
727 tegra_uart_read(tup, UART_LSR));
728 break;
729
730 case 5: /* break nothing to handle */
731 case 7: /* break nothing to handle */
732 break;
733 }
734 }
735 }
736
737 static void tegra_uart_stop_rx(struct uart_port *u)
738 {
739 struct tegra_uart_port *tup = to_tegra_uport(u);
740 struct dma_tx_state state;
741 unsigned long ier;
742
743 if (tup->rts_active)
744 set_rts(tup, false);
745
746 if (!tup->rx_in_progress)
747 return;
748
749 tegra_uart_wait_sym_time(tup, 1); /* wait one character interval */
750
751 ier = tup->ier_shadow;
752 ier &= ~(UART_IER_RDI | UART_IER_RLSI | UART_IER_RTOIE |
753 TEGRA_UART_IER_EORD);
754 tup->ier_shadow = ier;
755 tegra_uart_write(tup, ier, UART_IER);
756 tup->rx_in_progress = 0;
757 dmaengine_terminate_all(tup->rx_dma_chan);
758 dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state);
759 tegra_uart_rx_buffer_push(tup, state.residue);
760 }
761
762 static void tegra_uart_hw_deinit(struct tegra_uart_port *tup)
763 {
764 unsigned long flags;
765 unsigned long char_time = DIV_ROUND_UP(10000000, tup->current_baud);
766 unsigned long fifo_empty_time = tup->uport.fifosize * char_time;
767 unsigned long wait_time;
768 unsigned long lsr;
769 unsigned long msr;
770 unsigned long mcr;
771
772 /* Disable interrupts */
773 tegra_uart_write(tup, 0, UART_IER);
774
775 lsr = tegra_uart_read(tup, UART_LSR);
776 if ((lsr & UART_LSR_TEMT) != UART_LSR_TEMT) {
777 msr = tegra_uart_read(tup, UART_MSR);
778 mcr = tegra_uart_read(tup, UART_MCR);
779 if ((mcr & TEGRA_UART_MCR_CTS_EN) && (msr & UART_MSR_CTS))
780 dev_err(tup->uport.dev,
781 "Tx Fifo not empty, CTS disabled, waiting\n");
782
783 /* Wait for Tx fifo to be empty */
784 while ((lsr & UART_LSR_TEMT) != UART_LSR_TEMT) {
785 wait_time = min(fifo_empty_time, 100lu);
786 udelay(wait_time);
787 fifo_empty_time -= wait_time;
788 if (!fifo_empty_time) {
789 msr = tegra_uart_read(tup, UART_MSR);
790 mcr = tegra_uart_read(tup, UART_MCR);
791 if ((mcr & TEGRA_UART_MCR_CTS_EN) &&
792 (msr & UART_MSR_CTS))
793 dev_err(tup->uport.dev,
794 "Slave not ready\n");
795 break;
796 }
797 lsr = tegra_uart_read(tup, UART_LSR);
798 }
799 }
800
801 spin_lock_irqsave(&tup->uport.lock, flags);
802 /* Reset the Rx and Tx FIFOs */
803 tegra_uart_fifo_reset(tup, UART_FCR_CLEAR_XMIT | UART_FCR_CLEAR_RCVR);
804 tup->current_baud = 0;
805 spin_unlock_irqrestore(&tup->uport.lock, flags);
806
807 clk_disable_unprepare(tup->uart_clk);
808 }
809
810 static int tegra_uart_hw_init(struct tegra_uart_port *tup)
811 {
812 int ret;
813
814 tup->fcr_shadow = 0;
815 tup->mcr_shadow = 0;
816 tup->lcr_shadow = 0;
817 tup->ier_shadow = 0;
818 tup->current_baud = 0;
819
820 clk_prepare_enable(tup->uart_clk);
821
822 /* Reset the UART controller to clear all previous status.*/
823 reset_control_assert(tup->rst);
824 udelay(10);
825 reset_control_deassert(tup->rst);
826
827 tup->rx_in_progress = 0;
828 tup->tx_in_progress = 0;
829
830 /*
831 * Set the trigger level
832 *
833 * For PIO mode:
834 *
835 * For receive, this will interrupt the CPU after that many number of
836 * bytes are received, for the remaining bytes the receive timeout
837 * interrupt is received. Rx high watermark is set to 4.
838 *
839 * For transmit, if the trasnmit interrupt is enabled, this will
840 * interrupt the CPU when the number of entries in the FIFO reaches the
841 * low watermark. Tx low watermark is set to 16 bytes.
842 *
843 * For DMA mode:
844 *
845 * Set the Tx trigger to 16. This should match the DMA burst size that
846 * programmed in the DMA registers.
847 */
848 tup->fcr_shadow = UART_FCR_ENABLE_FIFO;
849 tup->fcr_shadow |= UART_FCR_R_TRIG_01;
850 tup->fcr_shadow |= TEGRA_UART_TX_TRIG_16B;
851 tegra_uart_write(tup, tup->fcr_shadow, UART_FCR);
852
853 /* Dummy read to ensure the write is posted */
854 tegra_uart_read(tup, UART_SCR);
855
856 /*
857 * For all tegra devices (up to t210), there is a hardware issue that
858 * requires software to wait for 3 UART clock periods after enabling
859 * the TX fifo, otherwise data could be lost.
860 */
861 tegra_uart_wait_cycle_time(tup, 3);
862
863 /*
864 * Initialize the UART with default configuration
865 * (115200, N, 8, 1) so that the receive DMA buffer may be
866 * enqueued
867 */
868 tup->lcr_shadow = TEGRA_UART_DEFAULT_LSR;
869 tegra_set_baudrate(tup, TEGRA_UART_DEFAULT_BAUD);
870 tup->fcr_shadow |= UART_FCR_DMA_SELECT;
871 tegra_uart_write(tup, tup->fcr_shadow, UART_FCR);
872
873 ret = tegra_uart_start_rx_dma(tup);
874 if (ret < 0) {
875 dev_err(tup->uport.dev, "Not able to start Rx DMA\n");
876 return ret;
877 }
878 tup->rx_in_progress = 1;
879
880 /*
881 * Enable IE_RXS for the receive status interrupts like line errros.
882 * Enable IE_RX_TIMEOUT to get the bytes which cannot be DMA'd.
883 *
884 * If using DMA mode, enable EORD instead of receive interrupt which
885 * will interrupt after the UART is done with the receive instead of
886 * the interrupt when the FIFO "threshold" is reached.
887 *
888 * EORD is different interrupt than RX_TIMEOUT - RX_TIMEOUT occurs when
889 * the DATA is sitting in the FIFO and couldn't be transferred to the
890 * DMA as the DMA size alignment (4 bytes) is not met. EORD will be
891 * triggered when there is a pause of the incomming data stream for 4
892 * characters long.
893 *
894 * For pauses in the data which is not aligned to 4 bytes, we get
895 * both the EORD as well as RX_TIMEOUT - SW sees RX_TIMEOUT first
896 * then the EORD.
897 */
898 tup->ier_shadow = UART_IER_RLSI | UART_IER_RTOIE | TEGRA_UART_IER_EORD;
899 tegra_uart_write(tup, tup->ier_shadow, UART_IER);
900 return 0;
901 }
902
903 static void tegra_uart_dma_channel_free(struct tegra_uart_port *tup,
904 bool dma_to_memory)
905 {
906 if (dma_to_memory) {
907 dmaengine_terminate_all(tup->rx_dma_chan);
908 dma_release_channel(tup->rx_dma_chan);
909 dma_free_coherent(tup->uport.dev, TEGRA_UART_RX_DMA_BUFFER_SIZE,
910 tup->rx_dma_buf_virt, tup->rx_dma_buf_phys);
911 tup->rx_dma_chan = NULL;
912 tup->rx_dma_buf_phys = 0;
913 tup->rx_dma_buf_virt = NULL;
914 } else {
915 dmaengine_terminate_all(tup->tx_dma_chan);
916 dma_release_channel(tup->tx_dma_chan);
917 dma_unmap_single(tup->uport.dev, tup->tx_dma_buf_phys,
918 UART_XMIT_SIZE, DMA_TO_DEVICE);
919 tup->tx_dma_chan = NULL;
920 tup->tx_dma_buf_phys = 0;
921 tup->tx_dma_buf_virt = NULL;
922 }
923 }
924
925 static int tegra_uart_dma_channel_allocate(struct tegra_uart_port *tup,
926 bool dma_to_memory)
927 {
928 struct dma_chan *dma_chan;
929 unsigned char *dma_buf;
930 dma_addr_t dma_phys;
931 int ret;
932 struct dma_slave_config dma_sconfig;
933
934 dma_chan = dma_request_slave_channel_reason(tup->uport.dev,
935 dma_to_memory ? "rx" : "tx");
936 if (IS_ERR(dma_chan)) {
937 ret = PTR_ERR(dma_chan);
938 dev_err(tup->uport.dev,
939 "DMA channel alloc failed: %d\n", ret);
940 return ret;
941 }
942
943 if (dma_to_memory) {
944 dma_buf = dma_alloc_coherent(tup->uport.dev,
945 TEGRA_UART_RX_DMA_BUFFER_SIZE,
946 &dma_phys, GFP_KERNEL);
947 if (!dma_buf) {
948 dev_err(tup->uport.dev,
949 "Not able to allocate the dma buffer\n");
950 dma_release_channel(dma_chan);
951 return -ENOMEM;
952 }
953 dma_sconfig.src_addr = tup->uport.mapbase;
954 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
955 dma_sconfig.src_maxburst = 4;
956 tup->rx_dma_chan = dma_chan;
957 tup->rx_dma_buf_virt = dma_buf;
958 tup->rx_dma_buf_phys = dma_phys;
959 } else {
960 dma_phys = dma_map_single(tup->uport.dev,
961 tup->uport.state->xmit.buf, UART_XMIT_SIZE,
962 DMA_TO_DEVICE);
963 if (dma_mapping_error(tup->uport.dev, dma_phys)) {
964 dev_err(tup->uport.dev, "dma_map_single tx failed\n");
965 dma_release_channel(dma_chan);
966 return -ENOMEM;
967 }
968 dma_buf = tup->uport.state->xmit.buf;
969 dma_sconfig.dst_addr = tup->uport.mapbase;
970 dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
971 dma_sconfig.dst_maxburst = 16;
972 tup->tx_dma_chan = dma_chan;
973 tup->tx_dma_buf_virt = dma_buf;
974 tup->tx_dma_buf_phys = dma_phys;
975 }
976
977 ret = dmaengine_slave_config(dma_chan, &dma_sconfig);
978 if (ret < 0) {
979 dev_err(tup->uport.dev,
980 "Dma slave config failed, err = %d\n", ret);
981 tegra_uart_dma_channel_free(tup, dma_to_memory);
982 return ret;
983 }
984
985 return 0;
986 }
987
988 static int tegra_uart_startup(struct uart_port *u)
989 {
990 struct tegra_uart_port *tup = to_tegra_uport(u);
991 int ret;
992
993 ret = tegra_uart_dma_channel_allocate(tup, false);
994 if (ret < 0) {
995 dev_err(u->dev, "Tx Dma allocation failed, err = %d\n", ret);
996 return ret;
997 }
998
999 ret = tegra_uart_dma_channel_allocate(tup, true);
1000 if (ret < 0) {
1001 dev_err(u->dev, "Rx Dma allocation failed, err = %d\n", ret);
1002 goto fail_rx_dma;
1003 }
1004
1005 ret = tegra_uart_hw_init(tup);
1006 if (ret < 0) {
1007 dev_err(u->dev, "Uart HW init failed, err = %d\n", ret);
1008 goto fail_hw_init;
1009 }
1010
1011 ret = request_irq(u->irq, tegra_uart_isr, 0,
1012 dev_name(u->dev), tup);
1013 if (ret < 0) {
1014 dev_err(u->dev, "Failed to register ISR for IRQ %d\n", u->irq);
1015 goto fail_hw_init;
1016 }
1017 return 0;
1018
1019 fail_hw_init:
1020 tegra_uart_dma_channel_free(tup, true);
1021 fail_rx_dma:
1022 tegra_uart_dma_channel_free(tup, false);
1023 return ret;
1024 }
1025
1026 /*
1027 * Flush any TX data submitted for DMA and PIO. Called when the
1028 * TX circular buffer is reset.
1029 */
1030 static void tegra_uart_flush_buffer(struct uart_port *u)
1031 {
1032 struct tegra_uart_port *tup = to_tegra_uport(u);
1033
1034 tup->tx_bytes = 0;
1035 if (tup->tx_dma_chan)
1036 dmaengine_terminate_all(tup->tx_dma_chan);
1037 }
1038
1039 static void tegra_uart_shutdown(struct uart_port *u)
1040 {
1041 struct tegra_uart_port *tup = to_tegra_uport(u);
1042
1043 tegra_uart_hw_deinit(tup);
1044
1045 tup->rx_in_progress = 0;
1046 tup->tx_in_progress = 0;
1047
1048 tegra_uart_dma_channel_free(tup, true);
1049 tegra_uart_dma_channel_free(tup, false);
1050 free_irq(u->irq, tup);
1051 }
1052
1053 static void tegra_uart_enable_ms(struct uart_port *u)
1054 {
1055 struct tegra_uart_port *tup = to_tegra_uport(u);
1056
1057 if (tup->enable_modem_interrupt) {
1058 tup->ier_shadow |= UART_IER_MSI;
1059 tegra_uart_write(tup, tup->ier_shadow, UART_IER);
1060 }
1061 }
1062
1063 static void tegra_uart_set_termios(struct uart_port *u,
1064 struct ktermios *termios, struct ktermios *oldtermios)
1065 {
1066 struct tegra_uart_port *tup = to_tegra_uport(u);
1067 unsigned int baud;
1068 unsigned long flags;
1069 unsigned int lcr;
1070 int symb_bit = 1;
1071 struct clk *parent_clk = clk_get_parent(tup->uart_clk);
1072 unsigned long parent_clk_rate = clk_get_rate(parent_clk);
1073 int max_divider = (tup->cdata->support_clk_src_div) ? 0x7FFF : 0xFFFF;
1074
1075 max_divider *= 16;
1076 spin_lock_irqsave(&u->lock, flags);
1077
1078 /* Changing configuration, it is safe to stop any rx now */
1079 if (tup->rts_active)
1080 set_rts(tup, false);
1081
1082 /* Clear all interrupts as configuration is going to be changed */
1083 tegra_uart_write(tup, tup->ier_shadow | UART_IER_RDI, UART_IER);
1084 tegra_uart_read(tup, UART_IER);
1085 tegra_uart_write(tup, 0, UART_IER);
1086 tegra_uart_read(tup, UART_IER);
1087
1088 /* Parity */
1089 lcr = tup->lcr_shadow;
1090 lcr &= ~UART_LCR_PARITY;
1091
1092 /* CMSPAR isn't supported by this driver */
1093 termios->c_cflag &= ~CMSPAR;
1094
1095 if ((termios->c_cflag & PARENB) == PARENB) {
1096 symb_bit++;
1097 if (termios->c_cflag & PARODD) {
1098 lcr |= UART_LCR_PARITY;
1099 lcr &= ~UART_LCR_EPAR;
1100 lcr &= ~UART_LCR_SPAR;
1101 } else {
1102 lcr |= UART_LCR_PARITY;
1103 lcr |= UART_LCR_EPAR;
1104 lcr &= ~UART_LCR_SPAR;
1105 }
1106 }
1107
1108 lcr &= ~UART_LCR_WLEN8;
1109 switch (termios->c_cflag & CSIZE) {
1110 case CS5:
1111 lcr |= UART_LCR_WLEN5;
1112 symb_bit += 5;
1113 break;
1114 case CS6:
1115 lcr |= UART_LCR_WLEN6;
1116 symb_bit += 6;
1117 break;
1118 case CS7:
1119 lcr |= UART_LCR_WLEN7;
1120 symb_bit += 7;
1121 break;
1122 default:
1123 lcr |= UART_LCR_WLEN8;
1124 symb_bit += 8;
1125 break;
1126 }
1127
1128 /* Stop bits */
1129 if (termios->c_cflag & CSTOPB) {
1130 lcr |= UART_LCR_STOP;
1131 symb_bit += 2;
1132 } else {
1133 lcr &= ~UART_LCR_STOP;
1134 symb_bit++;
1135 }
1136
1137 tegra_uart_write(tup, lcr, UART_LCR);
1138 tup->lcr_shadow = lcr;
1139 tup->symb_bit = symb_bit;
1140
1141 /* Baud rate. */
1142 baud = uart_get_baud_rate(u, termios, oldtermios,
1143 parent_clk_rate/max_divider,
1144 parent_clk_rate/16);
1145 spin_unlock_irqrestore(&u->lock, flags);
1146 tegra_set_baudrate(tup, baud);
1147 if (tty_termios_baud_rate(termios))
1148 tty_termios_encode_baud_rate(termios, baud, baud);
1149 spin_lock_irqsave(&u->lock, flags);
1150
1151 /* Flow control */
1152 if (termios->c_cflag & CRTSCTS) {
1153 tup->mcr_shadow |= TEGRA_UART_MCR_CTS_EN;
1154 tup->mcr_shadow &= ~TEGRA_UART_MCR_RTS_EN;
1155 tegra_uart_write(tup, tup->mcr_shadow, UART_MCR);
1156 /* if top layer has asked to set rts active then do so here */
1157 if (tup->rts_active)
1158 set_rts(tup, true);
1159 } else {
1160 tup->mcr_shadow &= ~TEGRA_UART_MCR_CTS_EN;
1161 tup->mcr_shadow &= ~TEGRA_UART_MCR_RTS_EN;
1162 tegra_uart_write(tup, tup->mcr_shadow, UART_MCR);
1163 }
1164
1165 /* update the port timeout based on new settings */
1166 uart_update_timeout(u, termios->c_cflag, baud);
1167
1168 /* Make sure all writes have completed */
1169 tegra_uart_read(tup, UART_IER);
1170
1171 /* Re-enable interrupt */
1172 tegra_uart_write(tup, tup->ier_shadow, UART_IER);
1173 tegra_uart_read(tup, UART_IER);
1174
1175 spin_unlock_irqrestore(&u->lock, flags);
1176 }
1177
1178 static const char *tegra_uart_type(struct uart_port *u)
1179 {
1180 return TEGRA_UART_TYPE;
1181 }
1182
1183 static const struct uart_ops tegra_uart_ops = {
1184 .tx_empty = tegra_uart_tx_empty,
1185 .set_mctrl = tegra_uart_set_mctrl,
1186 .get_mctrl = tegra_uart_get_mctrl,
1187 .stop_tx = tegra_uart_stop_tx,
1188 .start_tx = tegra_uart_start_tx,
1189 .stop_rx = tegra_uart_stop_rx,
1190 .flush_buffer = tegra_uart_flush_buffer,
1191 .enable_ms = tegra_uart_enable_ms,
1192 .break_ctl = tegra_uart_break_ctl,
1193 .startup = tegra_uart_startup,
1194 .shutdown = tegra_uart_shutdown,
1195 .set_termios = tegra_uart_set_termios,
1196 .type = tegra_uart_type,
1197 .request_port = tegra_uart_request_port,
1198 .release_port = tegra_uart_release_port,
1199 };
1200
1201 static struct uart_driver tegra_uart_driver = {
1202 .owner = THIS_MODULE,
1203 .driver_name = "tegra_hsuart",
1204 .dev_name = "ttyTHS",
1205 .cons = NULL,
1206 .nr = TEGRA_UART_MAXIMUM,
1207 };
1208
1209 static int tegra_uart_parse_dt(struct platform_device *pdev,
1210 struct tegra_uart_port *tup)
1211 {
1212 struct device_node *np = pdev->dev.of_node;
1213 int port;
1214
1215 port = of_alias_get_id(np, "serial");
1216 if (port < 0) {
1217 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", port);
1218 return port;
1219 }
1220 tup->uport.line = port;
1221
1222 tup->enable_modem_interrupt = of_property_read_bool(np,
1223 "nvidia,enable-modem-interrupt");
1224 return 0;
1225 }
1226
1227 static struct tegra_uart_chip_data tegra20_uart_chip_data = {
1228 .tx_fifo_full_status = false,
1229 .allow_txfifo_reset_fifo_mode = true,
1230 .support_clk_src_div = false,
1231 };
1232
1233 static struct tegra_uart_chip_data tegra30_uart_chip_data = {
1234 .tx_fifo_full_status = true,
1235 .allow_txfifo_reset_fifo_mode = false,
1236 .support_clk_src_div = true,
1237 };
1238
1239 static const struct of_device_id tegra_uart_of_match[] = {
1240 {
1241 .compatible = "nvidia,tegra30-hsuart",
1242 .data = &tegra30_uart_chip_data,
1243 }, {
1244 .compatible = "nvidia,tegra20-hsuart",
1245 .data = &tegra20_uart_chip_data,
1246 }, {
1247 },
1248 };
1249 MODULE_DEVICE_TABLE(of, tegra_uart_of_match);
1250
1251 static int tegra_uart_probe(struct platform_device *pdev)
1252 {
1253 struct tegra_uart_port *tup;
1254 struct uart_port *u;
1255 struct resource *resource;
1256 int ret;
1257 const struct tegra_uart_chip_data *cdata;
1258 const struct of_device_id *match;
1259
1260 match = of_match_device(tegra_uart_of_match, &pdev->dev);
1261 if (!match) {
1262 dev_err(&pdev->dev, "Error: No device match found\n");
1263 return -ENODEV;
1264 }
1265 cdata = match->data;
1266
1267 tup = devm_kzalloc(&pdev->dev, sizeof(*tup), GFP_KERNEL);
1268 if (!tup) {
1269 dev_err(&pdev->dev, "Failed to allocate memory for tup\n");
1270 return -ENOMEM;
1271 }
1272
1273 ret = tegra_uart_parse_dt(pdev, tup);
1274 if (ret < 0)
1275 return ret;
1276
1277 u = &tup->uport;
1278 u->dev = &pdev->dev;
1279 u->ops = &tegra_uart_ops;
1280 u->type = PORT_TEGRA;
1281 u->fifosize = 32;
1282 tup->cdata = cdata;
1283
1284 platform_set_drvdata(pdev, tup);
1285 resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1286 if (!resource) {
1287 dev_err(&pdev->dev, "No IO memory resource\n");
1288 return -ENODEV;
1289 }
1290
1291 u->mapbase = resource->start;
1292 u->membase = devm_ioremap_resource(&pdev->dev, resource);
1293 if (IS_ERR(u->membase))
1294 return PTR_ERR(u->membase);
1295
1296 tup->uart_clk = devm_clk_get(&pdev->dev, NULL);
1297 if (IS_ERR(tup->uart_clk)) {
1298 dev_err(&pdev->dev, "Couldn't get the clock\n");
1299 return PTR_ERR(tup->uart_clk);
1300 }
1301
1302 tup->rst = devm_reset_control_get_exclusive(&pdev->dev, "serial");
1303 if (IS_ERR(tup->rst)) {
1304 dev_err(&pdev->dev, "Couldn't get the reset\n");
1305 return PTR_ERR(tup->rst);
1306 }
1307
1308 u->iotype = UPIO_MEM32;
1309 ret = platform_get_irq(pdev, 0);
1310 if (ret < 0) {
1311 dev_err(&pdev->dev, "Couldn't get IRQ\n");
1312 return ret;
1313 }
1314 u->irq = ret;
1315 u->regshift = 2;
1316 ret = uart_add_one_port(&tegra_uart_driver, u);
1317 if (ret < 0) {
1318 dev_err(&pdev->dev, "Failed to add uart port, err %d\n", ret);
1319 return ret;
1320 }
1321 return ret;
1322 }
1323
1324 static int tegra_uart_remove(struct platform_device *pdev)
1325 {
1326 struct tegra_uart_port *tup = platform_get_drvdata(pdev);
1327 struct uart_port *u = &tup->uport;
1328
1329 uart_remove_one_port(&tegra_uart_driver, u);
1330 return 0;
1331 }
1332
1333 #ifdef CONFIG_PM_SLEEP
1334 static int tegra_uart_suspend(struct device *dev)
1335 {
1336 struct tegra_uart_port *tup = dev_get_drvdata(dev);
1337 struct uart_port *u = &tup->uport;
1338
1339 return uart_suspend_port(&tegra_uart_driver, u);
1340 }
1341
1342 static int tegra_uart_resume(struct device *dev)
1343 {
1344 struct tegra_uart_port *tup = dev_get_drvdata(dev);
1345 struct uart_port *u = &tup->uport;
1346
1347 return uart_resume_port(&tegra_uart_driver, u);
1348 }
1349 #endif
1350
1351 static const struct dev_pm_ops tegra_uart_pm_ops = {
1352 SET_SYSTEM_SLEEP_PM_OPS(tegra_uart_suspend, tegra_uart_resume)
1353 };
1354
1355 static struct platform_driver tegra_uart_platform_driver = {
1356 .probe = tegra_uart_probe,
1357 .remove = tegra_uart_remove,
1358 .driver = {
1359 .name = "serial-tegra",
1360 .of_match_table = tegra_uart_of_match,
1361 .pm = &tegra_uart_pm_ops,
1362 },
1363 };
1364
1365 static int __init tegra_uart_init(void)
1366 {
1367 int ret;
1368
1369 ret = uart_register_driver(&tegra_uart_driver);
1370 if (ret < 0) {
1371 pr_err("Could not register %s driver\n",
1372 tegra_uart_driver.driver_name);
1373 return ret;
1374 }
1375
1376 ret = platform_driver_register(&tegra_uart_platform_driver);
1377 if (ret < 0) {
1378 pr_err("Uart platform driver register failed, e = %d\n", ret);
1379 uart_unregister_driver(&tegra_uart_driver);
1380 return ret;
1381 }
1382 return 0;
1383 }
1384
1385 static void __exit tegra_uart_exit(void)
1386 {
1387 pr_info("Unloading tegra uart driver\n");
1388 platform_driver_unregister(&tegra_uart_platform_driver);
1389 uart_unregister_driver(&tegra_uart_driver);
1390 }
1391
1392 module_init(tegra_uart_init);
1393 module_exit(tegra_uart_exit);
1394
1395 MODULE_ALIAS("platform:serial-tegra");
1396 MODULE_DESCRIPTION("High speed UART driver for tegra chipset");
1397 MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
1398 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support