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staging: erofs: integrate decompression inplace
[linux/fpc-iii.git] / drivers / tty / serial / sh-sci.c
blobabc705716aa094fde652c3bc77c18210a5b8b280
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
4 *
5 * Copyright (C) 2002 - 2011 Paul Mundt
6 * Copyright (C) 2015 Glider bvba
7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
8 *
9 * based off of the old drivers/char/sh-sci.c by:
10 *
11 * Copyright (C) 1999, 2000 Niibe Yutaka
12 * Copyright (C) 2000 Sugioka Toshinobu
13 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
14 * Modified to support SecureEdge. David McCullough (2002)
15 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
16 * Removed SH7300 support (Jul 2007).
17 */
18 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
19 #define SUPPORT_SYSRQ
20 #endif
21
22 #undef DEBUG
23
24 #include <linux/clk.h>
25 #include <linux/console.h>
26 #include <linux/ctype.h>
27 #include <linux/cpufreq.h>
28 #include <linux/delay.h>
29 #include <linux/dmaengine.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/err.h>
32 #include <linux/errno.h>
33 #include <linux/init.h>
34 #include <linux/interrupt.h>
35 #include <linux/ioport.h>
36 #include <linux/ktime.h>
37 #include <linux/major.h>
38 #include <linux/module.h>
39 #include <linux/mm.h>
40 #include <linux/of.h>
41 #include <linux/of_device.h>
42 #include <linux/platform_device.h>
43 #include <linux/pm_runtime.h>
44 #include <linux/scatterlist.h>
45 #include <linux/serial.h>
46 #include <linux/serial_sci.h>
47 #include <linux/sh_dma.h>
48 #include <linux/slab.h>
49 #include <linux/string.h>
50 #include <linux/sysrq.h>
51 #include <linux/timer.h>
52 #include <linux/tty.h>
53 #include <linux/tty_flip.h>
54
55 #ifdef CONFIG_SUPERH
56 #include <asm/sh_bios.h>
57 #endif
58
59 #include "serial_mctrl_gpio.h"
60 #include "sh-sci.h"
61
62 /* Offsets into the sci_port->irqs array */
63 enum {
64 SCIx_ERI_IRQ,
65 SCIx_RXI_IRQ,
66 SCIx_TXI_IRQ,
67 SCIx_BRI_IRQ,
68 SCIx_DRI_IRQ,
69 SCIx_TEI_IRQ,
70 SCIx_NR_IRQS,
71
72 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
73 };
74
75 #define SCIx_IRQ_IS_MUXED(port) \
76 ((port)->irqs[SCIx_ERI_IRQ] == \
77 (port)->irqs[SCIx_RXI_IRQ]) || \
78 ((port)->irqs[SCIx_ERI_IRQ] && \
79 ((port)->irqs[SCIx_RXI_IRQ] < 0))
80
81 enum SCI_CLKS {
82 SCI_FCK, /* Functional Clock */
83 SCI_SCK, /* Optional External Clock */
84 SCI_BRG_INT, /* Optional BRG Internal Clock Source */
85 SCI_SCIF_CLK, /* Optional BRG External Clock Source */
86 SCI_NUM_CLKS
87 };
88
89 /* Bit x set means sampling rate x + 1 is supported */
90 #define SCI_SR(x) BIT((x) - 1)
91 #define SCI_SR_RANGE(x, y) GENMASK((y) - 1, (x) - 1)
92
93 #define SCI_SR_SCIFAB SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \
94 SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \
95 SCI_SR(19) | SCI_SR(27)
96
97 #define min_sr(_port) ffs((_port)->sampling_rate_mask)
98 #define max_sr(_port) fls((_port)->sampling_rate_mask)
99
100 /* Iterate over all supported sampling rates, from high to low */
101 #define for_each_sr(_sr, _port) \
102 for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \
103 if ((_port)->sampling_rate_mask & SCI_SR((_sr)))
104
105 struct plat_sci_reg {
106 u8 offset, size;
107 };
108
109 struct sci_port_params {
110 const struct plat_sci_reg regs[SCIx_NR_REGS];
111 unsigned int fifosize;
112 unsigned int overrun_reg;
113 unsigned int overrun_mask;
114 unsigned int sampling_rate_mask;
115 unsigned int error_mask;
116 unsigned int error_clear;
117 };
118
119 struct sci_port {
120 struct uart_port port;
121
122 /* Platform configuration */
123 const struct sci_port_params *params;
124 const struct plat_sci_port *cfg;
125 unsigned int sampling_rate_mask;
126 resource_size_t reg_size;
127 struct mctrl_gpios *gpios;
128
129 /* Clocks */
130 struct clk *clks[SCI_NUM_CLKS];
131 unsigned long clk_rates[SCI_NUM_CLKS];
132
133 int irqs[SCIx_NR_IRQS];
134 char *irqstr[SCIx_NR_IRQS];
135
136 struct dma_chan *chan_tx;
137 struct dma_chan *chan_rx;
138
139 #ifdef CONFIG_SERIAL_SH_SCI_DMA
140 struct dma_chan *chan_tx_saved;
141 struct dma_chan *chan_rx_saved;
142 dma_cookie_t cookie_tx;
143 dma_cookie_t cookie_rx[2];
144 dma_cookie_t active_rx;
145 dma_addr_t tx_dma_addr;
146 unsigned int tx_dma_len;
147 struct scatterlist sg_rx[2];
148 void *rx_buf[2];
149 size_t buf_len_rx;
150 struct work_struct work_tx;
151 struct hrtimer rx_timer;
152 unsigned int rx_timeout; /* microseconds */
153 #endif
154 unsigned int rx_frame;
155 int rx_trigger;
156 struct timer_list rx_fifo_timer;
157 int rx_fifo_timeout;
158 u16 hscif_tot;
159
160 bool has_rtscts;
161 bool autorts;
162 };
163
164 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
165
166 static struct sci_port sci_ports[SCI_NPORTS];
167 static unsigned long sci_ports_in_use;
168 static struct uart_driver sci_uart_driver;
169
170 static inline struct sci_port *
171 to_sci_port(struct uart_port *uart)
172 {
173 return container_of(uart, struct sci_port, port);
174 }
175
176 static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
177 /*
178 * Common SCI definitions, dependent on the port's regshift
179 * value.
180 */
181 [SCIx_SCI_REGTYPE] = {
182 .regs = {
183 [SCSMR] = { 0x00, 8 },
184 [SCBRR] = { 0x01, 8 },
185 [SCSCR] = { 0x02, 8 },
186 [SCxTDR] = { 0x03, 8 },
187 [SCxSR] = { 0x04, 8 },
188 [SCxRDR] = { 0x05, 8 },
189 },
190 .fifosize = 1,
191 .overrun_reg = SCxSR,
192 .overrun_mask = SCI_ORER,
193 .sampling_rate_mask = SCI_SR(32),
194 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
195 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
196 },
197
198 /*
199 * Common definitions for legacy IrDA ports.
200 */
201 [SCIx_IRDA_REGTYPE] = {
202 .regs = {
203 [SCSMR] = { 0x00, 8 },
204 [SCBRR] = { 0x02, 8 },
205 [SCSCR] = { 0x04, 8 },
206 [SCxTDR] = { 0x06, 8 },
207 [SCxSR] = { 0x08, 16 },
208 [SCxRDR] = { 0x0a, 8 },
209 [SCFCR] = { 0x0c, 8 },
210 [SCFDR] = { 0x0e, 16 },
211 },
212 .fifosize = 1,
213 .overrun_reg = SCxSR,
214 .overrun_mask = SCI_ORER,
215 .sampling_rate_mask = SCI_SR(32),
216 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
217 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
218 },
219
220 /*
221 * Common SCIFA definitions.
222 */
223 [SCIx_SCIFA_REGTYPE] = {
224 .regs = {
225 [SCSMR] = { 0x00, 16 },
226 [SCBRR] = { 0x04, 8 },
227 [SCSCR] = { 0x08, 16 },
228 [SCxTDR] = { 0x20, 8 },
229 [SCxSR] = { 0x14, 16 },
230 [SCxRDR] = { 0x24, 8 },
231 [SCFCR] = { 0x18, 16 },
232 [SCFDR] = { 0x1c, 16 },
233 [SCPCR] = { 0x30, 16 },
234 [SCPDR] = { 0x34, 16 },
235 },
236 .fifosize = 64,
237 .overrun_reg = SCxSR,
238 .overrun_mask = SCIFA_ORER,
239 .sampling_rate_mask = SCI_SR_SCIFAB,
240 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
241 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
242 },
243
244 /*
245 * Common SCIFB definitions.
246 */
247 [SCIx_SCIFB_REGTYPE] = {
248 .regs = {
249 [SCSMR] = { 0x00, 16 },
250 [SCBRR] = { 0x04, 8 },
251 [SCSCR] = { 0x08, 16 },
252 [SCxTDR] = { 0x40, 8 },
253 [SCxSR] = { 0x14, 16 },
254 [SCxRDR] = { 0x60, 8 },
255 [SCFCR] = { 0x18, 16 },
256 [SCTFDR] = { 0x38, 16 },
257 [SCRFDR] = { 0x3c, 16 },
258 [SCPCR] = { 0x30, 16 },
259 [SCPDR] = { 0x34, 16 },
260 },
261 .fifosize = 256,
262 .overrun_reg = SCxSR,
263 .overrun_mask = SCIFA_ORER,
264 .sampling_rate_mask = SCI_SR_SCIFAB,
265 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
266 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
267 },
268
269 /*
270 * Common SH-2(A) SCIF definitions for ports with FIFO data
271 * count registers.
272 */
273 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
274 .regs = {
275 [SCSMR] = { 0x00, 16 },
276 [SCBRR] = { 0x04, 8 },
277 [SCSCR] = { 0x08, 16 },
278 [SCxTDR] = { 0x0c, 8 },
279 [SCxSR] = { 0x10, 16 },
280 [SCxRDR] = { 0x14, 8 },
281 [SCFCR] = { 0x18, 16 },
282 [SCFDR] = { 0x1c, 16 },
283 [SCSPTR] = { 0x20, 16 },
284 [SCLSR] = { 0x24, 16 },
285 },
286 .fifosize = 16,
287 .overrun_reg = SCLSR,
288 .overrun_mask = SCLSR_ORER,
289 .sampling_rate_mask = SCI_SR(32),
290 .error_mask = SCIF_DEFAULT_ERROR_MASK,
291 .error_clear = SCIF_ERROR_CLEAR,
292 },
293
294 /*
295 * The "SCIFA" that is in RZ/T and RZ/A2.
296 * It looks like a normal SCIF with FIFO data, but with a
297 * compressed address space. Also, the break out of interrupts
298 * are different: ERI/BRI, RXI, TXI, TEI, DRI.
299 */
300 [SCIx_RZ_SCIFA_REGTYPE] = {
301 .regs = {
302 [SCSMR] = { 0x00, 16 },
303 [SCBRR] = { 0x02, 8 },
304 [SCSCR] = { 0x04, 16 },
305 [SCxTDR] = { 0x06, 8 },
306 [SCxSR] = { 0x08, 16 },
307 [SCxRDR] = { 0x0A, 8 },
308 [SCFCR] = { 0x0C, 16 },
309 [SCFDR] = { 0x0E, 16 },
310 [SCSPTR] = { 0x10, 16 },
311 [SCLSR] = { 0x12, 16 },
312 },
313 .fifosize = 16,
314 .overrun_reg = SCLSR,
315 .overrun_mask = SCLSR_ORER,
316 .sampling_rate_mask = SCI_SR(32),
317 .error_mask = SCIF_DEFAULT_ERROR_MASK,
318 .error_clear = SCIF_ERROR_CLEAR,
319 },
320
321 /*
322 * Common SH-3 SCIF definitions.
323 */
324 [SCIx_SH3_SCIF_REGTYPE] = {
325 .regs = {
326 [SCSMR] = { 0x00, 8 },
327 [SCBRR] = { 0x02, 8 },
328 [SCSCR] = { 0x04, 8 },
329 [SCxTDR] = { 0x06, 8 },
330 [SCxSR] = { 0x08, 16 },
331 [SCxRDR] = { 0x0a, 8 },
332 [SCFCR] = { 0x0c, 8 },
333 [SCFDR] = { 0x0e, 16 },
334 },
335 .fifosize = 16,
336 .overrun_reg = SCLSR,
337 .overrun_mask = SCLSR_ORER,
338 .sampling_rate_mask = SCI_SR(32),
339 .error_mask = SCIF_DEFAULT_ERROR_MASK,
340 .error_clear = SCIF_ERROR_CLEAR,
341 },
342
343 /*
344 * Common SH-4(A) SCIF(B) definitions.
345 */
346 [SCIx_SH4_SCIF_REGTYPE] = {
347 .regs = {
348 [SCSMR] = { 0x00, 16 },
349 [SCBRR] = { 0x04, 8 },
350 [SCSCR] = { 0x08, 16 },
351 [SCxTDR] = { 0x0c, 8 },
352 [SCxSR] = { 0x10, 16 },
353 [SCxRDR] = { 0x14, 8 },
354 [SCFCR] = { 0x18, 16 },
355 [SCFDR] = { 0x1c, 16 },
356 [SCSPTR] = { 0x20, 16 },
357 [SCLSR] = { 0x24, 16 },
358 },
359 .fifosize = 16,
360 .overrun_reg = SCLSR,
361 .overrun_mask = SCLSR_ORER,
362 .sampling_rate_mask = SCI_SR(32),
363 .error_mask = SCIF_DEFAULT_ERROR_MASK,
364 .error_clear = SCIF_ERROR_CLEAR,
365 },
366
367 /*
368 * Common SCIF definitions for ports with a Baud Rate Generator for
369 * External Clock (BRG).
370 */
371 [SCIx_SH4_SCIF_BRG_REGTYPE] = {
372 .regs = {
373 [SCSMR] = { 0x00, 16 },
374 [SCBRR] = { 0x04, 8 },
375 [SCSCR] = { 0x08, 16 },
376 [SCxTDR] = { 0x0c, 8 },
377 [SCxSR] = { 0x10, 16 },
378 [SCxRDR] = { 0x14, 8 },
379 [SCFCR] = { 0x18, 16 },
380 [SCFDR] = { 0x1c, 16 },
381 [SCSPTR] = { 0x20, 16 },
382 [SCLSR] = { 0x24, 16 },
383 [SCDL] = { 0x30, 16 },
384 [SCCKS] = { 0x34, 16 },
385 },
386 .fifosize = 16,
387 .overrun_reg = SCLSR,
388 .overrun_mask = SCLSR_ORER,
389 .sampling_rate_mask = SCI_SR(32),
390 .error_mask = SCIF_DEFAULT_ERROR_MASK,
391 .error_clear = SCIF_ERROR_CLEAR,
392 },
393
394 /*
395 * Common HSCIF definitions.
396 */
397 [SCIx_HSCIF_REGTYPE] = {
398 .regs = {
399 [SCSMR] = { 0x00, 16 },
400 [SCBRR] = { 0x04, 8 },
401 [SCSCR] = { 0x08, 16 },
402 [SCxTDR] = { 0x0c, 8 },
403 [SCxSR] = { 0x10, 16 },
404 [SCxRDR] = { 0x14, 8 },
405 [SCFCR] = { 0x18, 16 },
406 [SCFDR] = { 0x1c, 16 },
407 [SCSPTR] = { 0x20, 16 },
408 [SCLSR] = { 0x24, 16 },
409 [HSSRR] = { 0x40, 16 },
410 [SCDL] = { 0x30, 16 },
411 [SCCKS] = { 0x34, 16 },
412 [HSRTRGR] = { 0x54, 16 },
413 [HSTTRGR] = { 0x58, 16 },
414 },
415 .fifosize = 128,
416 .overrun_reg = SCLSR,
417 .overrun_mask = SCLSR_ORER,
418 .sampling_rate_mask = SCI_SR_RANGE(8, 32),
419 .error_mask = SCIF_DEFAULT_ERROR_MASK,
420 .error_clear = SCIF_ERROR_CLEAR,
421 },
422
423 /*
424 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
425 * register.
426 */
427 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
428 .regs = {
429 [SCSMR] = { 0x00, 16 },
430 [SCBRR] = { 0x04, 8 },
431 [SCSCR] = { 0x08, 16 },
432 [SCxTDR] = { 0x0c, 8 },
433 [SCxSR] = { 0x10, 16 },
434 [SCxRDR] = { 0x14, 8 },
435 [SCFCR] = { 0x18, 16 },
436 [SCFDR] = { 0x1c, 16 },
437 [SCLSR] = { 0x24, 16 },
438 },
439 .fifosize = 16,
440 .overrun_reg = SCLSR,
441 .overrun_mask = SCLSR_ORER,
442 .sampling_rate_mask = SCI_SR(32),
443 .error_mask = SCIF_DEFAULT_ERROR_MASK,
444 .error_clear = SCIF_ERROR_CLEAR,
445 },
446
447 /*
448 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
449 * count registers.
450 */
451 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
452 .regs = {
453 [SCSMR] = { 0x00, 16 },
454 [SCBRR] = { 0x04, 8 },
455 [SCSCR] = { 0x08, 16 },
456 [SCxTDR] = { 0x0c, 8 },
457 [SCxSR] = { 0x10, 16 },
458 [SCxRDR] = { 0x14, 8 },
459 [SCFCR] = { 0x18, 16 },
460 [SCFDR] = { 0x1c, 16 },
461 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
462 [SCRFDR] = { 0x20, 16 },
463 [SCSPTR] = { 0x24, 16 },
464 [SCLSR] = { 0x28, 16 },
465 },
466 .fifosize = 16,
467 .overrun_reg = SCLSR,
468 .overrun_mask = SCLSR_ORER,
469 .sampling_rate_mask = SCI_SR(32),
470 .error_mask = SCIF_DEFAULT_ERROR_MASK,
471 .error_clear = SCIF_ERROR_CLEAR,
472 },
473
474 /*
475 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
476 * registers.
477 */
478 [SCIx_SH7705_SCIF_REGTYPE] = {
479 .regs = {
480 [SCSMR] = { 0x00, 16 },
481 [SCBRR] = { 0x04, 8 },
482 [SCSCR] = { 0x08, 16 },
483 [SCxTDR] = { 0x20, 8 },
484 [SCxSR] = { 0x14, 16 },
485 [SCxRDR] = { 0x24, 8 },
486 [SCFCR] = { 0x18, 16 },
487 [SCFDR] = { 0x1c, 16 },
488 },
489 .fifosize = 64,
490 .overrun_reg = SCxSR,
491 .overrun_mask = SCIFA_ORER,
492 .sampling_rate_mask = SCI_SR(16),
493 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
494 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
495 },
496 };
497
498 #define sci_getreg(up, offset) (&to_sci_port(up)->params->regs[offset])
499
500 /*
501 * The "offset" here is rather misleading, in that it refers to an enum
502 * value relative to the port mapping rather than the fixed offset
503 * itself, which needs to be manually retrieved from the platform's
504 * register map for the given port.
505 */
506 static unsigned int sci_serial_in(struct uart_port *p, int offset)
507 {
508 const struct plat_sci_reg *reg = sci_getreg(p, offset);
509
510 if (reg->size == 8)
511 return ioread8(p->membase + (reg->offset << p->regshift));
512 else if (reg->size == 16)
513 return ioread16(p->membase + (reg->offset << p->regshift));
514 else
515 WARN(1, "Invalid register access\n");
516
517 return 0;
518 }
519
520 static void sci_serial_out(struct uart_port *p, int offset, int value)
521 {
522 const struct plat_sci_reg *reg = sci_getreg(p, offset);
523
524 if (reg->size == 8)
525 iowrite8(value, p->membase + (reg->offset << p->regshift));
526 else if (reg->size == 16)
527 iowrite16(value, p->membase + (reg->offset << p->regshift));
528 else
529 WARN(1, "Invalid register access\n");
530 }
531
532 static void sci_port_enable(struct sci_port *sci_port)
533 {
534 unsigned int i;
535
536 if (!sci_port->port.dev)
537 return;
538
539 pm_runtime_get_sync(sci_port->port.dev);
540
541 for (i = 0; i < SCI_NUM_CLKS; i++) {
542 clk_prepare_enable(sci_port->clks[i]);
543 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]);
544 }
545 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK];
546 }
547
548 static void sci_port_disable(struct sci_port *sci_port)
549 {
550 unsigned int i;
551
552 if (!sci_port->port.dev)
553 return;
554
555 for (i = SCI_NUM_CLKS; i-- > 0; )
556 clk_disable_unprepare(sci_port->clks[i]);
557
558 pm_runtime_put_sync(sci_port->port.dev);
559 }
560
561 static inline unsigned long port_rx_irq_mask(struct uart_port *port)
562 {
563 /*
564 * Not all ports (such as SCIFA) will support REIE. Rather than
565 * special-casing the port type, we check the port initialization
566 * IRQ enable mask to see whether the IRQ is desired at all. If
567 * it's unset, it's logically inferred that there's no point in
568 * testing for it.
569 */
570 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
571 }
572
573 static void sci_start_tx(struct uart_port *port)
574 {
575 struct sci_port *s = to_sci_port(port);
576 unsigned short ctrl;
577
578 #ifdef CONFIG_SERIAL_SH_SCI_DMA
579 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
580 u16 new, scr = serial_port_in(port, SCSCR);
581 if (s->chan_tx)
582 new = scr | SCSCR_TDRQE;
583 else
584 new = scr & ~SCSCR_TDRQE;
585 if (new != scr)
586 serial_port_out(port, SCSCR, new);
587 }
588
589 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
590 dma_submit_error(s->cookie_tx)) {
591 s->cookie_tx = 0;
592 schedule_work(&s->work_tx);
593 }
594 #endif
595
596 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
597 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
598 ctrl = serial_port_in(port, SCSCR);
599 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
600 }
601 }
602
603 static void sci_stop_tx(struct uart_port *port)
604 {
605 unsigned short ctrl;
606
607 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
608 ctrl = serial_port_in(port, SCSCR);
609
610 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
611 ctrl &= ~SCSCR_TDRQE;
612
613 ctrl &= ~SCSCR_TIE;
614
615 serial_port_out(port, SCSCR, ctrl);
616 }
617
618 static void sci_start_rx(struct uart_port *port)
619 {
620 unsigned short ctrl;
621
622 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
623
624 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
625 ctrl &= ~SCSCR_RDRQE;
626
627 serial_port_out(port, SCSCR, ctrl);
628 }
629
630 static void sci_stop_rx(struct uart_port *port)
631 {
632 unsigned short ctrl;
633
634 ctrl = serial_port_in(port, SCSCR);
635
636 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
637 ctrl &= ~SCSCR_RDRQE;
638
639 ctrl &= ~port_rx_irq_mask(port);
640
641 serial_port_out(port, SCSCR, ctrl);
642 }
643
644 static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
645 {
646 if (port->type == PORT_SCI) {
647 /* Just store the mask */
648 serial_port_out(port, SCxSR, mask);
649 } else if (to_sci_port(port)->params->overrun_mask == SCIFA_ORER) {
650 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */
651 /* Only clear the status bits we want to clear */
652 serial_port_out(port, SCxSR,
653 serial_port_in(port, SCxSR) & mask);
654 } else {
655 /* Store the mask, clear parity/framing errors */
656 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
657 }
658 }
659
660 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
661 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
662
663 #ifdef CONFIG_CONSOLE_POLL
664 static int sci_poll_get_char(struct uart_port *port)
665 {
666 unsigned short status;
667 int c;
668
669 do {
670 status = serial_port_in(port, SCxSR);
671 if (status & SCxSR_ERRORS(port)) {
672 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
673 continue;
674 }
675 break;
676 } while (1);
677
678 if (!(status & SCxSR_RDxF(port)))
679 return NO_POLL_CHAR;
680
681 c = serial_port_in(port, SCxRDR);
682
683 /* Dummy read */
684 serial_port_in(port, SCxSR);
685 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
686
687 return c;
688 }
689 #endif
690
691 static void sci_poll_put_char(struct uart_port *port, unsigned char c)
692 {
693 unsigned short status;
694
695 do {
696 status = serial_port_in(port, SCxSR);
697 } while (!(status & SCxSR_TDxE(port)));
698
699 serial_port_out(port, SCxTDR, c);
700 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
701 }
702 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE ||
703 CONFIG_SERIAL_SH_SCI_EARLYCON */
704
705 static void sci_init_pins(struct uart_port *port, unsigned int cflag)
706 {
707 struct sci_port *s = to_sci_port(port);
708
709 /*
710 * Use port-specific handler if provided.
711 */
712 if (s->cfg->ops && s->cfg->ops->init_pins) {
713 s->cfg->ops->init_pins(port, cflag);
714 return;
715 }
716
717 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
718 u16 data = serial_port_in(port, SCPDR);
719 u16 ctrl = serial_port_in(port, SCPCR);
720
721 /* Enable RXD and TXD pin functions */
722 ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC);
723 if (to_sci_port(port)->has_rtscts) {
724 /* RTS# is output, active low, unless autorts */
725 if (!(port->mctrl & TIOCM_RTS)) {
726 ctrl |= SCPCR_RTSC;
727 data |= SCPDR_RTSD;
728 } else if (!s->autorts) {
729 ctrl |= SCPCR_RTSC;
730 data &= ~SCPDR_RTSD;
731 } else {
732 /* Enable RTS# pin function */
733 ctrl &= ~SCPCR_RTSC;
734 }
735 /* Enable CTS# pin function */
736 ctrl &= ~SCPCR_CTSC;
737 }
738 serial_port_out(port, SCPDR, data);
739 serial_port_out(port, SCPCR, ctrl);
740 } else if (sci_getreg(port, SCSPTR)->size) {
741 u16 status = serial_port_in(port, SCSPTR);
742
743 /* RTS# is always output; and active low, unless autorts */
744 status |= SCSPTR_RTSIO;
745 if (!(port->mctrl & TIOCM_RTS))
746 status |= SCSPTR_RTSDT;
747 else if (!s->autorts)
748 status &= ~SCSPTR_RTSDT;
749 /* CTS# and SCK are inputs */
750 status &= ~(SCSPTR_CTSIO | SCSPTR_SCKIO);
751 serial_port_out(port, SCSPTR, status);
752 }
753 }
754
755 static int sci_txfill(struct uart_port *port)
756 {
757 struct sci_port *s = to_sci_port(port);
758 unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
759 const struct plat_sci_reg *reg;
760
761 reg = sci_getreg(port, SCTFDR);
762 if (reg->size)
763 return serial_port_in(port, SCTFDR) & fifo_mask;
764
765 reg = sci_getreg(port, SCFDR);
766 if (reg->size)
767 return serial_port_in(port, SCFDR) >> 8;
768
769 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
770 }
771
772 static int sci_txroom(struct uart_port *port)
773 {
774 return port->fifosize - sci_txfill(port);
775 }
776
777 static int sci_rxfill(struct uart_port *port)
778 {
779 struct sci_port *s = to_sci_port(port);
780 unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
781 const struct plat_sci_reg *reg;
782
783 reg = sci_getreg(port, SCRFDR);
784 if (reg->size)
785 return serial_port_in(port, SCRFDR) & fifo_mask;
786
787 reg = sci_getreg(port, SCFDR);
788 if (reg->size)
789 return serial_port_in(port, SCFDR) & fifo_mask;
790
791 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
792 }
793
794 /* ********************************************************************** *
795 * the interrupt related routines *
796 * ********************************************************************** */
797
798 static void sci_transmit_chars(struct uart_port *port)
799 {
800 struct circ_buf *xmit = &port->state->xmit;
801 unsigned int stopped = uart_tx_stopped(port);
802 unsigned short status;
803 unsigned short ctrl;
804 int count;
805
806 status = serial_port_in(port, SCxSR);
807 if (!(status & SCxSR_TDxE(port))) {
808 ctrl = serial_port_in(port, SCSCR);
809 if (uart_circ_empty(xmit))
810 ctrl &= ~SCSCR_TIE;
811 else
812 ctrl |= SCSCR_TIE;
813 serial_port_out(port, SCSCR, ctrl);
814 return;
815 }
816
817 count = sci_txroom(port);
818
819 do {
820 unsigned char c;
821
822 if (port->x_char) {
823 c = port->x_char;
824 port->x_char = 0;
825 } else if (!uart_circ_empty(xmit) && !stopped) {
826 c = xmit->buf[xmit->tail];
827 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
828 } else {
829 break;
830 }
831
832 serial_port_out(port, SCxTDR, c);
833
834 port->icount.tx++;
835 } while (--count > 0);
836
837 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
838
839 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
840 uart_write_wakeup(port);
841 if (uart_circ_empty(xmit))
842 sci_stop_tx(port);
843
844 }
845
846 /* On SH3, SCIF may read end-of-break as a space->mark char */
847 #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
848
849 static void sci_receive_chars(struct uart_port *port)
850 {
851 struct tty_port *tport = &port->state->port;
852 int i, count, copied = 0;
853 unsigned short status;
854 unsigned char flag;
855
856 status = serial_port_in(port, SCxSR);
857 if (!(status & SCxSR_RDxF(port)))
858 return;
859
860 while (1) {
861 /* Don't copy more bytes than there is room for in the buffer */
862 count = tty_buffer_request_room(tport, sci_rxfill(port));
863
864 /* If for any reason we can't copy more data, we're done! */
865 if (count == 0)
866 break;
867
868 if (port->type == PORT_SCI) {
869 char c = serial_port_in(port, SCxRDR);
870 if (uart_handle_sysrq_char(port, c))
871 count = 0;
872 else
873 tty_insert_flip_char(tport, c, TTY_NORMAL);
874 } else {
875 for (i = 0; i < count; i++) {
876 char c = serial_port_in(port, SCxRDR);
877
878 status = serial_port_in(port, SCxSR);
879 if (uart_handle_sysrq_char(port, c)) {
880 count--; i--;
881 continue;
882 }
883
884 /* Store data and status */
885 if (status & SCxSR_FER(port)) {
886 flag = TTY_FRAME;
887 port->icount.frame++;
888 dev_notice(port->dev, "frame error\n");
889 } else if (status & SCxSR_PER(port)) {
890 flag = TTY_PARITY;
891 port->icount.parity++;
892 dev_notice(port->dev, "parity error\n");
893 } else
894 flag = TTY_NORMAL;
895
896 tty_insert_flip_char(tport, c, flag);
897 }
898 }
899
900 serial_port_in(port, SCxSR); /* dummy read */
901 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
902
903 copied += count;
904 port->icount.rx += count;
905 }
906
907 if (copied) {
908 /* Tell the rest of the system the news. New characters! */
909 tty_flip_buffer_push(tport);
910 } else {
911 /* TTY buffers full; read from RX reg to prevent lockup */
912 serial_port_in(port, SCxRDR);
913 serial_port_in(port, SCxSR); /* dummy read */
914 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
915 }
916 }
917
918 static int sci_handle_errors(struct uart_port *port)
919 {
920 int copied = 0;
921 unsigned short status = serial_port_in(port, SCxSR);
922 struct tty_port *tport = &port->state->port;
923 struct sci_port *s = to_sci_port(port);
924
925 /* Handle overruns */
926 if (status & s->params->overrun_mask) {
927 port->icount.overrun++;
928
929 /* overrun error */
930 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
931 copied++;
932
933 dev_notice(port->dev, "overrun error\n");
934 }
935
936 if (status & SCxSR_FER(port)) {
937 /* frame error */
938 port->icount.frame++;
939
940 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
941 copied++;
942
943 dev_notice(port->dev, "frame error\n");
944 }
945
946 if (status & SCxSR_PER(port)) {
947 /* parity error */
948 port->icount.parity++;
949
950 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
951 copied++;
952
953 dev_notice(port->dev, "parity error\n");
954 }
955
956 if (copied)
957 tty_flip_buffer_push(tport);
958
959 return copied;
960 }
961
962 static int sci_handle_fifo_overrun(struct uart_port *port)
963 {
964 struct tty_port *tport = &port->state->port;
965 struct sci_port *s = to_sci_port(port);
966 const struct plat_sci_reg *reg;
967 int copied = 0;
968 u16 status;
969
970 reg = sci_getreg(port, s->params->overrun_reg);
971 if (!reg->size)
972 return 0;
973
974 status = serial_port_in(port, s->params->overrun_reg);
975 if (status & s->params->overrun_mask) {
976 status &= ~s->params->overrun_mask;
977 serial_port_out(port, s->params->overrun_reg, status);
978
979 port->icount.overrun++;
980
981 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
982 tty_flip_buffer_push(tport);
983
984 dev_dbg(port->dev, "overrun error\n");
985 copied++;
986 }
987
988 return copied;
989 }
990
991 static int sci_handle_breaks(struct uart_port *port)
992 {
993 int copied = 0;
994 unsigned short status = serial_port_in(port, SCxSR);
995 struct tty_port *tport = &port->state->port;
996
997 if (uart_handle_break(port))
998 return 0;
999
1000 if (status & SCxSR_BRK(port)) {
1001 port->icount.brk++;
1002
1003 /* Notify of BREAK */
1004 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
1005 copied++;
1006
1007 dev_dbg(port->dev, "BREAK detected\n");
1008 }
1009
1010 if (copied)
1011 tty_flip_buffer_push(tport);
1012
1013 copied += sci_handle_fifo_overrun(port);
1014
1015 return copied;
1016 }
1017
1018 static int scif_set_rtrg(struct uart_port *port, int rx_trig)
1019 {
1020 unsigned int bits;
1021
1022 if (rx_trig < 1)
1023 rx_trig = 1;
1024 if (rx_trig >= port->fifosize)
1025 rx_trig = port->fifosize;
1026
1027 /* HSCIF can be set to an arbitrary level. */
1028 if (sci_getreg(port, HSRTRGR)->size) {
1029 serial_port_out(port, HSRTRGR, rx_trig);
1030 return rx_trig;
1031 }
1032
1033 switch (port->type) {
1034 case PORT_SCIF:
1035 if (rx_trig < 4) {
1036 bits = 0;
1037 rx_trig = 1;
1038 } else if (rx_trig < 8) {
1039 bits = SCFCR_RTRG0;
1040 rx_trig = 4;
1041 } else if (rx_trig < 14) {
1042 bits = SCFCR_RTRG1;
1043 rx_trig = 8;
1044 } else {
1045 bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1046 rx_trig = 14;
1047 }
1048 break;
1049 case PORT_SCIFA:
1050 case PORT_SCIFB:
1051 if (rx_trig < 16) {
1052 bits = 0;
1053 rx_trig = 1;
1054 } else if (rx_trig < 32) {
1055 bits = SCFCR_RTRG0;
1056 rx_trig = 16;
1057 } else if (rx_trig < 48) {
1058 bits = SCFCR_RTRG1;
1059 rx_trig = 32;
1060 } else {
1061 bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1062 rx_trig = 48;
1063 }
1064 break;
1065 default:
1066 WARN(1, "unknown FIFO configuration");
1067 return 1;
1068 }
1069
1070 serial_port_out(port, SCFCR,
1071 (serial_port_in(port, SCFCR) &
1072 ~(SCFCR_RTRG1 | SCFCR_RTRG0)) | bits);
1073
1074 return rx_trig;
1075 }
1076
1077 static int scif_rtrg_enabled(struct uart_port *port)
1078 {
1079 if (sci_getreg(port, HSRTRGR)->size)
1080 return serial_port_in(port, HSRTRGR) != 0;
1081 else
1082 return (serial_port_in(port, SCFCR) &
1083 (SCFCR_RTRG0 | SCFCR_RTRG1)) != 0;
1084 }
1085
1086 static void rx_fifo_timer_fn(struct timer_list *t)
1087 {
1088 struct sci_port *s = from_timer(s, t, rx_fifo_timer);
1089 struct uart_port *port = &s->port;
1090
1091 dev_dbg(port->dev, "Rx timed out\n");
1092 scif_set_rtrg(port, 1);
1093 }
1094
1095 static ssize_t rx_trigger_show(struct device *dev,
1096 struct device_attribute *attr,
1097 char *buf)
1098 {
1099 struct uart_port *port = dev_get_drvdata(dev);
1100 struct sci_port *sci = to_sci_port(port);
1101
1102 return sprintf(buf, "%d\n", sci->rx_trigger);
1103 }
1104
1105 static ssize_t rx_trigger_store(struct device *dev,
1106 struct device_attribute *attr,
1107 const char *buf,
1108 size_t count)
1109 {
1110 struct uart_port *port = dev_get_drvdata(dev);
1111 struct sci_port *sci = to_sci_port(port);
1112 int ret;
1113 long r;
1114
1115 ret = kstrtol(buf, 0, &r);
1116 if (ret)
1117 return ret;
1118
1119 sci->rx_trigger = scif_set_rtrg(port, r);
1120 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1121 scif_set_rtrg(port, 1);
1122
1123 return count;
1124 }
1125
1126 static DEVICE_ATTR(rx_fifo_trigger, 0644, rx_trigger_show, rx_trigger_store);
1127
1128 static ssize_t rx_fifo_timeout_show(struct device *dev,
1129 struct device_attribute *attr,
1130 char *buf)
1131 {
1132 struct uart_port *port = dev_get_drvdata(dev);
1133 struct sci_port *sci = to_sci_port(port);
1134 int v;
1135
1136 if (port->type == PORT_HSCIF)
1137 v = sci->hscif_tot >> HSSCR_TOT_SHIFT;
1138 else
1139 v = sci->rx_fifo_timeout;
1140
1141 return sprintf(buf, "%d\n", v);
1142 }
1143
1144 static ssize_t rx_fifo_timeout_store(struct device *dev,
1145 struct device_attribute *attr,
1146 const char *buf,
1147 size_t count)
1148 {
1149 struct uart_port *port = dev_get_drvdata(dev);
1150 struct sci_port *sci = to_sci_port(port);
1151 int ret;
1152 long r;
1153
1154 ret = kstrtol(buf, 0, &r);
1155 if (ret)
1156 return ret;
1157
1158 if (port->type == PORT_HSCIF) {
1159 if (r < 0 || r > 3)
1160 return -EINVAL;
1161 sci->hscif_tot = r << HSSCR_TOT_SHIFT;
1162 } else {
1163 sci->rx_fifo_timeout = r;
1164 scif_set_rtrg(port, 1);
1165 if (r > 0)
1166 timer_setup(&sci->rx_fifo_timer, rx_fifo_timer_fn, 0);
1167 }
1168
1169 return count;
1170 }
1171
1172 static DEVICE_ATTR_RW(rx_fifo_timeout);
1173
1174
1175 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1176 static void sci_dma_tx_complete(void *arg)
1177 {
1178 struct sci_port *s = arg;
1179 struct uart_port *port = &s->port;
1180 struct circ_buf *xmit = &port->state->xmit;
1181 unsigned long flags;
1182
1183 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1184
1185 spin_lock_irqsave(&port->lock, flags);
1186
1187 xmit->tail += s->tx_dma_len;
1188 xmit->tail &= UART_XMIT_SIZE - 1;
1189
1190 port->icount.tx += s->tx_dma_len;
1191
1192 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1193 uart_write_wakeup(port);
1194
1195 if (!uart_circ_empty(xmit)) {
1196 s->cookie_tx = 0;
1197 schedule_work(&s->work_tx);
1198 } else {
1199 s->cookie_tx = -EINVAL;
1200 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1201 u16 ctrl = serial_port_in(port, SCSCR);
1202 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1203 }
1204 }
1205
1206 spin_unlock_irqrestore(&port->lock, flags);
1207 }
1208
1209 /* Locking: called with port lock held */
1210 static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count)
1211 {
1212 struct uart_port *port = &s->port;
1213 struct tty_port *tport = &port->state->port;
1214 int copied;
1215
1216 copied = tty_insert_flip_string(tport, buf, count);
1217 if (copied < count)
1218 port->icount.buf_overrun++;
1219
1220 port->icount.rx += copied;
1221
1222 return copied;
1223 }
1224
1225 static int sci_dma_rx_find_active(struct sci_port *s)
1226 {
1227 unsigned int i;
1228
1229 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1230 if (s->active_rx == s->cookie_rx[i])
1231 return i;
1232
1233 return -1;
1234 }
1235
1236 static void sci_dma_rx_chan_invalidate(struct sci_port *s)
1237 {
1238 unsigned int i;
1239
1240 s->chan_rx = NULL;
1241 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1242 s->cookie_rx[i] = -EINVAL;
1243 s->active_rx = 0;
1244 }
1245
1246 static void sci_dma_rx_release(struct sci_port *s)
1247 {
1248 struct dma_chan *chan = s->chan_rx_saved;
1249
1250 s->chan_rx_saved = NULL;
1251 sci_dma_rx_chan_invalidate(s);
1252 dmaengine_terminate_sync(chan);
1253 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0],
1254 sg_dma_address(&s->sg_rx[0]));
1255 dma_release_channel(chan);
1256 }
1257
1258 static void start_hrtimer_us(struct hrtimer *hrt, unsigned long usec)
1259 {
1260 long sec = usec / 1000000;
1261 long nsec = (usec % 1000000) * 1000;
1262 ktime_t t = ktime_set(sec, nsec);
1263
1264 hrtimer_start(hrt, t, HRTIMER_MODE_REL);
1265 }
1266
1267 static void sci_dma_rx_reenable_irq(struct sci_port *s)
1268 {
1269 struct uart_port *port = &s->port;
1270 u16 scr;
1271
1272 /* Direct new serial port interrupts back to CPU */
1273 scr = serial_port_in(port, SCSCR);
1274 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1275 scr &= ~SCSCR_RDRQE;
1276 enable_irq(s->irqs[SCIx_RXI_IRQ]);
1277 }
1278 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
1279 }
1280
1281 static void sci_dma_rx_complete(void *arg)
1282 {
1283 struct sci_port *s = arg;
1284 struct dma_chan *chan = s->chan_rx;
1285 struct uart_port *port = &s->port;
1286 struct dma_async_tx_descriptor *desc;
1287 unsigned long flags;
1288 int active, count = 0;
1289
1290 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line,
1291 s->active_rx);
1292
1293 spin_lock_irqsave(&port->lock, flags);
1294
1295 active = sci_dma_rx_find_active(s);
1296 if (active >= 0)
1297 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx);
1298
1299 start_hrtimer_us(&s->rx_timer, s->rx_timeout);
1300
1301 if (count)
1302 tty_flip_buffer_push(&port->state->port);
1303
1304 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1,
1305 DMA_DEV_TO_MEM,
1306 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1307 if (!desc)
1308 goto fail;
1309
1310 desc->callback = sci_dma_rx_complete;
1311 desc->callback_param = s;
1312 s->cookie_rx[active] = dmaengine_submit(desc);
1313 if (dma_submit_error(s->cookie_rx[active]))
1314 goto fail;
1315
1316 s->active_rx = s->cookie_rx[!active];
1317
1318 dma_async_issue_pending(chan);
1319
1320 spin_unlock_irqrestore(&port->lock, flags);
1321 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n",
1322 __func__, s->cookie_rx[active], active, s->active_rx);
1323 return;
1324
1325 fail:
1326 spin_unlock_irqrestore(&port->lock, flags);
1327 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1328 /* Switch to PIO */
1329 spin_lock_irqsave(&port->lock, flags);
1330 dmaengine_terminate_async(chan);
1331 sci_dma_rx_chan_invalidate(s);
1332 sci_dma_rx_reenable_irq(s);
1333 spin_unlock_irqrestore(&port->lock, flags);
1334 }
1335
1336 static void sci_dma_tx_release(struct sci_port *s)
1337 {
1338 struct dma_chan *chan = s->chan_tx_saved;
1339
1340 cancel_work_sync(&s->work_tx);
1341 s->chan_tx_saved = s->chan_tx = NULL;
1342 s->cookie_tx = -EINVAL;
1343 dmaengine_terminate_sync(chan);
1344 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE,
1345 DMA_TO_DEVICE);
1346 dma_release_channel(chan);
1347 }
1348
1349 static int sci_dma_rx_submit(struct sci_port *s, bool port_lock_held)
1350 {
1351 struct dma_chan *chan = s->chan_rx;
1352 struct uart_port *port = &s->port;
1353 unsigned long flags;
1354 int i;
1355
1356 for (i = 0; i < 2; i++) {
1357 struct scatterlist *sg = &s->sg_rx[i];
1358 struct dma_async_tx_descriptor *desc;
1359
1360 desc = dmaengine_prep_slave_sg(chan,
1361 sg, 1, DMA_DEV_TO_MEM,
1362 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1363 if (!desc)
1364 goto fail;
1365
1366 desc->callback = sci_dma_rx_complete;
1367 desc->callback_param = s;
1368 s->cookie_rx[i] = dmaengine_submit(desc);
1369 if (dma_submit_error(s->cookie_rx[i]))
1370 goto fail;
1371
1372 }
1373
1374 s->active_rx = s->cookie_rx[0];
1375
1376 dma_async_issue_pending(chan);
1377 return 0;
1378
1379 fail:
1380 /* Switch to PIO */
1381 if (!port_lock_held)
1382 spin_lock_irqsave(&port->lock, flags);
1383 if (i)
1384 dmaengine_terminate_async(chan);
1385 sci_dma_rx_chan_invalidate(s);
1386 sci_start_rx(port);
1387 if (!port_lock_held)
1388 spin_unlock_irqrestore(&port->lock, flags);
1389 return -EAGAIN;
1390 }
1391
1392 static void sci_dma_tx_work_fn(struct work_struct *work)
1393 {
1394 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1395 struct dma_async_tx_descriptor *desc;
1396 struct dma_chan *chan = s->chan_tx;
1397 struct uart_port *port = &s->port;
1398 struct circ_buf *xmit = &port->state->xmit;
1399 unsigned long flags;
1400 dma_addr_t buf;
1401
1402 /*
1403 * DMA is idle now.
1404 * Port xmit buffer is already mapped, and it is one page... Just adjust
1405 * offsets and lengths. Since it is a circular buffer, we have to
1406 * transmit till the end, and then the rest. Take the port lock to get a
1407 * consistent xmit buffer state.
1408 */
1409 spin_lock_irq(&port->lock);
1410 buf = s->tx_dma_addr + (xmit->tail & (UART_XMIT_SIZE - 1));
1411 s->tx_dma_len = min_t(unsigned int,
1412 CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
1413 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
1414 spin_unlock_irq(&port->lock);
1415
1416 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len,
1417 DMA_MEM_TO_DEV,
1418 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1419 if (!desc) {
1420 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n");
1421 goto switch_to_pio;
1422 }
1423
1424 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len,
1425 DMA_TO_DEVICE);
1426
1427 spin_lock_irq(&port->lock);
1428 desc->callback = sci_dma_tx_complete;
1429 desc->callback_param = s;
1430 spin_unlock_irq(&port->lock);
1431 s->cookie_tx = dmaengine_submit(desc);
1432 if (dma_submit_error(s->cookie_tx)) {
1433 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1434 goto switch_to_pio;
1435 }
1436
1437 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
1438 __func__, xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
1439
1440 dma_async_issue_pending(chan);
1441 return;
1442
1443 switch_to_pio:
1444 spin_lock_irqsave(&port->lock, flags);
1445 s->chan_tx = NULL;
1446 sci_start_tx(port);
1447 spin_unlock_irqrestore(&port->lock, flags);
1448 return;
1449 }
1450
1451 static enum hrtimer_restart sci_dma_rx_timer_fn(struct hrtimer *t)
1452 {
1453 struct sci_port *s = container_of(t, struct sci_port, rx_timer);
1454 struct dma_chan *chan = s->chan_rx;
1455 struct uart_port *port = &s->port;
1456 struct dma_tx_state state;
1457 enum dma_status status;
1458 unsigned long flags;
1459 unsigned int read;
1460 int active, count;
1461
1462 dev_dbg(port->dev, "DMA Rx timed out\n");
1463
1464 spin_lock_irqsave(&port->lock, flags);
1465
1466 active = sci_dma_rx_find_active(s);
1467 if (active < 0) {
1468 spin_unlock_irqrestore(&port->lock, flags);
1469 return HRTIMER_NORESTART;
1470 }
1471
1472 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1473 if (status == DMA_COMPLETE) {
1474 spin_unlock_irqrestore(&port->lock, flags);
1475 dev_dbg(port->dev, "Cookie %d #%d has already completed\n",
1476 s->active_rx, active);
1477
1478 /* Let packet complete handler take care of the packet */
1479 return HRTIMER_NORESTART;
1480 }
1481
1482 dmaengine_pause(chan);
1483
1484 /*
1485 * sometimes DMA transfer doesn't stop even if it is stopped and
1486 * data keeps on coming until transaction is complete so check
1487 * for DMA_COMPLETE again
1488 * Let packet complete handler take care of the packet
1489 */
1490 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1491 if (status == DMA_COMPLETE) {
1492 spin_unlock_irqrestore(&port->lock, flags);
1493 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped");
1494 return HRTIMER_NORESTART;
1495 }
1496
1497 /* Handle incomplete DMA receive */
1498 dmaengine_terminate_async(s->chan_rx);
1499 read = sg_dma_len(&s->sg_rx[active]) - state.residue;
1500
1501 if (read) {
1502 count = sci_dma_rx_push(s, s->rx_buf[active], read);
1503 if (count)
1504 tty_flip_buffer_push(&port->state->port);
1505 }
1506
1507 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1508 sci_dma_rx_submit(s, true);
1509
1510 sci_dma_rx_reenable_irq(s);
1511
1512 spin_unlock_irqrestore(&port->lock, flags);
1513
1514 return HRTIMER_NORESTART;
1515 }
1516
1517 static struct dma_chan *sci_request_dma_chan(struct uart_port *port,
1518 enum dma_transfer_direction dir)
1519 {
1520 struct dma_chan *chan;
1521 struct dma_slave_config cfg;
1522 int ret;
1523
1524 chan = dma_request_slave_channel(port->dev,
1525 dir == DMA_MEM_TO_DEV ? "tx" : "rx");
1526 if (!chan) {
1527 dev_dbg(port->dev, "dma_request_slave_channel failed\n");
1528 return NULL;
1529 }
1530
1531 memset(&cfg, 0, sizeof(cfg));
1532 cfg.direction = dir;
1533 if (dir == DMA_MEM_TO_DEV) {
1534 cfg.dst_addr = port->mapbase +
1535 (sci_getreg(port, SCxTDR)->offset << port->regshift);
1536 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1537 } else {
1538 cfg.src_addr = port->mapbase +
1539 (sci_getreg(port, SCxRDR)->offset << port->regshift);
1540 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1541 }
1542
1543 ret = dmaengine_slave_config(chan, &cfg);
1544 if (ret) {
1545 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret);
1546 dma_release_channel(chan);
1547 return NULL;
1548 }
1549
1550 return chan;
1551 }
1552
1553 static void sci_request_dma(struct uart_port *port)
1554 {
1555 struct sci_port *s = to_sci_port(port);
1556 struct dma_chan *chan;
1557
1558 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
1559
1560 /*
1561 * DMA on console may interfere with Kernel log messages which use
1562 * plain putchar(). So, simply don't use it with a console.
1563 */
1564 if (uart_console(port))
1565 return;
1566
1567 if (!port->dev->of_node)
1568 return;
1569
1570 s->cookie_tx = -EINVAL;
1571
1572 /*
1573 * Don't request a dma channel if no channel was specified
1574 * in the device tree.
1575 */
1576 if (!of_find_property(port->dev->of_node, "dmas", NULL))
1577 return;
1578
1579 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV);
1580 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1581 if (chan) {
1582 /* UART circular tx buffer is an aligned page. */
1583 s->tx_dma_addr = dma_map_single(chan->device->dev,
1584 port->state->xmit.buf,
1585 UART_XMIT_SIZE,
1586 DMA_TO_DEVICE);
1587 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) {
1588 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n");
1589 dma_release_channel(chan);
1590 } else {
1591 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n",
1592 __func__, UART_XMIT_SIZE,
1593 port->state->xmit.buf, &s->tx_dma_addr);
1594
1595 INIT_WORK(&s->work_tx, sci_dma_tx_work_fn);
1596 s->chan_tx_saved = s->chan_tx = chan;
1597 }
1598 }
1599
1600 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM);
1601 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1602 if (chan) {
1603 unsigned int i;
1604 dma_addr_t dma;
1605 void *buf;
1606
1607 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize);
1608 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2,
1609 &dma, GFP_KERNEL);
1610 if (!buf) {
1611 dev_warn(port->dev,
1612 "Failed to allocate Rx dma buffer, using PIO\n");
1613 dma_release_channel(chan);
1614 return;
1615 }
1616
1617 for (i = 0; i < 2; i++) {
1618 struct scatterlist *sg = &s->sg_rx[i];
1619
1620 sg_init_table(sg, 1);
1621 s->rx_buf[i] = buf;
1622 sg_dma_address(sg) = dma;
1623 sg_dma_len(sg) = s->buf_len_rx;
1624
1625 buf += s->buf_len_rx;
1626 dma += s->buf_len_rx;
1627 }
1628
1629 hrtimer_init(&s->rx_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1630 s->rx_timer.function = sci_dma_rx_timer_fn;
1631
1632 s->chan_rx_saved = s->chan_rx = chan;
1633
1634 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1635 sci_dma_rx_submit(s, false);
1636 }
1637 }
1638
1639 static void sci_free_dma(struct uart_port *port)
1640 {
1641 struct sci_port *s = to_sci_port(port);
1642
1643 if (s->chan_tx_saved)
1644 sci_dma_tx_release(s);
1645 if (s->chan_rx_saved)
1646 sci_dma_rx_release(s);
1647 }
1648
1649 static void sci_flush_buffer(struct uart_port *port)
1650 {
1651 /*
1652 * In uart_flush_buffer(), the xmit circular buffer has just been
1653 * cleared, so we have to reset tx_dma_len accordingly.
1654 */
1655 to_sci_port(port)->tx_dma_len = 0;
1656 }
1657 #else /* !CONFIG_SERIAL_SH_SCI_DMA */
1658 static inline void sci_request_dma(struct uart_port *port)
1659 {
1660 }
1661
1662 static inline void sci_free_dma(struct uart_port *port)
1663 {
1664 }
1665
1666 #define sci_flush_buffer NULL
1667 #endif /* !CONFIG_SERIAL_SH_SCI_DMA */
1668
1669 static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1670 {
1671 struct uart_port *port = ptr;
1672 struct sci_port *s = to_sci_port(port);
1673
1674 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1675 if (s->chan_rx) {
1676 u16 scr = serial_port_in(port, SCSCR);
1677 u16 ssr = serial_port_in(port, SCxSR);
1678
1679 /* Disable future Rx interrupts */
1680 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1681 disable_irq_nosync(irq);
1682 scr |= SCSCR_RDRQE;
1683 } else {
1684 if (sci_dma_rx_submit(s, false) < 0)
1685 goto handle_pio;
1686
1687 scr &= ~SCSCR_RIE;
1688 }
1689 serial_port_out(port, SCSCR, scr);
1690 /* Clear current interrupt */
1691 serial_port_out(port, SCxSR,
1692 ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
1693 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u us\n",
1694 jiffies, s->rx_timeout);
1695 start_hrtimer_us(&s->rx_timer, s->rx_timeout);
1696
1697 return IRQ_HANDLED;
1698 }
1699
1700 handle_pio:
1701 #endif
1702
1703 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) {
1704 if (!scif_rtrg_enabled(port))
1705 scif_set_rtrg(port, s->rx_trigger);
1706
1707 mod_timer(&s->rx_fifo_timer, jiffies + DIV_ROUND_UP(
1708 s->rx_frame * HZ * s->rx_fifo_timeout, 1000000));
1709 }
1710
1711 /* I think sci_receive_chars has to be called irrespective
1712 * of whether the I_IXOFF is set, otherwise, how is the interrupt
1713 * to be disabled?
1714 */
1715 sci_receive_chars(port);
1716
1717 return IRQ_HANDLED;
1718 }
1719
1720 static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
1721 {
1722 struct uart_port *port = ptr;
1723 unsigned long flags;
1724
1725 spin_lock_irqsave(&port->lock, flags);
1726 sci_transmit_chars(port);
1727 spin_unlock_irqrestore(&port->lock, flags);
1728
1729 return IRQ_HANDLED;
1730 }
1731
1732 static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1733 {
1734 struct uart_port *port = ptr;
1735
1736 /* Handle BREAKs */
1737 sci_handle_breaks(port);
1738 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
1739
1740 return IRQ_HANDLED;
1741 }
1742
1743 static irqreturn_t sci_er_interrupt(int irq, void *ptr)
1744 {
1745 struct uart_port *port = ptr;
1746 struct sci_port *s = to_sci_port(port);
1747
1748 if (s->irqs[SCIx_ERI_IRQ] == s->irqs[SCIx_BRI_IRQ]) {
1749 /* Break and Error interrupts are muxed */
1750 unsigned short ssr_status = serial_port_in(port, SCxSR);
1751
1752 /* Break Interrupt */
1753 if (ssr_status & SCxSR_BRK(port))
1754 sci_br_interrupt(irq, ptr);
1755
1756 /* Break only? */
1757 if (!(ssr_status & SCxSR_ERRORS(port)))
1758 return IRQ_HANDLED;
1759 }
1760
1761 /* Handle errors */
1762 if (port->type == PORT_SCI) {
1763 if (sci_handle_errors(port)) {
1764 /* discard character in rx buffer */
1765 serial_port_in(port, SCxSR);
1766 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1767 }
1768 } else {
1769 sci_handle_fifo_overrun(port);
1770 if (!s->chan_rx)
1771 sci_receive_chars(port);
1772 }
1773
1774 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1775
1776 /* Kick the transmission */
1777 if (!s->chan_tx)
1778 sci_tx_interrupt(irq, ptr);
1779
1780 return IRQ_HANDLED;
1781 }
1782
1783 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1784 {
1785 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
1786 struct uart_port *port = ptr;
1787 struct sci_port *s = to_sci_port(port);
1788 irqreturn_t ret = IRQ_NONE;
1789
1790 ssr_status = serial_port_in(port, SCxSR);
1791 scr_status = serial_port_in(port, SCSCR);
1792 if (s->params->overrun_reg == SCxSR)
1793 orer_status = ssr_status;
1794 else if (sci_getreg(port, s->params->overrun_reg)->size)
1795 orer_status = serial_port_in(port, s->params->overrun_reg);
1796
1797 err_enabled = scr_status & port_rx_irq_mask(port);
1798
1799 /* Tx Interrupt */
1800 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
1801 !s->chan_tx)
1802 ret = sci_tx_interrupt(irq, ptr);
1803
1804 /*
1805 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1806 * DR flags
1807 */
1808 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
1809 (scr_status & SCSCR_RIE))
1810 ret = sci_rx_interrupt(irq, ptr);
1811
1812 /* Error Interrupt */
1813 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
1814 ret = sci_er_interrupt(irq, ptr);
1815
1816 /* Break Interrupt */
1817 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
1818 ret = sci_br_interrupt(irq, ptr);
1819
1820 /* Overrun Interrupt */
1821 if (orer_status & s->params->overrun_mask) {
1822 sci_handle_fifo_overrun(port);
1823 ret = IRQ_HANDLED;
1824 }
1825
1826 return ret;
1827 }
1828
1829 static const struct sci_irq_desc {
1830 const char *desc;
1831 irq_handler_t handler;
1832 } sci_irq_desc[] = {
1833 /*
1834 * Split out handlers, the default case.
1835 */
1836 [SCIx_ERI_IRQ] = {
1837 .desc = "rx err",
1838 .handler = sci_er_interrupt,
1839 },
1840
1841 [SCIx_RXI_IRQ] = {
1842 .desc = "rx full",
1843 .handler = sci_rx_interrupt,
1844 },
1845
1846 [SCIx_TXI_IRQ] = {
1847 .desc = "tx empty",
1848 .handler = sci_tx_interrupt,
1849 },
1850
1851 [SCIx_BRI_IRQ] = {
1852 .desc = "break",
1853 .handler = sci_br_interrupt,
1854 },
1855
1856 [SCIx_DRI_IRQ] = {
1857 .desc = "rx ready",
1858 .handler = sci_rx_interrupt,
1859 },
1860
1861 [SCIx_TEI_IRQ] = {
1862 .desc = "tx end",
1863 .handler = sci_tx_interrupt,
1864 },
1865
1866 /*
1867 * Special muxed handler.
1868 */
1869 [SCIx_MUX_IRQ] = {
1870 .desc = "mux",
1871 .handler = sci_mpxed_interrupt,
1872 },
1873 };
1874
1875 static int sci_request_irq(struct sci_port *port)
1876 {
1877 struct uart_port *up = &port->port;
1878 int i, j, w, ret = 0;
1879
1880 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1881 const struct sci_irq_desc *desc;
1882 int irq;
1883
1884 /* Check if already registered (muxed) */
1885 for (w = 0; w < i; w++)
1886 if (port->irqs[w] == port->irqs[i])
1887 w = i + 1;
1888 if (w > i)
1889 continue;
1890
1891 if (SCIx_IRQ_IS_MUXED(port)) {
1892 i = SCIx_MUX_IRQ;
1893 irq = up->irq;
1894 } else {
1895 irq = port->irqs[i];
1896
1897 /*
1898 * Certain port types won't support all of the
1899 * available interrupt sources.
1900 */
1901 if (unlikely(irq < 0))
1902 continue;
1903 }
1904
1905 desc = sci_irq_desc + i;
1906 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1907 dev_name(up->dev), desc->desc);
1908 if (!port->irqstr[j]) {
1909 ret = -ENOMEM;
1910 goto out_nomem;
1911 }
1912
1913 ret = request_irq(irq, desc->handler, up->irqflags,
1914 port->irqstr[j], port);
1915 if (unlikely(ret)) {
1916 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1917 goto out_noirq;
1918 }
1919 }
1920
1921 return 0;
1922
1923 out_noirq:
1924 while (--i >= 0)
1925 free_irq(port->irqs[i], port);
1926
1927 out_nomem:
1928 while (--j >= 0)
1929 kfree(port->irqstr[j]);
1930
1931 return ret;
1932 }
1933
1934 static void sci_free_irq(struct sci_port *port)
1935 {
1936 int i, j;
1937
1938 /*
1939 * Intentionally in reverse order so we iterate over the muxed
1940 * IRQ first.
1941 */
1942 for (i = 0; i < SCIx_NR_IRQS; i++) {
1943 int irq = port->irqs[i];
1944
1945 /*
1946 * Certain port types won't support all of the available
1947 * interrupt sources.
1948 */
1949 if (unlikely(irq < 0))
1950 continue;
1951
1952 /* Check if already freed (irq was muxed) */
1953 for (j = 0; j < i; j++)
1954 if (port->irqs[j] == irq)
1955 j = i + 1;
1956 if (j > i)
1957 continue;
1958
1959 free_irq(port->irqs[i], port);
1960 kfree(port->irqstr[i]);
1961
1962 if (SCIx_IRQ_IS_MUXED(port)) {
1963 /* If there's only one IRQ, we're done. */
1964 return;
1965 }
1966 }
1967 }
1968
1969 static unsigned int sci_tx_empty(struct uart_port *port)
1970 {
1971 unsigned short status = serial_port_in(port, SCxSR);
1972 unsigned short in_tx_fifo = sci_txfill(port);
1973
1974 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1975 }
1976
1977 static void sci_set_rts(struct uart_port *port, bool state)
1978 {
1979 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1980 u16 data = serial_port_in(port, SCPDR);
1981
1982 /* Active low */
1983 if (state)
1984 data &= ~SCPDR_RTSD;
1985 else
1986 data |= SCPDR_RTSD;
1987 serial_port_out(port, SCPDR, data);
1988
1989 /* RTS# is output */
1990 serial_port_out(port, SCPCR,
1991 serial_port_in(port, SCPCR) | SCPCR_RTSC);
1992 } else if (sci_getreg(port, SCSPTR)->size) {
1993 u16 ctrl = serial_port_in(port, SCSPTR);
1994
1995 /* Active low */
1996 if (state)
1997 ctrl &= ~SCSPTR_RTSDT;
1998 else
1999 ctrl |= SCSPTR_RTSDT;
2000 serial_port_out(port, SCSPTR, ctrl);
2001 }
2002 }
2003
2004 static bool sci_get_cts(struct uart_port *port)
2005 {
2006 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
2007 /* Active low */
2008 return !(serial_port_in(port, SCPDR) & SCPDR_CTSD);
2009 } else if (sci_getreg(port, SCSPTR)->size) {
2010 /* Active low */
2011 return !(serial_port_in(port, SCSPTR) & SCSPTR_CTSDT);
2012 }
2013
2014 return true;
2015 }
2016
2017 /*
2018 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
2019 * CTS/RTS is supported in hardware by at least one port and controlled
2020 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
2021 * handled via the ->init_pins() op, which is a bit of a one-way street,
2022 * lacking any ability to defer pin control -- this will later be
2023 * converted over to the GPIO framework).
2024 *
2025 * Other modes (such as loopback) are supported generically on certain
2026 * port types, but not others. For these it's sufficient to test for the
2027 * existence of the support register and simply ignore the port type.
2028 */
2029 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
2030 {
2031 struct sci_port *s = to_sci_port(port);
2032
2033 if (mctrl & TIOCM_LOOP) {
2034 const struct plat_sci_reg *reg;
2035
2036 /*
2037 * Standard loopback mode for SCFCR ports.
2038 */
2039 reg = sci_getreg(port, SCFCR);
2040 if (reg->size)
2041 serial_port_out(port, SCFCR,
2042 serial_port_in(port, SCFCR) |
2043 SCFCR_LOOP);
2044 }
2045
2046 mctrl_gpio_set(s->gpios, mctrl);
2047
2048 if (!s->has_rtscts)
2049 return;
2050
2051 if (!(mctrl & TIOCM_RTS)) {
2052 /* Disable Auto RTS */
2053 serial_port_out(port, SCFCR,
2054 serial_port_in(port, SCFCR) & ~SCFCR_MCE);
2055
2056 /* Clear RTS */
2057 sci_set_rts(port, 0);
2058 } else if (s->autorts) {
2059 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
2060 /* Enable RTS# pin function */
2061 serial_port_out(port, SCPCR,
2062 serial_port_in(port, SCPCR) & ~SCPCR_RTSC);
2063 }
2064
2065 /* Enable Auto RTS */
2066 serial_port_out(port, SCFCR,
2067 serial_port_in(port, SCFCR) | SCFCR_MCE);
2068 } else {
2069 /* Set RTS */
2070 sci_set_rts(port, 1);
2071 }
2072 }
2073
2074 static unsigned int sci_get_mctrl(struct uart_port *port)
2075 {
2076 struct sci_port *s = to_sci_port(port);
2077 struct mctrl_gpios *gpios = s->gpios;
2078 unsigned int mctrl = 0;
2079
2080 mctrl_gpio_get(gpios, &mctrl);
2081
2082 /*
2083 * CTS/RTS is handled in hardware when supported, while nothing
2084 * else is wired up.
2085 */
2086 if (s->autorts) {
2087 if (sci_get_cts(port))
2088 mctrl |= TIOCM_CTS;
2089 } else if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS))) {
2090 mctrl |= TIOCM_CTS;
2091 }
2092 if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR)))
2093 mctrl |= TIOCM_DSR;
2094 if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD)))
2095 mctrl |= TIOCM_CAR;
2096
2097 return mctrl;
2098 }
2099
2100 static void sci_enable_ms(struct uart_port *port)
2101 {
2102 mctrl_gpio_enable_ms(to_sci_port(port)->gpios);
2103 }
2104
2105 static void sci_break_ctl(struct uart_port *port, int break_state)
2106 {
2107 unsigned short scscr, scsptr;
2108 unsigned long flags;
2109
2110 /* check wheter the port has SCSPTR */
2111 if (!sci_getreg(port, SCSPTR)->size) {
2112 /*
2113 * Not supported by hardware. Most parts couple break and rx
2114 * interrupts together, with break detection always enabled.
2115 */
2116 return;
2117 }
2118
2119 spin_lock_irqsave(&port->lock, flags);
2120 scsptr = serial_port_in(port, SCSPTR);
2121 scscr = serial_port_in(port, SCSCR);
2122
2123 if (break_state == -1) {
2124 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
2125 scscr &= ~SCSCR_TE;
2126 } else {
2127 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
2128 scscr |= SCSCR_TE;
2129 }
2130
2131 serial_port_out(port, SCSPTR, scsptr);
2132 serial_port_out(port, SCSCR, scscr);
2133 spin_unlock_irqrestore(&port->lock, flags);
2134 }
2135
2136 static int sci_startup(struct uart_port *port)
2137 {
2138 struct sci_port *s = to_sci_port(port);
2139 int ret;
2140
2141 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2142
2143 sci_request_dma(port);
2144
2145 ret = sci_request_irq(s);
2146 if (unlikely(ret < 0)) {
2147 sci_free_dma(port);
2148 return ret;
2149 }
2150
2151 return 0;
2152 }
2153
2154 static void sci_shutdown(struct uart_port *port)
2155 {
2156 struct sci_port *s = to_sci_port(port);
2157 unsigned long flags;
2158 u16 scr;
2159
2160 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2161
2162 s->autorts = false;
2163 mctrl_gpio_disable_ms(to_sci_port(port)->gpios);
2164
2165 spin_lock_irqsave(&port->lock, flags);
2166 sci_stop_rx(port);
2167 sci_stop_tx(port);
2168 /*
2169 * Stop RX and TX, disable related interrupts, keep clock source
2170 * and HSCIF TOT bits
2171 */
2172 scr = serial_port_in(port, SCSCR);
2173 serial_port_out(port, SCSCR, scr &
2174 (SCSCR_CKE1 | SCSCR_CKE0 | s->hscif_tot));
2175 spin_unlock_irqrestore(&port->lock, flags);
2176
2177 #ifdef CONFIG_SERIAL_SH_SCI_DMA
2178 if (s->chan_rx_saved) {
2179 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__,
2180 port->line);
2181 hrtimer_cancel(&s->rx_timer);
2182 }
2183 #endif
2184
2185 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0)
2186 del_timer_sync(&s->rx_fifo_timer);
2187 sci_free_irq(s);
2188 sci_free_dma(port);
2189 }
2190
2191 static int sci_sck_calc(struct sci_port *s, unsigned int bps,
2192 unsigned int *srr)
2193 {
2194 unsigned long freq = s->clk_rates[SCI_SCK];
2195 int err, min_err = INT_MAX;
2196 unsigned int sr;
2197
2198 if (s->port.type != PORT_HSCIF)
2199 freq *= 2;
2200
2201 for_each_sr(sr, s) {
2202 err = DIV_ROUND_CLOSEST(freq, sr) - bps;
2203 if (abs(err) >= abs(min_err))
2204 continue;
2205
2206 min_err = err;
2207 *srr = sr - 1;
2208
2209 if (!err)
2210 break;
2211 }
2212
2213 dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err,
2214 *srr + 1);
2215 return min_err;
2216 }
2217
2218 static int sci_brg_calc(struct sci_port *s, unsigned int bps,
2219 unsigned long freq, unsigned int *dlr,
2220 unsigned int *srr)
2221 {
2222 int err, min_err = INT_MAX;
2223 unsigned int sr, dl;
2224
2225 if (s->port.type != PORT_HSCIF)
2226 freq *= 2;
2227
2228 for_each_sr(sr, s) {
2229 dl = DIV_ROUND_CLOSEST(freq, sr * bps);
2230 dl = clamp(dl, 1U, 65535U);
2231
2232 err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps;
2233 if (abs(err) >= abs(min_err))
2234 continue;
2235
2236 min_err = err;
2237 *dlr = dl;
2238 *srr = sr - 1;
2239
2240 if (!err)
2241 break;
2242 }
2243
2244 dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps,
2245 min_err, *dlr, *srr + 1);
2246 return min_err;
2247 }
2248
2249 /* calculate sample rate, BRR, and clock select */
2250 static int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
2251 unsigned int *brr, unsigned int *srr,
2252 unsigned int *cks)
2253 {
2254 unsigned long freq = s->clk_rates[SCI_FCK];
2255 unsigned int sr, br, prediv, scrate, c;
2256 int err, min_err = INT_MAX;
2257
2258 if (s->port.type != PORT_HSCIF)
2259 freq *= 2;
2260
2261 /*
2262 * Find the combination of sample rate and clock select with the
2263 * smallest deviation from the desired baud rate.
2264 * Prefer high sample rates to maximise the receive margin.
2265 *
2266 * M: Receive margin (%)
2267 * N: Ratio of bit rate to clock (N = sampling rate)
2268 * D: Clock duty (D = 0 to 1.0)
2269 * L: Frame length (L = 9 to 12)
2270 * F: Absolute value of clock frequency deviation
2271 *
2272 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
2273 * (|D - 0.5| / N * (1 + F))|
2274 * NOTE: Usually, treat D for 0.5, F is 0 by this calculation.
2275 */
2276 for_each_sr(sr, s) {
2277 for (c = 0; c <= 3; c++) {
2278 /* integerized formulas from HSCIF documentation */
2279 prediv = sr * (1 << (2 * c + 1));
2280
2281 /*
2282 * We need to calculate:
2283 *
2284 * br = freq / (prediv * bps) clamped to [1..256]
2285 * err = freq / (br * prediv) - bps
2286 *
2287 * Watch out for overflow when calculating the desired
2288 * sampling clock rate!
2289 */
2290 if (bps > UINT_MAX / prediv)
2291 break;
2292
2293 scrate = prediv * bps;
2294 br = DIV_ROUND_CLOSEST(freq, scrate);
2295 br = clamp(br, 1U, 256U);
2296
2297 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps;
2298 if (abs(err) >= abs(min_err))
2299 continue;
2300
2301 min_err = err;
2302 *brr = br - 1;
2303 *srr = sr - 1;
2304 *cks = c;
2305
2306 if (!err)
2307 goto found;
2308 }
2309 }
2310
2311 found:
2312 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps,
2313 min_err, *brr, *srr + 1, *cks);
2314 return min_err;
2315 }
2316
2317 static void sci_reset(struct uart_port *port)
2318 {
2319 const struct plat_sci_reg *reg;
2320 unsigned int status;
2321 struct sci_port *s = to_sci_port(port);
2322
2323 serial_port_out(port, SCSCR, s->hscif_tot); /* TE=0, RE=0, CKE1=0 */
2324
2325 reg = sci_getreg(port, SCFCR);
2326 if (reg->size)
2327 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
2328
2329 sci_clear_SCxSR(port,
2330 SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) &
2331 SCxSR_BREAK_CLEAR(port));
2332 if (sci_getreg(port, SCLSR)->size) {
2333 status = serial_port_in(port, SCLSR);
2334 status &= ~(SCLSR_TO | SCLSR_ORER);
2335 serial_port_out(port, SCLSR, status);
2336 }
2337
2338 if (s->rx_trigger > 1) {
2339 if (s->rx_fifo_timeout) {
2340 scif_set_rtrg(port, 1);
2341 timer_setup(&s->rx_fifo_timer, rx_fifo_timer_fn, 0);
2342 } else {
2343 if (port->type == PORT_SCIFA ||
2344 port->type == PORT_SCIFB)
2345 scif_set_rtrg(port, 1);
2346 else
2347 scif_set_rtrg(port, s->rx_trigger);
2348 }
2349 }
2350 }
2351
2352 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
2353 struct ktermios *old)
2354 {
2355 unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i, bits;
2356 unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0;
2357 unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0;
2358 struct sci_port *s = to_sci_port(port);
2359 const struct plat_sci_reg *reg;
2360 int min_err = INT_MAX, err;
2361 unsigned long max_freq = 0;
2362 int best_clk = -1;
2363 unsigned long flags;
2364
2365 if ((termios->c_cflag & CSIZE) == CS7)
2366 smr_val |= SCSMR_CHR;
2367 if (termios->c_cflag & PARENB)
2368 smr_val |= SCSMR_PE;
2369 if (termios->c_cflag & PARODD)
2370 smr_val |= SCSMR_PE | SCSMR_ODD;
2371 if (termios->c_cflag & CSTOPB)
2372 smr_val |= SCSMR_STOP;
2373
2374 /*
2375 * earlyprintk comes here early on with port->uartclk set to zero.
2376 * the clock framework is not up and running at this point so here
2377 * we assume that 115200 is the maximum baud rate. please note that
2378 * the baud rate is not programmed during earlyprintk - it is assumed
2379 * that the previous boot loader has enabled required clocks and
2380 * setup the baud rate generator hardware for us already.
2381 */
2382 if (!port->uartclk) {
2383 baud = uart_get_baud_rate(port, termios, old, 0, 115200);
2384 goto done;
2385 }
2386
2387 for (i = 0; i < SCI_NUM_CLKS; i++)
2388 max_freq = max(max_freq, s->clk_rates[i]);
2389
2390 baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s));
2391 if (!baud)
2392 goto done;
2393
2394 /*
2395 * There can be multiple sources for the sampling clock. Find the one
2396 * that gives us the smallest deviation from the desired baud rate.
2397 */
2398
2399 /* Optional Undivided External Clock */
2400 if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA &&
2401 port->type != PORT_SCIFB) {
2402 err = sci_sck_calc(s, baud, &srr1);
2403 if (abs(err) < abs(min_err)) {
2404 best_clk = SCI_SCK;
2405 scr_val = SCSCR_CKE1;
2406 sccks = SCCKS_CKS;
2407 min_err = err;
2408 srr = srr1;
2409 if (!err)
2410 goto done;
2411 }
2412 }
2413
2414 /* Optional BRG Frequency Divided External Clock */
2415 if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) {
2416 err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1,
2417 &srr1);
2418 if (abs(err) < abs(min_err)) {
2419 best_clk = SCI_SCIF_CLK;
2420 scr_val = SCSCR_CKE1;
2421 sccks = 0;
2422 min_err = err;
2423 dl = dl1;
2424 srr = srr1;
2425 if (!err)
2426 goto done;
2427 }
2428 }
2429
2430 /* Optional BRG Frequency Divided Internal Clock */
2431 if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) {
2432 err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1,
2433 &srr1);
2434 if (abs(err) < abs(min_err)) {
2435 best_clk = SCI_BRG_INT;
2436 scr_val = SCSCR_CKE1;
2437 sccks = SCCKS_XIN;
2438 min_err = err;
2439 dl = dl1;
2440 srr = srr1;
2441 if (!min_err)
2442 goto done;
2443 }
2444 }
2445
2446 /* Divided Functional Clock using standard Bit Rate Register */
2447 err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1);
2448 if (abs(err) < abs(min_err)) {
2449 best_clk = SCI_FCK;
2450 scr_val = 0;
2451 min_err = err;
2452 brr = brr1;
2453 srr = srr1;
2454 cks = cks1;
2455 }
2456
2457 done:
2458 if (best_clk >= 0)
2459 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n",
2460 s->clks[best_clk], baud, min_err);
2461
2462 sci_port_enable(s);
2463
2464 /*
2465 * Program the optional External Baud Rate Generator (BRG) first.
2466 * It controls the mux to select (H)SCK or frequency divided clock.
2467 */
2468 if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) {
2469 serial_port_out(port, SCDL, dl);
2470 serial_port_out(port, SCCKS, sccks);
2471 }
2472
2473 spin_lock_irqsave(&port->lock, flags);
2474
2475 sci_reset(port);
2476
2477 uart_update_timeout(port, termios->c_cflag, baud);
2478
2479 /* byte size and parity */
2480 switch (termios->c_cflag & CSIZE) {
2481 case CS5:
2482 bits = 7;
2483 break;
2484 case CS6:
2485 bits = 8;
2486 break;
2487 case CS7:
2488 bits = 9;
2489 break;
2490 default:
2491 bits = 10;
2492 break;
2493 }
2494
2495 if (termios->c_cflag & CSTOPB)
2496 bits++;
2497 if (termios->c_cflag & PARENB)
2498 bits++;
2499
2500 if (best_clk >= 0) {
2501 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
2502 switch (srr + 1) {
2503 case 5: smr_val |= SCSMR_SRC_5; break;
2504 case 7: smr_val |= SCSMR_SRC_7; break;
2505 case 11: smr_val |= SCSMR_SRC_11; break;
2506 case 13: smr_val |= SCSMR_SRC_13; break;
2507 case 16: smr_val |= SCSMR_SRC_16; break;
2508 case 17: smr_val |= SCSMR_SRC_17; break;
2509 case 19: smr_val |= SCSMR_SRC_19; break;
2510 case 27: smr_val |= SCSMR_SRC_27; break;
2511 }
2512 smr_val |= cks;
2513 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
2514 serial_port_out(port, SCSMR, smr_val);
2515 serial_port_out(port, SCBRR, brr);
2516 if (sci_getreg(port, HSSRR)->size) {
2517 unsigned int hssrr = srr | HSCIF_SRE;
2518 /* Calculate deviation from intended rate at the
2519 * center of the last stop bit in sampling clocks.
2520 */
2521 int last_stop = bits * 2 - 1;
2522 int deviation = DIV_ROUND_CLOSEST(min_err * last_stop *
2523 (int)(srr + 1),
2524 2 * (int)baud);
2525
2526 if (abs(deviation) >= 2) {
2527 /* At least two sampling clocks off at the
2528 * last stop bit; we can increase the error
2529 * margin by shifting the sampling point.
2530 */
2531 int shift = clamp(deviation / 2, -8, 7);
2532
2533 hssrr |= (shift << HSCIF_SRHP_SHIFT) &
2534 HSCIF_SRHP_MASK;
2535 hssrr |= HSCIF_SRDE;
2536 }
2537 serial_port_out(port, HSSRR, hssrr);
2538 }
2539
2540 /* Wait one bit interval */
2541 udelay((1000000 + (baud - 1)) / baud);
2542 } else {
2543 /* Don't touch the bit rate configuration */
2544 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0);
2545 smr_val |= serial_port_in(port, SCSMR) &
2546 (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS);
2547 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
2548 serial_port_out(port, SCSMR, smr_val);
2549 }
2550
2551 sci_init_pins(port, termios->c_cflag);
2552
2553 port->status &= ~UPSTAT_AUTOCTS;
2554 s->autorts = false;
2555 reg = sci_getreg(port, SCFCR);
2556 if (reg->size) {
2557 unsigned short ctrl = serial_port_in(port, SCFCR);
2558
2559 if ((port->flags & UPF_HARD_FLOW) &&
2560 (termios->c_cflag & CRTSCTS)) {
2561 /* There is no CTS interrupt to restart the hardware */
2562 port->status |= UPSTAT_AUTOCTS;
2563 /* MCE is enabled when RTS is raised */
2564 s->autorts = true;
2565 }
2566
2567 /*
2568 * As we've done a sci_reset() above, ensure we don't
2569 * interfere with the FIFOs while toggling MCE. As the
2570 * reset values could still be set, simply mask them out.
2571 */
2572 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
2573
2574 serial_port_out(port, SCFCR, ctrl);
2575 }
2576 if (port->flags & UPF_HARD_FLOW) {
2577 /* Refresh (Auto) RTS */
2578 sci_set_mctrl(port, port->mctrl);
2579 }
2580
2581 scr_val |= SCSCR_RE | SCSCR_TE |
2582 (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0));
2583 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
2584 if ((srr + 1 == 5) &&
2585 (port->type == PORT_SCIFA || port->type == PORT_SCIFB)) {
2586 /*
2587 * In asynchronous mode, when the sampling rate is 1/5, first
2588 * received data may become invalid on some SCIFA and SCIFB.
2589 * To avoid this problem wait more than 1 serial data time (1
2590 * bit time x serial data number) after setting SCSCR.RE = 1.
2591 */
2592 udelay(DIV_ROUND_UP(10 * 1000000, baud));
2593 }
2594
2595 /*
2596 * Calculate delay for 2 DMA buffers (4 FIFO).
2597 * See serial_core.c::uart_update_timeout().
2598 * With 10 bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above
2599 * function calculates 1 jiffie for the data plus 5 jiffies for the
2600 * "slop(e)." Then below we calculate 5 jiffies (20ms) for 2 DMA
2601 * buffers (4 FIFO sizes), but when performing a faster transfer, the
2602 * value obtained by this formula is too small. Therefore, if the value
2603 * is smaller than 20ms, use 20ms as the timeout value for DMA.
2604 */
2605 s->rx_frame = (10000 * bits) / (baud / 100);
2606 #ifdef CONFIG_SERIAL_SH_SCI_DMA
2607 s->rx_timeout = s->buf_len_rx * 2 * s->rx_frame;
2608 if (s->rx_timeout < 20)
2609 s->rx_timeout = 20;
2610 #endif
2611
2612 if ((termios->c_cflag & CREAD) != 0)
2613 sci_start_rx(port);
2614
2615 spin_unlock_irqrestore(&port->lock, flags);
2616
2617 sci_port_disable(s);
2618
2619 if (UART_ENABLE_MS(port, termios->c_cflag))
2620 sci_enable_ms(port);
2621 }
2622
2623 static void sci_pm(struct uart_port *port, unsigned int state,
2624 unsigned int oldstate)
2625 {
2626 struct sci_port *sci_port = to_sci_port(port);
2627
2628 switch (state) {
2629 case UART_PM_STATE_OFF:
2630 sci_port_disable(sci_port);
2631 break;
2632 default:
2633 sci_port_enable(sci_port);
2634 break;
2635 }
2636 }
2637
2638 static const char *sci_type(struct uart_port *port)
2639 {
2640 switch (port->type) {
2641 case PORT_IRDA:
2642 return "irda";
2643 case PORT_SCI:
2644 return "sci";
2645 case PORT_SCIF:
2646 return "scif";
2647 case PORT_SCIFA:
2648 return "scifa";
2649 case PORT_SCIFB:
2650 return "scifb";
2651 case PORT_HSCIF:
2652 return "hscif";
2653 }
2654
2655 return NULL;
2656 }
2657
2658 static int sci_remap_port(struct uart_port *port)
2659 {
2660 struct sci_port *sport = to_sci_port(port);
2661
2662 /*
2663 * Nothing to do if there's already an established membase.
2664 */
2665 if (port->membase)
2666 return 0;
2667
2668 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
2669 port->membase = ioremap_nocache(port->mapbase, sport->reg_size);
2670 if (unlikely(!port->membase)) {
2671 dev_err(port->dev, "can't remap port#%d\n", port->line);
2672 return -ENXIO;
2673 }
2674 } else {
2675 /*
2676 * For the simple (and majority of) cases where we don't
2677 * need to do any remapping, just cast the cookie
2678 * directly.
2679 */
2680 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
2681 }
2682
2683 return 0;
2684 }
2685
2686 static void sci_release_port(struct uart_port *port)
2687 {
2688 struct sci_port *sport = to_sci_port(port);
2689
2690 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
2691 iounmap(port->membase);
2692 port->membase = NULL;
2693 }
2694
2695 release_mem_region(port->mapbase, sport->reg_size);
2696 }
2697
2698 static int sci_request_port(struct uart_port *port)
2699 {
2700 struct resource *res;
2701 struct sci_port *sport = to_sci_port(port);
2702 int ret;
2703
2704 res = request_mem_region(port->mapbase, sport->reg_size,
2705 dev_name(port->dev));
2706 if (unlikely(res == NULL)) {
2707 dev_err(port->dev, "request_mem_region failed.");
2708 return -EBUSY;
2709 }
2710
2711 ret = sci_remap_port(port);
2712 if (unlikely(ret != 0)) {
2713 release_resource(res);
2714 return ret;
2715 }
2716
2717 return 0;
2718 }
2719
2720 static void sci_config_port(struct uart_port *port, int flags)
2721 {
2722 if (flags & UART_CONFIG_TYPE) {
2723 struct sci_port *sport = to_sci_port(port);
2724
2725 port->type = sport->cfg->type;
2726 sci_request_port(port);
2727 }
2728 }
2729
2730 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2731 {
2732 if (ser->baud_base < 2400)
2733 /* No paper tape reader for Mitch.. */
2734 return -EINVAL;
2735
2736 return 0;
2737 }
2738
2739 static const struct uart_ops sci_uart_ops = {
2740 .tx_empty = sci_tx_empty,
2741 .set_mctrl = sci_set_mctrl,
2742 .get_mctrl = sci_get_mctrl,
2743 .start_tx = sci_start_tx,
2744 .stop_tx = sci_stop_tx,
2745 .stop_rx = sci_stop_rx,
2746 .enable_ms = sci_enable_ms,
2747 .break_ctl = sci_break_ctl,
2748 .startup = sci_startup,
2749 .shutdown = sci_shutdown,
2750 .flush_buffer = sci_flush_buffer,
2751 .set_termios = sci_set_termios,
2752 .pm = sci_pm,
2753 .type = sci_type,
2754 .release_port = sci_release_port,
2755 .request_port = sci_request_port,
2756 .config_port = sci_config_port,
2757 .verify_port = sci_verify_port,
2758 #ifdef CONFIG_CONSOLE_POLL
2759 .poll_get_char = sci_poll_get_char,
2760 .poll_put_char = sci_poll_put_char,
2761 #endif
2762 };
2763
2764 static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
2765 {
2766 const char *clk_names[] = {
2767 [SCI_FCK] = "fck",
2768 [SCI_SCK] = "sck",
2769 [SCI_BRG_INT] = "brg_int",
2770 [SCI_SCIF_CLK] = "scif_clk",
2771 };
2772 struct clk *clk;
2773 unsigned int i;
2774
2775 if (sci_port->cfg->type == PORT_HSCIF)
2776 clk_names[SCI_SCK] = "hsck";
2777
2778 for (i = 0; i < SCI_NUM_CLKS; i++) {
2779 clk = devm_clk_get(dev, clk_names[i]);
2780 if (PTR_ERR(clk) == -EPROBE_DEFER)
2781 return -EPROBE_DEFER;
2782
2783 if (IS_ERR(clk) && i == SCI_FCK) {
2784 /*
2785 * "fck" used to be called "sci_ick", and we need to
2786 * maintain DT backward compatibility.
2787 */
2788 clk = devm_clk_get(dev, "sci_ick");
2789 if (PTR_ERR(clk) == -EPROBE_DEFER)
2790 return -EPROBE_DEFER;
2791
2792 if (!IS_ERR(clk))
2793 goto found;
2794
2795 /*
2796 * Not all SH platforms declare a clock lookup entry
2797 * for SCI devices, in which case we need to get the
2798 * global "peripheral_clk" clock.
2799 */
2800 clk = devm_clk_get(dev, "peripheral_clk");
2801 if (!IS_ERR(clk))
2802 goto found;
2803
2804 dev_err(dev, "failed to get %s (%ld)\n", clk_names[i],
2805 PTR_ERR(clk));
2806 return PTR_ERR(clk);
2807 }
2808
2809 found:
2810 if (IS_ERR(clk))
2811 dev_dbg(dev, "failed to get %s (%ld)\n", clk_names[i],
2812 PTR_ERR(clk));
2813 else
2814 dev_dbg(dev, "clk %s is %pC rate %lu\n", clk_names[i],
2815 clk, clk_get_rate(clk));
2816 sci_port->clks[i] = IS_ERR(clk) ? NULL : clk;
2817 }
2818 return 0;
2819 }
2820
2821 static const struct sci_port_params *
2822 sci_probe_regmap(const struct plat_sci_port *cfg)
2823 {
2824 unsigned int regtype;
2825
2826 if (cfg->regtype != SCIx_PROBE_REGTYPE)
2827 return &sci_port_params[cfg->regtype];
2828
2829 switch (cfg->type) {
2830 case PORT_SCI:
2831 regtype = SCIx_SCI_REGTYPE;
2832 break;
2833 case PORT_IRDA:
2834 regtype = SCIx_IRDA_REGTYPE;
2835 break;
2836 case PORT_SCIFA:
2837 regtype = SCIx_SCIFA_REGTYPE;
2838 break;
2839 case PORT_SCIFB:
2840 regtype = SCIx_SCIFB_REGTYPE;
2841 break;
2842 case PORT_SCIF:
2843 /*
2844 * The SH-4 is a bit of a misnomer here, although that's
2845 * where this particular port layout originated. This
2846 * configuration (or some slight variation thereof)
2847 * remains the dominant model for all SCIFs.
2848 */
2849 regtype = SCIx_SH4_SCIF_REGTYPE;
2850 break;
2851 case PORT_HSCIF:
2852 regtype = SCIx_HSCIF_REGTYPE;
2853 break;
2854 default:
2855 pr_err("Can't probe register map for given port\n");
2856 return NULL;
2857 }
2858
2859 return &sci_port_params[regtype];
2860 }
2861
2862 static int sci_init_single(struct platform_device *dev,
2863 struct sci_port *sci_port, unsigned int index,
2864 const struct plat_sci_port *p, bool early)
2865 {
2866 struct uart_port *port = &sci_port->port;
2867 const struct resource *res;
2868 unsigned int i;
2869 int ret;
2870
2871 sci_port->cfg = p;
2872
2873 port->ops = &sci_uart_ops;
2874 port->iotype = UPIO_MEM;
2875 port->line = index;
2876
2877 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2878 if (res == NULL)
2879 return -ENOMEM;
2880
2881 port->mapbase = res->start;
2882 sci_port->reg_size = resource_size(res);
2883
2884 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i)
2885 sci_port->irqs[i] = platform_get_irq(dev, i);
2886
2887 /* The SCI generates several interrupts. They can be muxed together or
2888 * connected to different interrupt lines. In the muxed case only one
2889 * interrupt resource is specified as there is only one interrupt ID.
2890 * In the non-muxed case, up to 6 interrupt signals might be generated
2891 * from the SCI, however those signals might have their own individual
2892 * interrupt ID numbers, or muxed together with another interrupt.
2893 */
2894 if (sci_port->irqs[0] < 0)
2895 return -ENXIO;
2896
2897 if (sci_port->irqs[1] < 0)
2898 for (i = 1; i < ARRAY_SIZE(sci_port->irqs); i++)
2899 sci_port->irqs[i] = sci_port->irqs[0];
2900
2901 sci_port->params = sci_probe_regmap(p);
2902 if (unlikely(sci_port->params == NULL))
2903 return -EINVAL;
2904
2905 switch (p->type) {
2906 case PORT_SCIFB:
2907 sci_port->rx_trigger = 48;
2908 break;
2909 case PORT_HSCIF:
2910 sci_port->rx_trigger = 64;
2911 break;
2912 case PORT_SCIFA:
2913 sci_port->rx_trigger = 32;
2914 break;
2915 case PORT_SCIF:
2916 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE)
2917 /* RX triggering not implemented for this IP */
2918 sci_port->rx_trigger = 1;
2919 else
2920 sci_port->rx_trigger = 8;
2921 break;
2922 default:
2923 sci_port->rx_trigger = 1;
2924 break;
2925 }
2926
2927 sci_port->rx_fifo_timeout = 0;
2928 sci_port->hscif_tot = 0;
2929
2930 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
2931 * match the SoC datasheet, this should be investigated. Let platform
2932 * data override the sampling rate for now.
2933 */
2934 sci_port->sampling_rate_mask = p->sampling_rate
2935 ? SCI_SR(p->sampling_rate)
2936 : sci_port->params->sampling_rate_mask;
2937
2938 if (!early) {
2939 ret = sci_init_clocks(sci_port, &dev->dev);
2940 if (ret < 0)
2941 return ret;
2942
2943 port->dev = &dev->dev;
2944
2945 pm_runtime_enable(&dev->dev);
2946 }
2947
2948 port->type = p->type;
2949 port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags;
2950 port->fifosize = sci_port->params->fifosize;
2951
2952 if (port->type == PORT_SCI) {
2953 if (sci_port->reg_size >= 0x20)
2954 port->regshift = 2;
2955 else
2956 port->regshift = 1;
2957 }
2958
2959 /*
2960 * The UART port needs an IRQ value, so we peg this to the RX IRQ
2961 * for the multi-IRQ ports, which is where we are primarily
2962 * concerned with the shutdown path synchronization.
2963 *
2964 * For the muxed case there's nothing more to do.
2965 */
2966 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
2967 port->irqflags = 0;
2968
2969 port->serial_in = sci_serial_in;
2970 port->serial_out = sci_serial_out;
2971
2972 return 0;
2973 }
2974
2975 static void sci_cleanup_single(struct sci_port *port)
2976 {
2977 pm_runtime_disable(port->port.dev);
2978 }
2979
2980 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
2981 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
2982 static void serial_console_putchar(struct uart_port *port, int ch)
2983 {
2984 sci_poll_put_char(port, ch);
2985 }
2986
2987 /*
2988 * Print a string to the serial port trying not to disturb
2989 * any possible real use of the port...
2990 */
2991 static void serial_console_write(struct console *co, const char *s,
2992 unsigned count)
2993 {
2994 struct sci_port *sci_port = &sci_ports[co->index];
2995 struct uart_port *port = &sci_port->port;
2996 unsigned short bits, ctrl, ctrl_temp;
2997 unsigned long flags;
2998 int locked = 1;
2999
3000 #if defined(SUPPORT_SYSRQ)
3001 if (port->sysrq)
3002 locked = 0;
3003 else
3004 #endif
3005 if (oops_in_progress)
3006 locked = spin_trylock_irqsave(&port->lock, flags);
3007 else
3008 spin_lock_irqsave(&port->lock, flags);
3009
3010 /* first save SCSCR then disable interrupts, keep clock source */
3011 ctrl = serial_port_in(port, SCSCR);
3012 ctrl_temp = SCSCR_RE | SCSCR_TE |
3013 (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) |
3014 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0));
3015 serial_port_out(port, SCSCR, ctrl_temp | sci_port->hscif_tot);
3016
3017 uart_console_write(port, s, count, serial_console_putchar);
3018
3019 /* wait until fifo is empty and last bit has been transmitted */
3020 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
3021 while ((serial_port_in(port, SCxSR) & bits) != bits)
3022 cpu_relax();
3023
3024 /* restore the SCSCR */
3025 serial_port_out(port, SCSCR, ctrl);
3026
3027 if (locked)
3028 spin_unlock_irqrestore(&port->lock, flags);
3029 }
3030
3031 static int serial_console_setup(struct console *co, char *options)
3032 {
3033 struct sci_port *sci_port;
3034 struct uart_port *port;
3035 int baud = 115200;
3036 int bits = 8;
3037 int parity = 'n';
3038 int flow = 'n';
3039 int ret;
3040
3041 /*
3042 * Refuse to handle any bogus ports.
3043 */
3044 if (co->index < 0 || co->index >= SCI_NPORTS)
3045 return -ENODEV;
3046
3047 sci_port = &sci_ports[co->index];
3048 port = &sci_port->port;
3049
3050 /*
3051 * Refuse to handle uninitialized ports.
3052 */
3053 if (!port->ops)
3054 return -ENODEV;
3055
3056 ret = sci_remap_port(port);
3057 if (unlikely(ret != 0))
3058 return ret;
3059
3060 if (options)
3061 uart_parse_options(options, &baud, &parity, &bits, &flow);
3062
3063 return uart_set_options(port, co, baud, parity, bits, flow);
3064 }
3065
3066 static struct console serial_console = {
3067 .name = "ttySC",
3068 .device = uart_console_device,
3069 .write = serial_console_write,
3070 .setup = serial_console_setup,
3071 .flags = CON_PRINTBUFFER,
3072 .index = -1,
3073 .data = &sci_uart_driver,
3074 };
3075
3076 static struct console early_serial_console = {
3077 .name = "early_ttySC",
3078 .write = serial_console_write,
3079 .flags = CON_PRINTBUFFER,
3080 .index = -1,
3081 };
3082
3083 static char early_serial_buf[32];
3084
3085 static int sci_probe_earlyprintk(struct platform_device *pdev)
3086 {
3087 const struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
3088
3089 if (early_serial_console.data)
3090 return -EEXIST;
3091
3092 early_serial_console.index = pdev->id;
3093
3094 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
3095
3096 serial_console_setup(&early_serial_console, early_serial_buf);
3097
3098 if (!strstr(early_serial_buf, "keep"))
3099 early_serial_console.flags |= CON_BOOT;
3100
3101 register_console(&early_serial_console);
3102 return 0;
3103 }
3104
3105 #define SCI_CONSOLE (&serial_console)
3106
3107 #else
3108 static inline int sci_probe_earlyprintk(struct platform_device *pdev)
3109 {
3110 return -EINVAL;
3111 }
3112
3113 #define SCI_CONSOLE NULL
3114
3115 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE || CONFIG_SERIAL_SH_SCI_EARLYCON */
3116
3117 static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
3118
3119 static DEFINE_MUTEX(sci_uart_registration_lock);
3120 static struct uart_driver sci_uart_driver = {
3121 .owner = THIS_MODULE,
3122 .driver_name = "sci",
3123 .dev_name = "ttySC",
3124 .major = SCI_MAJOR,
3125 .minor = SCI_MINOR_START,
3126 .nr = SCI_NPORTS,
3127 .cons = SCI_CONSOLE,
3128 };
3129
3130 static int sci_remove(struct platform_device *dev)
3131 {
3132 struct sci_port *port = platform_get_drvdata(dev);
3133 unsigned int type = port->port.type; /* uart_remove_... clears it */
3134
3135 sci_ports_in_use &= ~BIT(port->port.line);
3136 uart_remove_one_port(&sci_uart_driver, &port->port);
3137
3138 sci_cleanup_single(port);
3139
3140 if (port->port.fifosize > 1) {
3141 sysfs_remove_file(&dev->dev.kobj,
3142 &dev_attr_rx_fifo_trigger.attr);
3143 }
3144 if (type == PORT_SCIFA || type == PORT_SCIFB || type == PORT_HSCIF) {
3145 sysfs_remove_file(&dev->dev.kobj,
3146 &dev_attr_rx_fifo_timeout.attr);
3147 }
3148
3149 return 0;
3150 }
3151
3152
3153 #define SCI_OF_DATA(type, regtype) (void *)((type) << 16 | (regtype))
3154 #define SCI_OF_TYPE(data) ((unsigned long)(data) >> 16)
3155 #define SCI_OF_REGTYPE(data) ((unsigned long)(data) & 0xffff)
3156
3157 static const struct of_device_id of_sci_match[] = {
3158 /* SoC-specific types */
3159 {
3160 .compatible = "renesas,scif-r7s72100",
3161 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE),
3162 },
3163 {
3164 .compatible = "renesas,scif-r7s9210",
3165 .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE),
3166 },
3167 /* Family-specific types */
3168 {
3169 .compatible = "renesas,rcar-gen1-scif",
3170 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3171 }, {
3172 .compatible = "renesas,rcar-gen2-scif",
3173 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3174 }, {
3175 .compatible = "renesas,rcar-gen3-scif",
3176 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3177 },
3178 /* Generic types */
3179 {
3180 .compatible = "renesas,scif",
3181 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_REGTYPE),
3182 }, {
3183 .compatible = "renesas,scifa",
3184 .data = SCI_OF_DATA(PORT_SCIFA, SCIx_SCIFA_REGTYPE),
3185 }, {
3186 .compatible = "renesas,scifb",
3187 .data = SCI_OF_DATA(PORT_SCIFB, SCIx_SCIFB_REGTYPE),
3188 }, {
3189 .compatible = "renesas,hscif",
3190 .data = SCI_OF_DATA(PORT_HSCIF, SCIx_HSCIF_REGTYPE),
3191 }, {
3192 .compatible = "renesas,sci",
3193 .data = SCI_OF_DATA(PORT_SCI, SCIx_SCI_REGTYPE),
3194 }, {
3195 /* Terminator */
3196 },
3197 };
3198 MODULE_DEVICE_TABLE(of, of_sci_match);
3199
3200 static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev,
3201 unsigned int *dev_id)
3202 {
3203 struct device_node *np = pdev->dev.of_node;
3204 struct plat_sci_port *p;
3205 struct sci_port *sp;
3206 const void *data;
3207 int id;
3208
3209 if (!IS_ENABLED(CONFIG_OF) || !np)
3210 return NULL;
3211
3212 data = of_device_get_match_data(&pdev->dev);
3213
3214 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
3215 if (!p)
3216 return NULL;
3217
3218 /* Get the line number from the aliases node. */
3219 id = of_alias_get_id(np, "serial");
3220 if (id < 0 && ~sci_ports_in_use)
3221 id = ffz(sci_ports_in_use);
3222 if (id < 0) {
3223 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
3224 return NULL;
3225 }
3226 if (id >= ARRAY_SIZE(sci_ports)) {
3227 dev_err(&pdev->dev, "serial%d out of range\n", id);
3228 return NULL;
3229 }
3230
3231 sp = &sci_ports[id];
3232 *dev_id = id;
3233
3234 p->type = SCI_OF_TYPE(data);
3235 p->regtype = SCI_OF_REGTYPE(data);
3236
3237 sp->has_rtscts = of_property_read_bool(np, "uart-has-rtscts");
3238
3239 return p;
3240 }
3241
3242 static int sci_probe_single(struct platform_device *dev,
3243 unsigned int index,
3244 struct plat_sci_port *p,
3245 struct sci_port *sciport)
3246 {
3247 int ret;
3248
3249 /* Sanity check */
3250 if (unlikely(index >= SCI_NPORTS)) {
3251 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
3252 index+1, SCI_NPORTS);
3253 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
3254 return -EINVAL;
3255 }
3256 BUILD_BUG_ON(SCI_NPORTS > sizeof(sci_ports_in_use) * 8);
3257 if (sci_ports_in_use & BIT(index))
3258 return -EBUSY;
3259
3260 mutex_lock(&sci_uart_registration_lock);
3261 if (!sci_uart_driver.state) {
3262 ret = uart_register_driver(&sci_uart_driver);
3263 if (ret) {
3264 mutex_unlock(&sci_uart_registration_lock);
3265 return ret;
3266 }
3267 }
3268 mutex_unlock(&sci_uart_registration_lock);
3269
3270 ret = sci_init_single(dev, sciport, index, p, false);
3271 if (ret)
3272 return ret;
3273
3274 sciport->gpios = mctrl_gpio_init(&sciport->port, 0);
3275 if (IS_ERR(sciport->gpios) && PTR_ERR(sciport->gpios) != -ENOSYS)
3276 return PTR_ERR(sciport->gpios);
3277
3278 if (sciport->has_rtscts) {
3279 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(sciport->gpios,
3280 UART_GPIO_CTS)) ||
3281 !IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(sciport->gpios,
3282 UART_GPIO_RTS))) {
3283 dev_err(&dev->dev, "Conflicting RTS/CTS config\n");
3284 return -EINVAL;
3285 }
3286 sciport->port.flags |= UPF_HARD_FLOW;
3287 }
3288
3289 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
3290 if (ret) {
3291 sci_cleanup_single(sciport);
3292 return ret;
3293 }
3294
3295 return 0;
3296 }
3297
3298 static int sci_probe(struct platform_device *dev)
3299 {
3300 struct plat_sci_port *p;
3301 struct sci_port *sp;
3302 unsigned int dev_id;
3303 int ret;
3304
3305 /*
3306 * If we've come here via earlyprintk initialization, head off to
3307 * the special early probe. We don't have sufficient device state
3308 * to make it beyond this yet.
3309 */
3310 if (is_early_platform_device(dev))
3311 return sci_probe_earlyprintk(dev);
3312
3313 if (dev->dev.of_node) {
3314 p = sci_parse_dt(dev, &dev_id);
3315 if (p == NULL)
3316 return -EINVAL;
3317 } else {
3318 p = dev->dev.platform_data;
3319 if (p == NULL) {
3320 dev_err(&dev->dev, "no platform data supplied\n");
3321 return -EINVAL;
3322 }
3323
3324 dev_id = dev->id;
3325 }
3326
3327 sp = &sci_ports[dev_id];
3328 platform_set_drvdata(dev, sp);
3329
3330 ret = sci_probe_single(dev, dev_id, p, sp);
3331 if (ret)
3332 return ret;
3333
3334 if (sp->port.fifosize > 1) {
3335 ret = sysfs_create_file(&dev->dev.kobj,
3336 &dev_attr_rx_fifo_trigger.attr);
3337 if (ret)
3338 return ret;
3339 }
3340 if (sp->port.type == PORT_SCIFA || sp->port.type == PORT_SCIFB ||
3341 sp->port.type == PORT_HSCIF) {
3342 ret = sysfs_create_file(&dev->dev.kobj,
3343 &dev_attr_rx_fifo_timeout.attr);
3344 if (ret) {
3345 if (sp->port.fifosize > 1) {
3346 sysfs_remove_file(&dev->dev.kobj,
3347 &dev_attr_rx_fifo_trigger.attr);
3348 }
3349 return ret;
3350 }
3351 }
3352
3353 #ifdef CONFIG_SH_STANDARD_BIOS
3354 sh_bios_gdb_detach();
3355 #endif
3356
3357 sci_ports_in_use |= BIT(dev_id);
3358 return 0;
3359 }
3360
3361 static __maybe_unused int sci_suspend(struct device *dev)
3362 {
3363 struct sci_port *sport = dev_get_drvdata(dev);
3364
3365 if (sport)
3366 uart_suspend_port(&sci_uart_driver, &sport->port);
3367
3368 return 0;
3369 }
3370
3371 static __maybe_unused int sci_resume(struct device *dev)
3372 {
3373 struct sci_port *sport = dev_get_drvdata(dev);
3374
3375 if (sport)
3376 uart_resume_port(&sci_uart_driver, &sport->port);
3377
3378 return 0;
3379 }
3380
3381 static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
3382
3383 static struct platform_driver sci_driver = {
3384 .probe = sci_probe,
3385 .remove = sci_remove,
3386 .driver = {
3387 .name = "sh-sci",
3388 .pm = &sci_dev_pm_ops,
3389 .of_match_table = of_match_ptr(of_sci_match),
3390 },
3391 };
3392
3393 static int __init sci_init(void)
3394 {
3395 pr_info("%s\n", banner);
3396
3397 return platform_driver_register(&sci_driver);
3398 }
3399
3400 static void __exit sci_exit(void)
3401 {
3402 platform_driver_unregister(&sci_driver);
3403
3404 if (sci_uart_driver.state)
3405 uart_unregister_driver(&sci_uart_driver);
3406 }
3407
3408 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
3409 early_platform_init_buffer("earlyprintk", &sci_driver,
3410 early_serial_buf, ARRAY_SIZE(early_serial_buf));
3411 #endif
3412 #ifdef CONFIG_SERIAL_SH_SCI_EARLYCON
3413 static struct plat_sci_port port_cfg __initdata;
3414
3415 static int __init early_console_setup(struct earlycon_device *device,
3416 int type)
3417 {
3418 if (!device->port.membase)
3419 return -ENODEV;
3420
3421 device->port.serial_in = sci_serial_in;
3422 device->port.serial_out = sci_serial_out;
3423 device->port.type = type;
3424 memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port));
3425 port_cfg.type = type;
3426 sci_ports[0].cfg = &port_cfg;
3427 sci_ports[0].params = sci_probe_regmap(&port_cfg);
3428 port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR);
3429 sci_serial_out(&sci_ports[0].port, SCSCR,
3430 SCSCR_RE | SCSCR_TE | port_cfg.scscr);
3431
3432 device->con->write = serial_console_write;
3433 return 0;
3434 }
3435 static int __init sci_early_console_setup(struct earlycon_device *device,
3436 const char *opt)
3437 {
3438 return early_console_setup(device, PORT_SCI);
3439 }
3440 static int __init scif_early_console_setup(struct earlycon_device *device,
3441 const char *opt)
3442 {
3443 return early_console_setup(device, PORT_SCIF);
3444 }
3445 static int __init rzscifa_early_console_setup(struct earlycon_device *device,
3446 const char *opt)
3447 {
3448 port_cfg.regtype = SCIx_RZ_SCIFA_REGTYPE;
3449 return early_console_setup(device, PORT_SCIF);
3450 }
3451 static int __init scifa_early_console_setup(struct earlycon_device *device,
3452 const char *opt)
3453 {
3454 return early_console_setup(device, PORT_SCIFA);
3455 }
3456 static int __init scifb_early_console_setup(struct earlycon_device *device,
3457 const char *opt)
3458 {
3459 return early_console_setup(device, PORT_SCIFB);
3460 }
3461 static int __init hscif_early_console_setup(struct earlycon_device *device,
3462 const char *opt)
3463 {
3464 return early_console_setup(device, PORT_HSCIF);
3465 }
3466
3467 OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup);
3468 OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup);
3469 OF_EARLYCON_DECLARE(scif, "renesas,scif-r7s9210", rzscifa_early_console_setup);
3470 OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup);
3471 OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup);
3472 OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup);
3473 #endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */
3474
3475 module_init(sci_init);
3476 module_exit(sci_exit);
3477
3478 MODULE_LICENSE("GPL");
3479 MODULE_ALIAS("platform:sh-sci");
3480 MODULE_AUTHOR("Paul Mundt");
3481 MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");
Linux with added FPC-III support