?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
staging: erofs: integrate decompression inplace
[linux/fpc-iii.git] / drivers / tty / serial / uartlite.c
blobb8b912b5a8b992bcb6bcf2ddd3e5703ca00dd2ae
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * uartlite.c: Serial driver for Xilinx uartlite serial controller
4 *
5 * Copyright (C) 2006 Peter Korsgaard <jacmet@sunsite.dk>
6 * Copyright (C) 2007 Secret Lab Technologies Ltd.
7 */
8
9 #include <linux/platform_device.h>
10 #include <linux/module.h>
11 #include <linux/console.h>
12 #include <linux/serial.h>
13 #include <linux/serial_core.h>
14 #include <linux/tty.h>
15 #include <linux/tty_flip.h>
16 #include <linux/delay.h>
17 #include <linux/interrupt.h>
18 #include <linux/init.h>
19 #include <linux/io.h>
20 #include <linux/of.h>
21 #include <linux/of_address.h>
22 #include <linux/of_device.h>
23 #include <linux/of_platform.h>
24 #include <linux/clk.h>
25 #include <linux/pm_runtime.h>
26
27 #define ULITE_NAME "ttyUL"
28 #define ULITE_MAJOR 204
29 #define ULITE_MINOR 187
30 #define ULITE_NR_UARTS CONFIG_SERIAL_UARTLITE_NR_UARTS
31
32 /* ---------------------------------------------------------------------
33 * Register definitions
34 *
35 * For register details see datasheet:
36 * http://www.xilinx.com/support/documentation/ip_documentation/opb_uartlite.pdf
37 */
38
39 #define ULITE_RX 0x00
40 #define ULITE_TX 0x04
41 #define ULITE_STATUS 0x08
42 #define ULITE_CONTROL 0x0c
43
44 #define ULITE_REGION 16
45
46 #define ULITE_STATUS_RXVALID 0x01
47 #define ULITE_STATUS_RXFULL 0x02
48 #define ULITE_STATUS_TXEMPTY 0x04
49 #define ULITE_STATUS_TXFULL 0x08
50 #define ULITE_STATUS_IE 0x10
51 #define ULITE_STATUS_OVERRUN 0x20
52 #define ULITE_STATUS_FRAME 0x40
53 #define ULITE_STATUS_PARITY 0x80
54
55 #define ULITE_CONTROL_RST_TX 0x01
56 #define ULITE_CONTROL_RST_RX 0x02
57 #define ULITE_CONTROL_IE 0x10
58 #define UART_AUTOSUSPEND_TIMEOUT 3000
59
60 /* Static pointer to console port */
61 #ifdef CONFIG_SERIAL_UARTLITE_CONSOLE
62 static struct uart_port *console_port;
63 #endif
64
65 struct uartlite_data {
66 const struct uartlite_reg_ops *reg_ops;
67 struct clk *clk;
68 struct uart_driver *ulite_uart_driver;
69 };
70
71 struct uartlite_reg_ops {
72 u32 (*in)(void __iomem *addr);
73 void (*out)(u32 val, void __iomem *addr);
74 };
75
76 static u32 uartlite_inbe32(void __iomem *addr)
77 {
78 return ioread32be(addr);
79 }
80
81 static void uartlite_outbe32(u32 val, void __iomem *addr)
82 {
83 iowrite32be(val, addr);
84 }
85
86 static const struct uartlite_reg_ops uartlite_be = {
87 .in = uartlite_inbe32,
88 .out = uartlite_outbe32,
89 };
90
91 static u32 uartlite_inle32(void __iomem *addr)
92 {
93 return ioread32(addr);
94 }
95
96 static void uartlite_outle32(u32 val, void __iomem *addr)
97 {
98 iowrite32(val, addr);
99 }
100
101 static const struct uartlite_reg_ops uartlite_le = {
102 .in = uartlite_inle32,
103 .out = uartlite_outle32,
104 };
105
106 static inline u32 uart_in32(u32 offset, struct uart_port *port)
107 {
108 struct uartlite_data *pdata = port->private_data;
109
110 return pdata->reg_ops->in(port->membase + offset);
111 }
112
113 static inline void uart_out32(u32 val, u32 offset, struct uart_port *port)
114 {
115 struct uartlite_data *pdata = port->private_data;
116
117 pdata->reg_ops->out(val, port->membase + offset);
118 }
119
120 static struct uart_port ulite_ports[ULITE_NR_UARTS];
121
122 /* ---------------------------------------------------------------------
123 * Core UART driver operations
124 */
125
126 static int ulite_receive(struct uart_port *port, int stat)
127 {
128 struct tty_port *tport = &port->state->port;
129 unsigned char ch = 0;
130 char flag = TTY_NORMAL;
131
132 if ((stat & (ULITE_STATUS_RXVALID | ULITE_STATUS_OVERRUN
133 | ULITE_STATUS_FRAME)) == 0)
134 return 0;
135
136 /* stats */
137 if (stat & ULITE_STATUS_RXVALID) {
138 port->icount.rx++;
139 ch = uart_in32(ULITE_RX, port);
140
141 if (stat & ULITE_STATUS_PARITY)
142 port->icount.parity++;
143 }
144
145 if (stat & ULITE_STATUS_OVERRUN)
146 port->icount.overrun++;
147
148 if (stat & ULITE_STATUS_FRAME)
149 port->icount.frame++;
150
151
152 /* drop byte with parity error if IGNPAR specificed */
153 if (stat & port->ignore_status_mask & ULITE_STATUS_PARITY)
154 stat &= ~ULITE_STATUS_RXVALID;
155
156 stat &= port->read_status_mask;
157
158 if (stat & ULITE_STATUS_PARITY)
159 flag = TTY_PARITY;
160
161
162 stat &= ~port->ignore_status_mask;
163
164 if (stat & ULITE_STATUS_RXVALID)
165 tty_insert_flip_char(tport, ch, flag);
166
167 if (stat & ULITE_STATUS_FRAME)
168 tty_insert_flip_char(tport, 0, TTY_FRAME);
169
170 if (stat & ULITE_STATUS_OVERRUN)
171 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
172
173 return 1;
174 }
175
176 static int ulite_transmit(struct uart_port *port, int stat)
177 {
178 struct circ_buf *xmit = &port->state->xmit;
179
180 if (stat & ULITE_STATUS_TXFULL)
181 return 0;
182
183 if (port->x_char) {
184 uart_out32(port->x_char, ULITE_TX, port);
185 port->x_char = 0;
186 port->icount.tx++;
187 return 1;
188 }
189
190 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
191 return 0;
192
193 uart_out32(xmit->buf[xmit->tail], ULITE_TX, port);
194 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE-1);
195 port->icount.tx++;
196
197 /* wake up */
198 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
199 uart_write_wakeup(port);
200
201 return 1;
202 }
203
204 static irqreturn_t ulite_isr(int irq, void *dev_id)
205 {
206 struct uart_port *port = dev_id;
207 int stat, busy, n = 0;
208 unsigned long flags;
209
210 do {
211 spin_lock_irqsave(&port->lock, flags);
212 stat = uart_in32(ULITE_STATUS, port);
213 busy = ulite_receive(port, stat);
214 busy |= ulite_transmit(port, stat);
215 spin_unlock_irqrestore(&port->lock, flags);
216 n++;
217 } while (busy);
218
219 /* work done? */
220 if (n > 1) {
221 tty_flip_buffer_push(&port->state->port);
222 return IRQ_HANDLED;
223 } else {
224 return IRQ_NONE;
225 }
226 }
227
228 static unsigned int ulite_tx_empty(struct uart_port *port)
229 {
230 unsigned long flags;
231 unsigned int ret;
232
233 spin_lock_irqsave(&port->lock, flags);
234 ret = uart_in32(ULITE_STATUS, port);
235 spin_unlock_irqrestore(&port->lock, flags);
236
237 return ret & ULITE_STATUS_TXEMPTY ? TIOCSER_TEMT : 0;
238 }
239
240 static unsigned int ulite_get_mctrl(struct uart_port *port)
241 {
242 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
243 }
244
245 static void ulite_set_mctrl(struct uart_port *port, unsigned int mctrl)
246 {
247 /* N/A */
248 }
249
250 static void ulite_stop_tx(struct uart_port *port)
251 {
252 /* N/A */
253 }
254
255 static void ulite_start_tx(struct uart_port *port)
256 {
257 ulite_transmit(port, uart_in32(ULITE_STATUS, port));
258 }
259
260 static void ulite_stop_rx(struct uart_port *port)
261 {
262 /* don't forward any more data (like !CREAD) */
263 port->ignore_status_mask = ULITE_STATUS_RXVALID | ULITE_STATUS_PARITY
264 | ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN;
265 }
266
267 static void ulite_break_ctl(struct uart_port *port, int ctl)
268 {
269 /* N/A */
270 }
271
272 static int ulite_startup(struct uart_port *port)
273 {
274 struct uartlite_data *pdata = port->private_data;
275 int ret;
276
277 ret = clk_enable(pdata->clk);
278 if (ret) {
279 dev_err(port->dev, "Failed to enable clock\n");
280 return ret;
281 }
282
283 ret = request_irq(port->irq, ulite_isr, IRQF_SHARED | IRQF_TRIGGER_RISING,
284 "uartlite", port);
285 if (ret)
286 return ret;
287
288 uart_out32(ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX,
289 ULITE_CONTROL, port);
290 uart_out32(ULITE_CONTROL_IE, ULITE_CONTROL, port);
291
292 return 0;
293 }
294
295 static void ulite_shutdown(struct uart_port *port)
296 {
297 struct uartlite_data *pdata = port->private_data;
298
299 uart_out32(0, ULITE_CONTROL, port);
300 uart_in32(ULITE_CONTROL, port); /* dummy */
301 free_irq(port->irq, port);
302 clk_disable(pdata->clk);
303 }
304
305 static void ulite_set_termios(struct uart_port *port, struct ktermios *termios,
306 struct ktermios *old)
307 {
308 unsigned long flags;
309 unsigned int baud;
310
311 spin_lock_irqsave(&port->lock, flags);
312
313 port->read_status_mask = ULITE_STATUS_RXVALID | ULITE_STATUS_OVERRUN
314 | ULITE_STATUS_TXFULL;
315
316 if (termios->c_iflag & INPCK)
317 port->read_status_mask |=
318 ULITE_STATUS_PARITY | ULITE_STATUS_FRAME;
319
320 port->ignore_status_mask = 0;
321 if (termios->c_iflag & IGNPAR)
322 port->ignore_status_mask |= ULITE_STATUS_PARITY
323 | ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN;
324
325 /* ignore all characters if CREAD is not set */
326 if ((termios->c_cflag & CREAD) == 0)
327 port->ignore_status_mask |=
328 ULITE_STATUS_RXVALID | ULITE_STATUS_PARITY
329 | ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN;
330
331 /* update timeout */
332 baud = uart_get_baud_rate(port, termios, old, 0, 460800);
333 uart_update_timeout(port, termios->c_cflag, baud);
334
335 spin_unlock_irqrestore(&port->lock, flags);
336 }
337
338 static const char *ulite_type(struct uart_port *port)
339 {
340 return port->type == PORT_UARTLITE ? "uartlite" : NULL;
341 }
342
343 static void ulite_release_port(struct uart_port *port)
344 {
345 release_mem_region(port->mapbase, ULITE_REGION);
346 iounmap(port->membase);
347 port->membase = NULL;
348 }
349
350 static int ulite_request_port(struct uart_port *port)
351 {
352 struct uartlite_data *pdata = port->private_data;
353 int ret;
354
355 pr_debug("ulite console: port=%p; port->mapbase=%llx\n",
356 port, (unsigned long long) port->mapbase);
357
358 if (!request_mem_region(port->mapbase, ULITE_REGION, "uartlite")) {
359 dev_err(port->dev, "Memory region busy\n");
360 return -EBUSY;
361 }
362
363 port->membase = ioremap(port->mapbase, ULITE_REGION);
364 if (!port->membase) {
365 dev_err(port->dev, "Unable to map registers\n");
366 release_mem_region(port->mapbase, ULITE_REGION);
367 return -EBUSY;
368 }
369
370 pdata->reg_ops = &uartlite_be;
371 ret = uart_in32(ULITE_CONTROL, port);
372 uart_out32(ULITE_CONTROL_RST_TX, ULITE_CONTROL, port);
373 ret = uart_in32(ULITE_STATUS, port);
374 /* Endianess detection */
375 if ((ret & ULITE_STATUS_TXEMPTY) != ULITE_STATUS_TXEMPTY)
376 pdata->reg_ops = &uartlite_le;
377
378 return 0;
379 }
380
381 static void ulite_config_port(struct uart_port *port, int flags)
382 {
383 if (!ulite_request_port(port))
384 port->type = PORT_UARTLITE;
385 }
386
387 static int ulite_verify_port(struct uart_port *port, struct serial_struct *ser)
388 {
389 /* we don't want the core code to modify any port params */
390 return -EINVAL;
391 }
392
393 static void ulite_pm(struct uart_port *port, unsigned int state,
394 unsigned int oldstate)
395 {
396 if (!state) {
397 pm_runtime_get_sync(port->dev);
398 } else {
399 pm_runtime_mark_last_busy(port->dev);
400 pm_runtime_put_autosuspend(port->dev);
401 }
402 }
403
404 #ifdef CONFIG_CONSOLE_POLL
405 static int ulite_get_poll_char(struct uart_port *port)
406 {
407 if (!(uart_in32(ULITE_STATUS, port) & ULITE_STATUS_RXVALID))
408 return NO_POLL_CHAR;
409
410 return uart_in32(ULITE_RX, port);
411 }
412
413 static void ulite_put_poll_char(struct uart_port *port, unsigned char ch)
414 {
415 while (uart_in32(ULITE_STATUS, port) & ULITE_STATUS_TXFULL)
416 cpu_relax();
417
418 /* write char to device */
419 uart_out32(ch, ULITE_TX, port);
420 }
421 #endif
422
423 static const struct uart_ops ulite_ops = {
424 .tx_empty = ulite_tx_empty,
425 .set_mctrl = ulite_set_mctrl,
426 .get_mctrl = ulite_get_mctrl,
427 .stop_tx = ulite_stop_tx,
428 .start_tx = ulite_start_tx,
429 .stop_rx = ulite_stop_rx,
430 .break_ctl = ulite_break_ctl,
431 .startup = ulite_startup,
432 .shutdown = ulite_shutdown,
433 .set_termios = ulite_set_termios,
434 .type = ulite_type,
435 .release_port = ulite_release_port,
436 .request_port = ulite_request_port,
437 .config_port = ulite_config_port,
438 .verify_port = ulite_verify_port,
439 .pm = ulite_pm,
440 #ifdef CONFIG_CONSOLE_POLL
441 .poll_get_char = ulite_get_poll_char,
442 .poll_put_char = ulite_put_poll_char,
443 #endif
444 };
445
446 /* ---------------------------------------------------------------------
447 * Console driver operations
448 */
449
450 #ifdef CONFIG_SERIAL_UARTLITE_CONSOLE
451 static void ulite_console_wait_tx(struct uart_port *port)
452 {
453 u8 val;
454 unsigned long timeout;
455
456 /*
457 * Spin waiting for TX fifo to have space available.
458 * When using the Microblaze Debug Module this can take up to 1s
459 */
460 timeout = jiffies + msecs_to_jiffies(1000);
461 while (1) {
462 val = uart_in32(ULITE_STATUS, port);
463 if ((val & ULITE_STATUS_TXFULL) == 0)
464 break;
465 if (time_after(jiffies, timeout)) {
466 dev_warn(port->dev,
467 "timeout waiting for TX buffer empty\n");
468 break;
469 }
470 cpu_relax();
471 }
472 }
473
474 static void ulite_console_putchar(struct uart_port *port, int ch)
475 {
476 ulite_console_wait_tx(port);
477 uart_out32(ch, ULITE_TX, port);
478 }
479
480 static void ulite_console_write(struct console *co, const char *s,
481 unsigned int count)
482 {
483 struct uart_port *port = console_port;
484 unsigned long flags;
485 unsigned int ier;
486 int locked = 1;
487
488 if (oops_in_progress) {
489 locked = spin_trylock_irqsave(&port->lock, flags);
490 } else
491 spin_lock_irqsave(&port->lock, flags);
492
493 /* save and disable interrupt */
494 ier = uart_in32(ULITE_STATUS, port) & ULITE_STATUS_IE;
495 uart_out32(0, ULITE_CONTROL, port);
496
497 uart_console_write(port, s, count, ulite_console_putchar);
498
499 ulite_console_wait_tx(port);
500
501 /* restore interrupt state */
502 if (ier)
503 uart_out32(ULITE_CONTROL_IE, ULITE_CONTROL, port);
504
505 if (locked)
506 spin_unlock_irqrestore(&port->lock, flags);
507 }
508
509 static int ulite_console_setup(struct console *co, char *options)
510 {
511 struct uart_port *port;
512 int baud = 9600;
513 int bits = 8;
514 int parity = 'n';
515 int flow = 'n';
516
517
518 port = console_port;
519
520 /* Has the device been initialized yet? */
521 if (!port->mapbase) {
522 pr_debug("console on ttyUL%i not present\n", co->index);
523 return -ENODEV;
524 }
525
526 /* not initialized yet? */
527 if (!port->membase) {
528 if (ulite_request_port(port))
529 return -ENODEV;
530 }
531
532 if (options)
533 uart_parse_options(options, &baud, &parity, &bits, &flow);
534
535 return uart_set_options(port, co, baud, parity, bits, flow);
536 }
537
538 static struct uart_driver ulite_uart_driver;
539
540 static struct console ulite_console = {
541 .name = ULITE_NAME,
542 .write = ulite_console_write,
543 .device = uart_console_device,
544 .setup = ulite_console_setup,
545 .flags = CON_PRINTBUFFER,
546 .index = -1, /* Specified on the cmdline (e.g. console=ttyUL0 ) */
547 .data = &ulite_uart_driver,
548 };
549
550 static void early_uartlite_putc(struct uart_port *port, int c)
551 {
552 /*
553 * Limit how many times we'll spin waiting for TX FIFO status.
554 * This will prevent lockups if the base address is incorrectly
555 * set, or any other issue on the UARTLITE.
556 * This limit is pretty arbitrary, unless we are at about 10 baud
557 * we'll never timeout on a working UART.
558 */
559
560 unsigned retries = 1000000;
561 /* read status bit - 0x8 offset */
562 while (--retries && (readl(port->membase + 8) & (1 << 3)))
563 ;
564
565 /* Only attempt the iowrite if we didn't timeout */
566 /* write to TX_FIFO - 0x4 offset */
567 if (retries)
568 writel(c & 0xff, port->membase + 4);
569 }
570
571 static void early_uartlite_write(struct console *console,
572 const char *s, unsigned n)
573 {
574 struct earlycon_device *device = console->data;
575 uart_console_write(&device->port, s, n, early_uartlite_putc);
576 }
577
578 static int __init early_uartlite_setup(struct earlycon_device *device,
579 const char *options)
580 {
581 if (!device->port.membase)
582 return -ENODEV;
583
584 device->con->write = early_uartlite_write;
585 return 0;
586 }
587 EARLYCON_DECLARE(uartlite, early_uartlite_setup);
588 OF_EARLYCON_DECLARE(uartlite_b, "xlnx,opb-uartlite-1.00.b", early_uartlite_setup);
589 OF_EARLYCON_DECLARE(uartlite_a, "xlnx,xps-uartlite-1.00.a", early_uartlite_setup);
590
591 #endif /* CONFIG_SERIAL_UARTLITE_CONSOLE */
592
593 static struct uart_driver ulite_uart_driver = {
594 .owner = THIS_MODULE,
595 .driver_name = "uartlite",
596 .dev_name = ULITE_NAME,
597 .major = ULITE_MAJOR,
598 .minor = ULITE_MINOR,
599 .nr = ULITE_NR_UARTS,
600 #ifdef CONFIG_SERIAL_UARTLITE_CONSOLE
601 .cons = &ulite_console,
602 #endif
603 };
604
605 /* ---------------------------------------------------------------------
606 * Port assignment functions (mapping devices to uart_port structures)
607 */
608
609 /** ulite_assign: register a uartlite device with the driver
610 *
611 * @dev: pointer to device structure
612 * @id: requested id number. Pass -1 for automatic port assignment
613 * @base: base address of uartlite registers
614 * @irq: irq number for uartlite
615 * @pdata: private data for uartlite
616 *
617 * Returns: 0 on success, <0 otherwise
618 */
619 static int ulite_assign(struct device *dev, int id, u32 base, int irq,
620 struct uartlite_data *pdata)
621 {
622 struct uart_port *port;
623 int rc;
624
625 /* if id = -1; then scan for a free id and use that */
626 if (id < 0) {
627 for (id = 0; id < ULITE_NR_UARTS; id++)
628 if (ulite_ports[id].mapbase == 0)
629 break;
630 }
631 if (id < 0 || id >= ULITE_NR_UARTS) {
632 dev_err(dev, "%s%i too large\n", ULITE_NAME, id);
633 return -EINVAL;
634 }
635
636 if ((ulite_ports[id].mapbase) && (ulite_ports[id].mapbase != base)) {
637 dev_err(dev, "cannot assign to %s%i; it is already in use\n",
638 ULITE_NAME, id);
639 return -EBUSY;
640 }
641
642 port = &ulite_ports[id];
643
644 spin_lock_init(&port->lock);
645 port->fifosize = 16;
646 port->regshift = 2;
647 port->iotype = UPIO_MEM;
648 port->iobase = 1; /* mark port in use */
649 port->mapbase = base;
650 port->membase = NULL;
651 port->ops = &ulite_ops;
652 port->irq = irq;
653 port->flags = UPF_BOOT_AUTOCONF;
654 port->dev = dev;
655 port->type = PORT_UNKNOWN;
656 port->line = id;
657 port->private_data = pdata;
658
659 dev_set_drvdata(dev, port);
660
661 #ifdef CONFIG_SERIAL_UARTLITE_CONSOLE
662 /*
663 * If console hasn't been found yet try to assign this port
664 * because it is required to be assigned for console setup function.
665 * If register_console() don't assign value, then console_port pointer
666 * is cleanup.
667 */
668 if (ulite_uart_driver.cons->index == -1)
669 console_port = port;
670 #endif
671
672 /* Register the port */
673 rc = uart_add_one_port(&ulite_uart_driver, port);
674 if (rc) {
675 dev_err(dev, "uart_add_one_port() failed; err=%i\n", rc);
676 port->mapbase = 0;
677 dev_set_drvdata(dev, NULL);
678 return rc;
679 }
680
681 #ifdef CONFIG_SERIAL_UARTLITE_CONSOLE
682 /* This is not port which is used for console that's why clean it up */
683 if (ulite_uart_driver.cons->index == -1)
684 console_port = NULL;
685 #endif
686
687 return 0;
688 }
689
690 /** ulite_release: register a uartlite device with the driver
691 *
692 * @dev: pointer to device structure
693 */
694 static int ulite_release(struct device *dev)
695 {
696 struct uart_port *port = dev_get_drvdata(dev);
697 int rc = 0;
698
699 if (port) {
700 struct uartlite_data *pdata = port->private_data;
701
702 rc = uart_remove_one_port(pdata->ulite_uart_driver, port);
703 dev_set_drvdata(dev, NULL);
704 port->mapbase = 0;
705 }
706
707 return rc;
708 }
709
710 /**
711 * ulite_suspend - Stop the device.
712 *
713 * @dev: handle to the device structure.
714 * Return: 0 always.
715 */
716 static int __maybe_unused ulite_suspend(struct device *dev)
717 {
718 struct uart_port *port = dev_get_drvdata(dev);
719
720 if (port) {
721 struct uartlite_data *pdata = port->private_data;
722
723 uart_suspend_port(pdata->ulite_uart_driver, port);
724 }
725
726 return 0;
727 }
728
729 /**
730 * ulite_resume - Resume the device.
731 *
732 * @dev: handle to the device structure.
733 * Return: 0 on success, errno otherwise.
734 */
735 static int __maybe_unused ulite_resume(struct device *dev)
736 {
737 struct uart_port *port = dev_get_drvdata(dev);
738
739 if (port) {
740 struct uartlite_data *pdata = port->private_data;
741
742 uart_resume_port(pdata->ulite_uart_driver, port);
743 }
744
745 return 0;
746 }
747
748 static int __maybe_unused ulite_runtime_suspend(struct device *dev)
749 {
750 struct uart_port *port = dev_get_drvdata(dev);
751 struct uartlite_data *pdata = port->private_data;
752
753 clk_disable(pdata->clk);
754 return 0;
755 };
756
757 static int __maybe_unused ulite_runtime_resume(struct device *dev)
758 {
759 struct uart_port *port = dev_get_drvdata(dev);
760 struct uartlite_data *pdata = port->private_data;
761
762 clk_enable(pdata->clk);
763 return 0;
764 }
765 /* ---------------------------------------------------------------------
766 * Platform bus binding
767 */
768
769 static const struct dev_pm_ops ulite_pm_ops = {
770 SET_SYSTEM_SLEEP_PM_OPS(ulite_suspend, ulite_resume)
771 SET_RUNTIME_PM_OPS(ulite_runtime_suspend,
772 ulite_runtime_resume, NULL)
773 };
774
775 #if defined(CONFIG_OF)
776 /* Match table for of_platform binding */
777 static const struct of_device_id ulite_of_match[] = {
778 { .compatible = "xlnx,opb-uartlite-1.00.b", },
779 { .compatible = "xlnx,xps-uartlite-1.00.a", },
780 {}
781 };
782 MODULE_DEVICE_TABLE(of, ulite_of_match);
783 #endif /* CONFIG_OF */
784
785 static int ulite_probe(struct platform_device *pdev)
786 {
787 struct resource *res;
788 struct uartlite_data *pdata;
789 int irq, ret;
790 int id = pdev->id;
791 #ifdef CONFIG_OF
792 const __be32 *prop;
793
794 prop = of_get_property(pdev->dev.of_node, "port-number", NULL);
795 if (prop)
796 id = be32_to_cpup(prop);
797 #endif
798 if (id < 0) {
799 /* Look for a serialN alias */
800 id = of_alias_get_id(pdev->dev.of_node, "serial");
801 if (id < 0)
802 id = 0;
803 }
804
805 if (!ulite_uart_driver.state) {
806 dev_dbg(&pdev->dev, "uartlite: calling uart_register_driver()\n");
807 ret = uart_register_driver(&ulite_uart_driver);
808 if (ret < 0) {
809 dev_err(&pdev->dev, "Failed to register driver\n");
810 return ret;
811 }
812 }
813
814 pdata = devm_kzalloc(&pdev->dev, sizeof(struct uartlite_data),
815 GFP_KERNEL);
816 if (!pdata)
817 return -ENOMEM;
818
819 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
820 if (!res)
821 return -ENODEV;
822
823 irq = platform_get_irq(pdev, 0);
824 if (irq <= 0)
825 return -ENXIO;
826
827 pdata->clk = devm_clk_get(&pdev->dev, "s_axi_aclk");
828 if (IS_ERR(pdata->clk)) {
829 if (PTR_ERR(pdata->clk) != -ENOENT)
830 return PTR_ERR(pdata->clk);
831
832 /*
833 * Clock framework support is optional, continue on
834 * anyways if we don't find a matching clock.
835 */
836 pdata->clk = NULL;
837 }
838
839 pdata->ulite_uart_driver = &ulite_uart_driver;
840 ret = clk_prepare_enable(pdata->clk);
841 if (ret) {
842 dev_err(&pdev->dev, "Failed to prepare clock\n");
843 return ret;
844 }
845
846 pm_runtime_use_autosuspend(&pdev->dev);
847 pm_runtime_set_autosuspend_delay(&pdev->dev, UART_AUTOSUSPEND_TIMEOUT);
848 pm_runtime_set_active(&pdev->dev);
849 pm_runtime_enable(&pdev->dev);
850
851 ret = ulite_assign(&pdev->dev, id, res->start, irq, pdata);
852
853 pm_runtime_mark_last_busy(&pdev->dev);
854 pm_runtime_put_autosuspend(&pdev->dev);
855
856 return ret;
857 }
858
859 static int ulite_remove(struct platform_device *pdev)
860 {
861 struct uart_port *port = dev_get_drvdata(&pdev->dev);
862 struct uartlite_data *pdata = port->private_data;
863 int rc;
864
865 clk_unprepare(pdata->clk);
866 rc = ulite_release(&pdev->dev);
867 pm_runtime_disable(&pdev->dev);
868 pm_runtime_set_suspended(&pdev->dev);
869 pm_runtime_dont_use_autosuspend(&pdev->dev);
870 return rc;
871 }
872
873 /* work with hotplug and coldplug */
874 MODULE_ALIAS("platform:uartlite");
875
876 static struct platform_driver ulite_platform_driver = {
877 .probe = ulite_probe,
878 .remove = ulite_remove,
879 .driver = {
880 .name = "uartlite",
881 .of_match_table = of_match_ptr(ulite_of_match),
882 .pm = &ulite_pm_ops,
883 },
884 };
885
886 /* ---------------------------------------------------------------------
887 * Module setup/teardown
888 */
889
890 static int __init ulite_init(void)
891 {
892
893 pr_debug("uartlite: calling platform_driver_register()\n");
894 return platform_driver_register(&ulite_platform_driver);
895 }
896
897 static void __exit ulite_exit(void)
898 {
899 platform_driver_unregister(&ulite_platform_driver);
900 uart_unregister_driver(&ulite_uart_driver);
901 }
902
903 module_init(ulite_init);
904 module_exit(ulite_exit);
905
906 MODULE_AUTHOR("Peter Korsgaard <jacmet@sunsite.dk>");
907 MODULE_DESCRIPTION("Xilinx uartlite serial driver");
908 MODULE_LICENSE("GPL");
Linux with added FPC-III support