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cpuset: restore sanity to cpuset_cpus_allowed_fallback()
[linux/fpc-iii.git] / drivers / mmc / host / au1xmmc.c
blob9b4be67330dd2fa5cefb0cf139b77f989c2f0383
1 /*
2 * linux/drivers/mmc/host/au1xmmc.c - AU1XX0 MMC driver
3 *
4 * Copyright (c) 2005, Advanced Micro Devices, Inc.
5 *
6 * Developed with help from the 2.4.30 MMC AU1XXX controller including
7 * the following copyright notices:
8 * Copyright (c) 2003-2004 Embedded Edge, LLC.
9 * Portions Copyright (C) 2002 Embedix, Inc
10 * Copyright 2002 Hewlett-Packard Company
11
12 * 2.6 version of this driver inspired by:
13 * (drivers/mmc/wbsd.c) Copyright (C) 2004-2005 Pierre Ossman,
14 * All Rights Reserved.
15 * (drivers/mmc/pxa.c) Copyright (C) 2003 Russell King,
16 * All Rights Reserved.
17 *
18
19 * This program is free software; you can redistribute it and/or modify
20 * it under the terms of the GNU General Public License version 2 as
21 * published by the Free Software Foundation.
22 */
23
24 /* Why don't we use the SD controllers' carddetect feature?
25 *
26 * From the AU1100 MMC application guide:
27 * If the Au1100-based design is intended to support both MultiMediaCards
28 * and 1- or 4-data bit SecureDigital cards, then the solution is to
29 * connect a weak (560KOhm) pull-up resistor to connector pin 1.
30 * In doing so, a MMC card never enters SPI-mode communications,
31 * but now the SecureDigital card-detect feature of CD/DAT3 is ineffective
32 * (the low to high transition will not occur).
33 */
34
35 #include <linux/clk.h>
36 #include <linux/module.h>
37 #include <linux/init.h>
38 #include <linux/platform_device.h>
39 #include <linux/mm.h>
40 #include <linux/interrupt.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/scatterlist.h>
43 #include <linux/highmem.h>
44 #include <linux/leds.h>
45 #include <linux/mmc/host.h>
46 #include <linux/slab.h>
47
48 #include <asm/io.h>
49 #include <asm/mach-au1x00/au1000.h>
50 #include <asm/mach-au1x00/au1xxx_dbdma.h>
51 #include <asm/mach-au1x00/au1100_mmc.h>
52
53 #define DRIVER_NAME "au1xxx-mmc"
54
55 /* Set this to enable special debugging macros */
56 /* #define DEBUG */
57
58 #ifdef DEBUG
59 #define DBG(fmt, idx, args...) \
60 pr_debug("au1xmmc(%d): DEBUG: " fmt, idx, ##args)
61 #else
62 #define DBG(fmt, idx, args...) do {} while (0)
63 #endif
64
65 /* Hardware definitions */
66 #define AU1XMMC_DESCRIPTOR_COUNT 1
67
68 /* max DMA seg size: 64KB on Au1100, 4MB on Au1200 */
69 #define AU1100_MMC_DESCRIPTOR_SIZE 0x0000ffff
70 #define AU1200_MMC_DESCRIPTOR_SIZE 0x003fffff
71
72 #define AU1XMMC_OCR (MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 | \
73 MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 | \
74 MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36)
75
76 /* This gives us a hard value for the stop command that we can write directly
77 * to the command register.
78 */
79 #define STOP_CMD \
80 (SD_CMD_RT_1B | SD_CMD_CT_7 | (0xC << SD_CMD_CI_SHIFT) | SD_CMD_GO)
81
82 /* This is the set of interrupts that we configure by default. */
83 #define AU1XMMC_INTERRUPTS \
84 (SD_CONFIG_SC | SD_CONFIG_DT | SD_CONFIG_RAT | \
85 SD_CONFIG_CR | SD_CONFIG_I)
86
87 /* The poll event (looking for insert/remove events runs twice a second. */
88 #define AU1XMMC_DETECT_TIMEOUT (HZ/2)
89
90 struct au1xmmc_host {
91 struct mmc_host *mmc;
92 struct mmc_request *mrq;
93
94 u32 flags;
95 void __iomem *iobase;
96 u32 clock;
97 u32 bus_width;
98 u32 power_mode;
99
100 int status;
101
102 struct {
103 int len;
104 int dir;
105 } dma;
106
107 struct {
108 int index;
109 int offset;
110 int len;
111 } pio;
112
113 u32 tx_chan;
114 u32 rx_chan;
115
116 int irq;
117
118 struct tasklet_struct finish_task;
119 struct tasklet_struct data_task;
120 struct au1xmmc_platform_data *platdata;
121 struct platform_device *pdev;
122 struct resource *ioarea;
123 struct clk *clk;
124 };
125
126 /* Status flags used by the host structure */
127 #define HOST_F_XMIT 0x0001
128 #define HOST_F_RECV 0x0002
129 #define HOST_F_DMA 0x0010
130 #define HOST_F_DBDMA 0x0020
131 #define HOST_F_ACTIVE 0x0100
132 #define HOST_F_STOP 0x1000
133
134 #define HOST_S_IDLE 0x0001
135 #define HOST_S_CMD 0x0002
136 #define HOST_S_DATA 0x0003
137 #define HOST_S_STOP 0x0004
138
139 /* Easy access macros */
140 #define HOST_STATUS(h) ((h)->iobase + SD_STATUS)
141 #define HOST_CONFIG(h) ((h)->iobase + SD_CONFIG)
142 #define HOST_ENABLE(h) ((h)->iobase + SD_ENABLE)
143 #define HOST_TXPORT(h) ((h)->iobase + SD_TXPORT)
144 #define HOST_RXPORT(h) ((h)->iobase + SD_RXPORT)
145 #define HOST_CMDARG(h) ((h)->iobase + SD_CMDARG)
146 #define HOST_BLKSIZE(h) ((h)->iobase + SD_BLKSIZE)
147 #define HOST_CMD(h) ((h)->iobase + SD_CMD)
148 #define HOST_CONFIG2(h) ((h)->iobase + SD_CONFIG2)
149 #define HOST_TIMEOUT(h) ((h)->iobase + SD_TIMEOUT)
150 #define HOST_DEBUG(h) ((h)->iobase + SD_DEBUG)
151
152 #define DMA_CHANNEL(h) \
153 (((h)->flags & HOST_F_XMIT) ? (h)->tx_chan : (h)->rx_chan)
154
155 static inline int has_dbdma(void)
156 {
157 switch (alchemy_get_cputype()) {
158 case ALCHEMY_CPU_AU1200:
159 case ALCHEMY_CPU_AU1300:
160 return 1;
161 default:
162 return 0;
163 }
164 }
165
166 static inline void IRQ_ON(struct au1xmmc_host *host, u32 mask)
167 {
168 u32 val = __raw_readl(HOST_CONFIG(host));
169 val |= mask;
170 __raw_writel(val, HOST_CONFIG(host));
171 wmb(); /* drain writebuffer */
172 }
173
174 static inline void FLUSH_FIFO(struct au1xmmc_host *host)
175 {
176 u32 val = __raw_readl(HOST_CONFIG2(host));
177
178 __raw_writel(val | SD_CONFIG2_FF, HOST_CONFIG2(host));
179 wmb(); /* drain writebuffer */
180 mdelay(1);
181
182 /* SEND_STOP will turn off clock control - this re-enables it */
183 val &= ~SD_CONFIG2_DF;
184
185 __raw_writel(val, HOST_CONFIG2(host));
186 wmb(); /* drain writebuffer */
187 }
188
189 static inline void IRQ_OFF(struct au1xmmc_host *host, u32 mask)
190 {
191 u32 val = __raw_readl(HOST_CONFIG(host));
192 val &= ~mask;
193 __raw_writel(val, HOST_CONFIG(host));
194 wmb(); /* drain writebuffer */
195 }
196
197 static inline void SEND_STOP(struct au1xmmc_host *host)
198 {
199 u32 config2;
200
201 WARN_ON(host->status != HOST_S_DATA);
202 host->status = HOST_S_STOP;
203
204 config2 = __raw_readl(HOST_CONFIG2(host));
205 __raw_writel(config2 | SD_CONFIG2_DF, HOST_CONFIG2(host));
206 wmb(); /* drain writebuffer */
207
208 /* Send the stop command */
209 __raw_writel(STOP_CMD, HOST_CMD(host));
210 wmb(); /* drain writebuffer */
211 }
212
213 static void au1xmmc_set_power(struct au1xmmc_host *host, int state)
214 {
215 if (host->platdata && host->platdata->set_power)
216 host->platdata->set_power(host->mmc, state);
217 }
218
219 static int au1xmmc_card_inserted(struct mmc_host *mmc)
220 {
221 struct au1xmmc_host *host = mmc_priv(mmc);
222
223 if (host->platdata && host->platdata->card_inserted)
224 return !!host->platdata->card_inserted(host->mmc);
225
226 return -ENOSYS;
227 }
228
229 static int au1xmmc_card_readonly(struct mmc_host *mmc)
230 {
231 struct au1xmmc_host *host = mmc_priv(mmc);
232
233 if (host->platdata && host->platdata->card_readonly)
234 return !!host->platdata->card_readonly(mmc);
235
236 return -ENOSYS;
237 }
238
239 static void au1xmmc_finish_request(struct au1xmmc_host *host)
240 {
241 struct mmc_request *mrq = host->mrq;
242
243 host->mrq = NULL;
244 host->flags &= HOST_F_ACTIVE | HOST_F_DMA;
245
246 host->dma.len = 0;
247 host->dma.dir = 0;
248
249 host->pio.index = 0;
250 host->pio.offset = 0;
251 host->pio.len = 0;
252
253 host->status = HOST_S_IDLE;
254
255 mmc_request_done(host->mmc, mrq);
256 }
257
258 static void au1xmmc_tasklet_finish(unsigned long param)
259 {
260 struct au1xmmc_host *host = (struct au1xmmc_host *) param;
261 au1xmmc_finish_request(host);
262 }
263
264 static int au1xmmc_send_command(struct au1xmmc_host *host, int wait,
265 struct mmc_command *cmd, struct mmc_data *data)
266 {
267 u32 mmccmd = (cmd->opcode << SD_CMD_CI_SHIFT);
268
269 switch (mmc_resp_type(cmd)) {
270 case MMC_RSP_NONE:
271 break;
272 case MMC_RSP_R1:
273 mmccmd |= SD_CMD_RT_1;
274 break;
275 case MMC_RSP_R1B:
276 mmccmd |= SD_CMD_RT_1B;
277 break;
278 case MMC_RSP_R2:
279 mmccmd |= SD_CMD_RT_2;
280 break;
281 case MMC_RSP_R3:
282 mmccmd |= SD_CMD_RT_3;
283 break;
284 default:
285 pr_info("au1xmmc: unhandled response type %02x\n",
286 mmc_resp_type(cmd));
287 return -EINVAL;
288 }
289
290 if (data) {
291 if (data->flags & MMC_DATA_READ) {
292 if (data->blocks > 1)
293 mmccmd |= SD_CMD_CT_4;
294 else
295 mmccmd |= SD_CMD_CT_2;
296 } else if (data->flags & MMC_DATA_WRITE) {
297 if (data->blocks > 1)
298 mmccmd |= SD_CMD_CT_3;
299 else
300 mmccmd |= SD_CMD_CT_1;
301 }
302 }
303
304 __raw_writel(cmd->arg, HOST_CMDARG(host));
305 wmb(); /* drain writebuffer */
306
307 if (wait)
308 IRQ_OFF(host, SD_CONFIG_CR);
309
310 __raw_writel((mmccmd | SD_CMD_GO), HOST_CMD(host));
311 wmb(); /* drain writebuffer */
312
313 /* Wait for the command to go on the line */
314 while (__raw_readl(HOST_CMD(host)) & SD_CMD_GO)
315 /* nop */;
316
317 /* Wait for the command to come back */
318 if (wait) {
319 u32 status = __raw_readl(HOST_STATUS(host));
320
321 while (!(status & SD_STATUS_CR))
322 status = __raw_readl(HOST_STATUS(host));
323
324 /* Clear the CR status */
325 __raw_writel(SD_STATUS_CR, HOST_STATUS(host));
326
327 IRQ_ON(host, SD_CONFIG_CR);
328 }
329
330 return 0;
331 }
332
333 static void au1xmmc_data_complete(struct au1xmmc_host *host, u32 status)
334 {
335 struct mmc_request *mrq = host->mrq;
336 struct mmc_data *data;
337 u32 crc;
338
339 WARN_ON((host->status != HOST_S_DATA) && (host->status != HOST_S_STOP));
340
341 if (host->mrq == NULL)
342 return;
343
344 data = mrq->cmd->data;
345
346 if (status == 0)
347 status = __raw_readl(HOST_STATUS(host));
348
349 /* The transaction is really over when the SD_STATUS_DB bit is clear */
350 while ((host->flags & HOST_F_XMIT) && (status & SD_STATUS_DB))
351 status = __raw_readl(HOST_STATUS(host));
352
353 data->error = 0;
354 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, host->dma.dir);
355
356 /* Process any errors */
357 crc = (status & (SD_STATUS_WC | SD_STATUS_RC));
358 if (host->flags & HOST_F_XMIT)
359 crc |= ((status & 0x07) == 0x02) ? 0 : 1;
360
361 if (crc)
362 data->error = -EILSEQ;
363
364 /* Clear the CRC bits */
365 __raw_writel(SD_STATUS_WC | SD_STATUS_RC, HOST_STATUS(host));
366
367 data->bytes_xfered = 0;
368
369 if (!data->error) {
370 if (host->flags & (HOST_F_DMA | HOST_F_DBDMA)) {
371 u32 chan = DMA_CHANNEL(host);
372
373 chan_tab_t *c = *((chan_tab_t **)chan);
374 au1x_dma_chan_t *cp = c->chan_ptr;
375 data->bytes_xfered = cp->ddma_bytecnt;
376 } else
377 data->bytes_xfered =
378 (data->blocks * data->blksz) - host->pio.len;
379 }
380
381 au1xmmc_finish_request(host);
382 }
383
384 static void au1xmmc_tasklet_data(unsigned long param)
385 {
386 struct au1xmmc_host *host = (struct au1xmmc_host *)param;
387
388 u32 status = __raw_readl(HOST_STATUS(host));
389 au1xmmc_data_complete(host, status);
390 }
391
392 #define AU1XMMC_MAX_TRANSFER 8
393
394 static void au1xmmc_send_pio(struct au1xmmc_host *host)
395 {
396 struct mmc_data *data;
397 int sg_len, max, count;
398 unsigned char *sg_ptr, val;
399 u32 status;
400 struct scatterlist *sg;
401
402 data = host->mrq->data;
403
404 if (!(host->flags & HOST_F_XMIT))
405 return;
406
407 /* This is the pointer to the data buffer */
408 sg = &data->sg[host->pio.index];
409 sg_ptr = kmap_atomic(sg_page(sg)) + sg->offset + host->pio.offset;
410
411 /* This is the space left inside the buffer */
412 sg_len = data->sg[host->pio.index].length - host->pio.offset;
413
414 /* Check if we need less than the size of the sg_buffer */
415 max = (sg_len > host->pio.len) ? host->pio.len : sg_len;
416 if (max > AU1XMMC_MAX_TRANSFER)
417 max = AU1XMMC_MAX_TRANSFER;
418
419 for (count = 0; count < max; count++) {
420 status = __raw_readl(HOST_STATUS(host));
421
422 if (!(status & SD_STATUS_TH))
423 break;
424
425 val = sg_ptr[count];
426
427 __raw_writel((unsigned long)val, HOST_TXPORT(host));
428 wmb(); /* drain writebuffer */
429 }
430 kunmap_atomic(sg_ptr);
431
432 host->pio.len -= count;
433 host->pio.offset += count;
434
435 if (count == sg_len) {
436 host->pio.index++;
437 host->pio.offset = 0;
438 }
439
440 if (host->pio.len == 0) {
441 IRQ_OFF(host, SD_CONFIG_TH);
442
443 if (host->flags & HOST_F_STOP)
444 SEND_STOP(host);
445
446 tasklet_schedule(&host->data_task);
447 }
448 }
449
450 static void au1xmmc_receive_pio(struct au1xmmc_host *host)
451 {
452 struct mmc_data *data;
453 int max, count, sg_len = 0;
454 unsigned char *sg_ptr = NULL;
455 u32 status, val;
456 struct scatterlist *sg;
457
458 data = host->mrq->data;
459
460 if (!(host->flags & HOST_F_RECV))
461 return;
462
463 max = host->pio.len;
464
465 if (host->pio.index < host->dma.len) {
466 sg = &data->sg[host->pio.index];
467 sg_ptr = kmap_atomic(sg_page(sg)) + sg->offset + host->pio.offset;
468
469 /* This is the space left inside the buffer */
470 sg_len = sg_dma_len(&data->sg[host->pio.index]) - host->pio.offset;
471
472 /* Check if we need less than the size of the sg_buffer */
473 if (sg_len < max)
474 max = sg_len;
475 }
476
477 if (max > AU1XMMC_MAX_TRANSFER)
478 max = AU1XMMC_MAX_TRANSFER;
479
480 for (count = 0; count < max; count++) {
481 status = __raw_readl(HOST_STATUS(host));
482
483 if (!(status & SD_STATUS_NE))
484 break;
485
486 if (status & SD_STATUS_RC) {
487 DBG("RX CRC Error [%d + %d].\n", host->pdev->id,
488 host->pio.len, count);
489 break;
490 }
491
492 if (status & SD_STATUS_RO) {
493 DBG("RX Overrun [%d + %d]\n", host->pdev->id,
494 host->pio.len, count);
495 break;
496 }
497 else if (status & SD_STATUS_RU) {
498 DBG("RX Underrun [%d + %d]\n", host->pdev->id,
499 host->pio.len, count);
500 break;
501 }
502
503 val = __raw_readl(HOST_RXPORT(host));
504
505 if (sg_ptr)
506 sg_ptr[count] = (unsigned char)(val & 0xFF);
507 }
508 if (sg_ptr)
509 kunmap_atomic(sg_ptr);
510
511 host->pio.len -= count;
512 host->pio.offset += count;
513
514 if (sg_len && count == sg_len) {
515 host->pio.index++;
516 host->pio.offset = 0;
517 }
518
519 if (host->pio.len == 0) {
520 /* IRQ_OFF(host, SD_CONFIG_RA | SD_CONFIG_RF); */
521 IRQ_OFF(host, SD_CONFIG_NE);
522
523 if (host->flags & HOST_F_STOP)
524 SEND_STOP(host);
525
526 tasklet_schedule(&host->data_task);
527 }
528 }
529
530 /* This is called when a command has been completed - grab the response
531 * and check for errors. Then start the data transfer if it is indicated.
532 */
533 static void au1xmmc_cmd_complete(struct au1xmmc_host *host, u32 status)
534 {
535 struct mmc_request *mrq = host->mrq;
536 struct mmc_command *cmd;
537 u32 r[4];
538 int i, trans;
539
540 if (!host->mrq)
541 return;
542
543 cmd = mrq->cmd;
544 cmd->error = 0;
545
546 if (cmd->flags & MMC_RSP_PRESENT) {
547 if (cmd->flags & MMC_RSP_136) {
548 r[0] = __raw_readl(host->iobase + SD_RESP3);
549 r[1] = __raw_readl(host->iobase + SD_RESP2);
550 r[2] = __raw_readl(host->iobase + SD_RESP1);
551 r[3] = __raw_readl(host->iobase + SD_RESP0);
552
553 /* The CRC is omitted from the response, so really
554 * we only got 120 bytes, but the engine expects
555 * 128 bits, so we have to shift things up.
556 */
557 for (i = 0; i < 4; i++) {
558 cmd->resp[i] = (r[i] & 0x00FFFFFF) << 8;
559 if (i != 3)
560 cmd->resp[i] |= (r[i + 1] & 0xFF000000) >> 24;
561 }
562 } else {
563 /* Techincally, we should be getting all 48 bits of
564 * the response (SD_RESP1 + SD_RESP2), but because
565 * our response omits the CRC, our data ends up
566 * being shifted 8 bits to the right. In this case,
567 * that means that the OSR data starts at bit 31,
568 * so we can just read RESP0 and return that.
569 */
570 cmd->resp[0] = __raw_readl(host->iobase + SD_RESP0);
571 }
572 }
573
574 /* Figure out errors */
575 if (status & (SD_STATUS_SC | SD_STATUS_WC | SD_STATUS_RC))
576 cmd->error = -EILSEQ;
577
578 trans = host->flags & (HOST_F_XMIT | HOST_F_RECV);
579
580 if (!trans || cmd->error) {
581 IRQ_OFF(host, SD_CONFIG_TH | SD_CONFIG_RA | SD_CONFIG_RF);
582 tasklet_schedule(&host->finish_task);
583 return;
584 }
585
586 host->status = HOST_S_DATA;
587
588 if ((host->flags & (HOST_F_DMA | HOST_F_DBDMA))) {
589 u32 channel = DMA_CHANNEL(host);
590
591 /* Start the DBDMA as soon as the buffer gets something in it */
592
593 if (host->flags & HOST_F_RECV) {
594 u32 mask = SD_STATUS_DB | SD_STATUS_NE;
595
596 while((status & mask) != mask)
597 status = __raw_readl(HOST_STATUS(host));
598 }
599
600 au1xxx_dbdma_start(channel);
601 }
602 }
603
604 static void au1xmmc_set_clock(struct au1xmmc_host *host, int rate)
605 {
606 unsigned int pbus = clk_get_rate(host->clk);
607 unsigned int divisor = ((pbus / rate) / 2) - 1;
608 u32 config;
609
610 config = __raw_readl(HOST_CONFIG(host));
611
612 config &= ~(SD_CONFIG_DIV);
613 config |= (divisor & SD_CONFIG_DIV) | SD_CONFIG_DE;
614
615 __raw_writel(config, HOST_CONFIG(host));
616 wmb(); /* drain writebuffer */
617 }
618
619 static int au1xmmc_prepare_data(struct au1xmmc_host *host,
620 struct mmc_data *data)
621 {
622 int datalen = data->blocks * data->blksz;
623
624 if (data->flags & MMC_DATA_READ)
625 host->flags |= HOST_F_RECV;
626 else
627 host->flags |= HOST_F_XMIT;
628
629 if (host->mrq->stop)
630 host->flags |= HOST_F_STOP;
631
632 host->dma.dir = DMA_BIDIRECTIONAL;
633
634 host->dma.len = dma_map_sg(mmc_dev(host->mmc), data->sg,
635 data->sg_len, host->dma.dir);
636
637 if (host->dma.len == 0)
638 return -ETIMEDOUT;
639
640 __raw_writel(data->blksz - 1, HOST_BLKSIZE(host));
641
642 if (host->flags & (HOST_F_DMA | HOST_F_DBDMA)) {
643 int i;
644 u32 channel = DMA_CHANNEL(host);
645
646 au1xxx_dbdma_stop(channel);
647
648 for (i = 0; i < host->dma.len; i++) {
649 u32 ret = 0, flags = DDMA_FLAGS_NOIE;
650 struct scatterlist *sg = &data->sg[i];
651 int sg_len = sg->length;
652
653 int len = (datalen > sg_len) ? sg_len : datalen;
654
655 if (i == host->dma.len - 1)
656 flags = DDMA_FLAGS_IE;
657
658 if (host->flags & HOST_F_XMIT) {
659 ret = au1xxx_dbdma_put_source(channel,
660 sg_phys(sg), len, flags);
661 } else {
662 ret = au1xxx_dbdma_put_dest(channel,
663 sg_phys(sg), len, flags);
664 }
665
666 if (!ret)
667 goto dataerr;
668
669 datalen -= len;
670 }
671 } else {
672 host->pio.index = 0;
673 host->pio.offset = 0;
674 host->pio.len = datalen;
675
676 if (host->flags & HOST_F_XMIT)
677 IRQ_ON(host, SD_CONFIG_TH);
678 else
679 IRQ_ON(host, SD_CONFIG_NE);
680 /* IRQ_ON(host, SD_CONFIG_RA | SD_CONFIG_RF); */
681 }
682
683 return 0;
684
685 dataerr:
686 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
687 host->dma.dir);
688 return -ETIMEDOUT;
689 }
690
691 /* This actually starts a command or data transaction */
692 static void au1xmmc_request(struct mmc_host* mmc, struct mmc_request* mrq)
693 {
694 struct au1xmmc_host *host = mmc_priv(mmc);
695 int ret = 0;
696
697 WARN_ON(irqs_disabled());
698 WARN_ON(host->status != HOST_S_IDLE);
699
700 host->mrq = mrq;
701 host->status = HOST_S_CMD;
702
703 /* fail request immediately if no card is present */
704 if (0 == au1xmmc_card_inserted(mmc)) {
705 mrq->cmd->error = -ENOMEDIUM;
706 au1xmmc_finish_request(host);
707 return;
708 }
709
710 if (mrq->data) {
711 FLUSH_FIFO(host);
712 ret = au1xmmc_prepare_data(host, mrq->data);
713 }
714
715 if (!ret)
716 ret = au1xmmc_send_command(host, 0, mrq->cmd, mrq->data);
717
718 if (ret) {
719 mrq->cmd->error = ret;
720 au1xmmc_finish_request(host);
721 }
722 }
723
724 static void au1xmmc_reset_controller(struct au1xmmc_host *host)
725 {
726 /* Apply the clock */
727 __raw_writel(SD_ENABLE_CE, HOST_ENABLE(host));
728 wmb(); /* drain writebuffer */
729 mdelay(1);
730
731 __raw_writel(SD_ENABLE_R | SD_ENABLE_CE, HOST_ENABLE(host));
732 wmb(); /* drain writebuffer */
733 mdelay(5);
734
735 __raw_writel(~0, HOST_STATUS(host));
736 wmb(); /* drain writebuffer */
737
738 __raw_writel(0, HOST_BLKSIZE(host));
739 __raw_writel(0x001fffff, HOST_TIMEOUT(host));
740 wmb(); /* drain writebuffer */
741
742 __raw_writel(SD_CONFIG2_EN, HOST_CONFIG2(host));
743 wmb(); /* drain writebuffer */
744
745 __raw_writel(SD_CONFIG2_EN | SD_CONFIG2_FF, HOST_CONFIG2(host));
746 wmb(); /* drain writebuffer */
747 mdelay(1);
748
749 __raw_writel(SD_CONFIG2_EN, HOST_CONFIG2(host));
750 wmb(); /* drain writebuffer */
751
752 /* Configure interrupts */
753 __raw_writel(AU1XMMC_INTERRUPTS, HOST_CONFIG(host));
754 wmb(); /* drain writebuffer */
755 }
756
757
758 static void au1xmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
759 {
760 struct au1xmmc_host *host = mmc_priv(mmc);
761 u32 config2;
762
763 if (ios->power_mode == MMC_POWER_OFF)
764 au1xmmc_set_power(host, 0);
765 else if (ios->power_mode == MMC_POWER_ON) {
766 au1xmmc_set_power(host, 1);
767 }
768
769 if (ios->clock && ios->clock != host->clock) {
770 au1xmmc_set_clock(host, ios->clock);
771 host->clock = ios->clock;
772 }
773
774 config2 = __raw_readl(HOST_CONFIG2(host));
775 switch (ios->bus_width) {
776 case MMC_BUS_WIDTH_8:
777 config2 |= SD_CONFIG2_BB;
778 break;
779 case MMC_BUS_WIDTH_4:
780 config2 &= ~SD_CONFIG2_BB;
781 config2 |= SD_CONFIG2_WB;
782 break;
783 case MMC_BUS_WIDTH_1:
784 config2 &= ~(SD_CONFIG2_WB | SD_CONFIG2_BB);
785 break;
786 }
787 __raw_writel(config2, HOST_CONFIG2(host));
788 wmb(); /* drain writebuffer */
789 }
790
791 #define STATUS_TIMEOUT (SD_STATUS_RAT | SD_STATUS_DT)
792 #define STATUS_DATA_IN (SD_STATUS_NE)
793 #define STATUS_DATA_OUT (SD_STATUS_TH)
794
795 static irqreturn_t au1xmmc_irq(int irq, void *dev_id)
796 {
797 struct au1xmmc_host *host = dev_id;
798 u32 status;
799
800 status = __raw_readl(HOST_STATUS(host));
801
802 if (!(status & SD_STATUS_I))
803 return IRQ_NONE; /* not ours */
804
805 if (status & SD_STATUS_SI) /* SDIO */
806 mmc_signal_sdio_irq(host->mmc);
807
808 if (host->mrq && (status & STATUS_TIMEOUT)) {
809 if (status & SD_STATUS_RAT)
810 host->mrq->cmd->error = -ETIMEDOUT;
811 else if (status & SD_STATUS_DT)
812 host->mrq->data->error = -ETIMEDOUT;
813
814 /* In PIO mode, interrupts might still be enabled */
815 IRQ_OFF(host, SD_CONFIG_NE | SD_CONFIG_TH);
816
817 /* IRQ_OFF(host, SD_CONFIG_TH | SD_CONFIG_RA | SD_CONFIG_RF); */
818 tasklet_schedule(&host->finish_task);
819 }
820 #if 0
821 else if (status & SD_STATUS_DD) {
822 /* Sometimes we get a DD before a NE in PIO mode */
823 if (!(host->flags & HOST_F_DMA) && (status & SD_STATUS_NE))
824 au1xmmc_receive_pio(host);
825 else {
826 au1xmmc_data_complete(host, status);
827 /* tasklet_schedule(&host->data_task); */
828 }
829 }
830 #endif
831 else if (status & SD_STATUS_CR) {
832 if (host->status == HOST_S_CMD)
833 au1xmmc_cmd_complete(host, status);
834
835 } else if (!(host->flags & HOST_F_DMA)) {
836 if ((host->flags & HOST_F_XMIT) && (status & STATUS_DATA_OUT))
837 au1xmmc_send_pio(host);
838 else if ((host->flags & HOST_F_RECV) && (status & STATUS_DATA_IN))
839 au1xmmc_receive_pio(host);
840
841 } else if (status & 0x203F3C70) {
842 DBG("Unhandled status %8.8x\n", host->pdev->id,
843 status);
844 }
845
846 __raw_writel(status, HOST_STATUS(host));
847 wmb(); /* drain writebuffer */
848
849 return IRQ_HANDLED;
850 }
851
852 /* 8bit memory DMA device */
853 static dbdev_tab_t au1xmmc_mem_dbdev = {
854 .dev_id = DSCR_CMD0_ALWAYS,
855 .dev_flags = DEV_FLAGS_ANYUSE,
856 .dev_tsize = 0,
857 .dev_devwidth = 8,
858 .dev_physaddr = 0x00000000,
859 .dev_intlevel = 0,
860 .dev_intpolarity = 0,
861 };
862 static int memid;
863
864 static void au1xmmc_dbdma_callback(int irq, void *dev_id)
865 {
866 struct au1xmmc_host *host = (struct au1xmmc_host *)dev_id;
867
868 /* Avoid spurious interrupts */
869 if (!host->mrq)
870 return;
871
872 if (host->flags & HOST_F_STOP)
873 SEND_STOP(host);
874
875 tasklet_schedule(&host->data_task);
876 }
877
878 static int au1xmmc_dbdma_init(struct au1xmmc_host *host)
879 {
880 struct resource *res;
881 int txid, rxid;
882
883 res = platform_get_resource(host->pdev, IORESOURCE_DMA, 0);
884 if (!res)
885 return -ENODEV;
886 txid = res->start;
887
888 res = platform_get_resource(host->pdev, IORESOURCE_DMA, 1);
889 if (!res)
890 return -ENODEV;
891 rxid = res->start;
892
893 if (!memid)
894 return -ENODEV;
895
896 host->tx_chan = au1xxx_dbdma_chan_alloc(memid, txid,
897 au1xmmc_dbdma_callback, (void *)host);
898 if (!host->tx_chan) {
899 dev_err(&host->pdev->dev, "cannot allocate TX DMA\n");
900 return -ENODEV;
901 }
902
903 host->rx_chan = au1xxx_dbdma_chan_alloc(rxid, memid,
904 au1xmmc_dbdma_callback, (void *)host);
905 if (!host->rx_chan) {
906 dev_err(&host->pdev->dev, "cannot allocate RX DMA\n");
907 au1xxx_dbdma_chan_free(host->tx_chan);
908 return -ENODEV;
909 }
910
911 au1xxx_dbdma_set_devwidth(host->tx_chan, 8);
912 au1xxx_dbdma_set_devwidth(host->rx_chan, 8);
913
914 au1xxx_dbdma_ring_alloc(host->tx_chan, AU1XMMC_DESCRIPTOR_COUNT);
915 au1xxx_dbdma_ring_alloc(host->rx_chan, AU1XMMC_DESCRIPTOR_COUNT);
916
917 /* DBDMA is good to go */
918 host->flags |= HOST_F_DMA | HOST_F_DBDMA;
919
920 return 0;
921 }
922
923 static void au1xmmc_dbdma_shutdown(struct au1xmmc_host *host)
924 {
925 if (host->flags & HOST_F_DMA) {
926 host->flags &= ~HOST_F_DMA;
927 au1xxx_dbdma_chan_free(host->tx_chan);
928 au1xxx_dbdma_chan_free(host->rx_chan);
929 }
930 }
931
932 static void au1xmmc_enable_sdio_irq(struct mmc_host *mmc, int en)
933 {
934 struct au1xmmc_host *host = mmc_priv(mmc);
935
936 if (en)
937 IRQ_ON(host, SD_CONFIG_SI);
938 else
939 IRQ_OFF(host, SD_CONFIG_SI);
940 }
941
942 static const struct mmc_host_ops au1xmmc_ops = {
943 .request = au1xmmc_request,
944 .set_ios = au1xmmc_set_ios,
945 .get_ro = au1xmmc_card_readonly,
946 .get_cd = au1xmmc_card_inserted,
947 .enable_sdio_irq = au1xmmc_enable_sdio_irq,
948 };
949
950 static int au1xmmc_probe(struct platform_device *pdev)
951 {
952 struct mmc_host *mmc;
953 struct au1xmmc_host *host;
954 struct resource *r;
955 int ret, iflag;
956
957 mmc = mmc_alloc_host(sizeof(struct au1xmmc_host), &pdev->dev);
958 if (!mmc) {
959 dev_err(&pdev->dev, "no memory for mmc_host\n");
960 ret = -ENOMEM;
961 goto out0;
962 }
963
964 host = mmc_priv(mmc);
965 host->mmc = mmc;
966 host->platdata = pdev->dev.platform_data;
967 host->pdev = pdev;
968
969 ret = -ENODEV;
970 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
971 if (!r) {
972 dev_err(&pdev->dev, "no mmio defined\n");
973 goto out1;
974 }
975
976 host->ioarea = request_mem_region(r->start, resource_size(r),
977 pdev->name);
978 if (!host->ioarea) {
979 dev_err(&pdev->dev, "mmio already in use\n");
980 goto out1;
981 }
982
983 host->iobase = ioremap(r->start, 0x3c);
984 if (!host->iobase) {
985 dev_err(&pdev->dev, "cannot remap mmio\n");
986 goto out2;
987 }
988
989 r = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
990 if (!r) {
991 dev_err(&pdev->dev, "no IRQ defined\n");
992 goto out3;
993 }
994 host->irq = r->start;
995
996 mmc->ops = &au1xmmc_ops;
997
998 mmc->f_min = 450000;
999 mmc->f_max = 24000000;
1000
1001 mmc->max_blk_size = 2048;
1002 mmc->max_blk_count = 512;
1003
1004 mmc->ocr_avail = AU1XMMC_OCR;
1005 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
1006 mmc->max_segs = AU1XMMC_DESCRIPTOR_COUNT;
1007
1008 iflag = IRQF_SHARED; /* Au1100/Au1200: one int for both ctrls */
1009
1010 switch (alchemy_get_cputype()) {
1011 case ALCHEMY_CPU_AU1100:
1012 mmc->max_seg_size = AU1100_MMC_DESCRIPTOR_SIZE;
1013 break;
1014 case ALCHEMY_CPU_AU1200:
1015 mmc->max_seg_size = AU1200_MMC_DESCRIPTOR_SIZE;
1016 break;
1017 case ALCHEMY_CPU_AU1300:
1018 iflag = 0; /* nothing is shared */
1019 mmc->max_seg_size = AU1200_MMC_DESCRIPTOR_SIZE;
1020 mmc->f_max = 52000000;
1021 if (host->ioarea->start == AU1100_SD0_PHYS_ADDR)
1022 mmc->caps |= MMC_CAP_8_BIT_DATA;
1023 break;
1024 }
1025
1026 ret = request_irq(host->irq, au1xmmc_irq, iflag, DRIVER_NAME, host);
1027 if (ret) {
1028 dev_err(&pdev->dev, "cannot grab IRQ\n");
1029 goto out3;
1030 }
1031
1032 host->clk = clk_get(&pdev->dev, ALCHEMY_PERIPH_CLK);
1033 if (IS_ERR(host->clk)) {
1034 dev_err(&pdev->dev, "cannot find clock\n");
1035 ret = PTR_ERR(host->clk);
1036 goto out_irq;
1037 }
1038
1039 ret = clk_prepare_enable(host->clk);
1040 if (ret) {
1041 dev_err(&pdev->dev, "cannot enable clock\n");
1042 goto out_clk;
1043 }
1044
1045 host->status = HOST_S_IDLE;
1046
1047 /* board-specific carddetect setup, if any */
1048 if (host->platdata && host->platdata->cd_setup) {
1049 ret = host->platdata->cd_setup(mmc, 1);
1050 if (ret) {
1051 dev_warn(&pdev->dev, "board CD setup failed\n");
1052 mmc->caps |= MMC_CAP_NEEDS_POLL;
1053 }
1054 } else
1055 mmc->caps |= MMC_CAP_NEEDS_POLL;
1056
1057 /* platform may not be able to use all advertised caps */
1058 if (host->platdata)
1059 mmc->caps &= ~(host->platdata->mask_host_caps);
1060
1061 tasklet_init(&host->data_task, au1xmmc_tasklet_data,
1062 (unsigned long)host);
1063
1064 tasklet_init(&host->finish_task, au1xmmc_tasklet_finish,
1065 (unsigned long)host);
1066
1067 if (has_dbdma()) {
1068 ret = au1xmmc_dbdma_init(host);
1069 if (ret)
1070 pr_info(DRIVER_NAME ": DBDMA init failed; using PIO\n");
1071 }
1072
1073 #ifdef CONFIG_LEDS_CLASS
1074 if (host->platdata && host->platdata->led) {
1075 struct led_classdev *led = host->platdata->led;
1076 led->name = mmc_hostname(mmc);
1077 led->brightness = LED_OFF;
1078 led->default_trigger = mmc_hostname(mmc);
1079 ret = led_classdev_register(mmc_dev(mmc), led);
1080 if (ret)
1081 goto out5;
1082 }
1083 #endif
1084
1085 au1xmmc_reset_controller(host);
1086
1087 ret = mmc_add_host(mmc);
1088 if (ret) {
1089 dev_err(&pdev->dev, "cannot add mmc host\n");
1090 goto out6;
1091 }
1092
1093 platform_set_drvdata(pdev, host);
1094
1095 pr_info(DRIVER_NAME ": MMC Controller %d set up at %p"
1096 " (mode=%s)\n", pdev->id, host->iobase,
1097 host->flags & HOST_F_DMA ? "dma" : "pio");
1098
1099 return 0; /* all ok */
1100
1101 out6:
1102 #ifdef CONFIG_LEDS_CLASS
1103 if (host->platdata && host->platdata->led)
1104 led_classdev_unregister(host->platdata->led);
1105 out5:
1106 #endif
1107 __raw_writel(0, HOST_ENABLE(host));
1108 __raw_writel(0, HOST_CONFIG(host));
1109 __raw_writel(0, HOST_CONFIG2(host));
1110 wmb(); /* drain writebuffer */
1111
1112 if (host->flags & HOST_F_DBDMA)
1113 au1xmmc_dbdma_shutdown(host);
1114
1115 tasklet_kill(&host->data_task);
1116 tasklet_kill(&host->finish_task);
1117
1118 if (host->platdata && host->platdata->cd_setup &&
1119 !(mmc->caps & MMC_CAP_NEEDS_POLL))
1120 host->platdata->cd_setup(mmc, 0);
1121 out_clk:
1122 clk_disable_unprepare(host->clk);
1123 clk_put(host->clk);
1124 out_irq:
1125 free_irq(host->irq, host);
1126 out3:
1127 iounmap((void *)host->iobase);
1128 out2:
1129 release_resource(host->ioarea);
1130 kfree(host->ioarea);
1131 out1:
1132 mmc_free_host(mmc);
1133 out0:
1134 return ret;
1135 }
1136
1137 static int au1xmmc_remove(struct platform_device *pdev)
1138 {
1139 struct au1xmmc_host *host = platform_get_drvdata(pdev);
1140
1141 if (host) {
1142 mmc_remove_host(host->mmc);
1143
1144 #ifdef CONFIG_LEDS_CLASS
1145 if (host->platdata && host->platdata->led)
1146 led_classdev_unregister(host->platdata->led);
1147 #endif
1148
1149 if (host->platdata && host->platdata->cd_setup &&
1150 !(host->mmc->caps & MMC_CAP_NEEDS_POLL))
1151 host->platdata->cd_setup(host->mmc, 0);
1152
1153 __raw_writel(0, HOST_ENABLE(host));
1154 __raw_writel(0, HOST_CONFIG(host));
1155 __raw_writel(0, HOST_CONFIG2(host));
1156 wmb(); /* drain writebuffer */
1157
1158 tasklet_kill(&host->data_task);
1159 tasklet_kill(&host->finish_task);
1160
1161 if (host->flags & HOST_F_DBDMA)
1162 au1xmmc_dbdma_shutdown(host);
1163
1164 au1xmmc_set_power(host, 0);
1165
1166 clk_disable_unprepare(host->clk);
1167 clk_put(host->clk);
1168
1169 free_irq(host->irq, host);
1170 iounmap((void *)host->iobase);
1171 release_resource(host->ioarea);
1172 kfree(host->ioarea);
1173
1174 mmc_free_host(host->mmc);
1175 }
1176 return 0;
1177 }
1178
1179 #ifdef CONFIG_PM
1180 static int au1xmmc_suspend(struct platform_device *pdev, pm_message_t state)
1181 {
1182 struct au1xmmc_host *host = platform_get_drvdata(pdev);
1183
1184 __raw_writel(0, HOST_CONFIG2(host));
1185 __raw_writel(0, HOST_CONFIG(host));
1186 __raw_writel(0xffffffff, HOST_STATUS(host));
1187 __raw_writel(0, HOST_ENABLE(host));
1188 wmb(); /* drain writebuffer */
1189
1190 return 0;
1191 }
1192
1193 static int au1xmmc_resume(struct platform_device *pdev)
1194 {
1195 struct au1xmmc_host *host = platform_get_drvdata(pdev);
1196
1197 au1xmmc_reset_controller(host);
1198
1199 return 0;
1200 }
1201 #else
1202 #define au1xmmc_suspend NULL
1203 #define au1xmmc_resume NULL
1204 #endif
1205
1206 static struct platform_driver au1xmmc_driver = {
1207 .probe = au1xmmc_probe,
1208 .remove = au1xmmc_remove,
1209 .suspend = au1xmmc_suspend,
1210 .resume = au1xmmc_resume,
1211 .driver = {
1212 .name = DRIVER_NAME,
1213 },
1214 };
1215
1216 static int __init au1xmmc_init(void)
1217 {
1218 if (has_dbdma()) {
1219 /* DSCR_CMD0_ALWAYS has a stride of 32 bits, we need a stride
1220 * of 8 bits. And since devices are shared, we need to create
1221 * our own to avoid freaking out other devices.
1222 */
1223 memid = au1xxx_ddma_add_device(&au1xmmc_mem_dbdev);
1224 if (!memid)
1225 pr_err("au1xmmc: cannot add memory dbdma\n");
1226 }
1227 return platform_driver_register(&au1xmmc_driver);
1228 }
1229
1230 static void __exit au1xmmc_exit(void)
1231 {
1232 if (has_dbdma() && memid)
1233 au1xxx_ddma_del_device(memid);
1234
1235 platform_driver_unregister(&au1xmmc_driver);
1236 }
1237
1238 module_init(au1xmmc_init);
1239 module_exit(au1xmmc_exit);
1240
1241 MODULE_AUTHOR("Advanced Micro Devices, Inc");
1242 MODULE_DESCRIPTION("MMC/SD driver for the Alchemy Au1XXX");
1243 MODULE_LICENSE("GPL");
1244 MODULE_ALIAS("platform:au1xxx-mmc");
Linux with added FPC-III support