drivers/usb/dwc3/dwc3-omap.c

   1 /**
   2  * dwc3-omap.c - OMAP Specific Glue layer
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions, and the following disclaimer,
  14  *    without modification.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  * 3. The names of the above-listed copyright holders may not be used
  19  *    to endorse or promote products derived from this software without
  20  *    specific prior written permission.
  21  *
  22  * ALTERNATIVELY, this software may be distributed under the terms of the
  23  * GNU General Public License ("GPL") version 2, as published by the Free
  24  * Software Foundation.
  25  *
  26  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  27  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  28  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  29  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  30  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  31  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  32  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  33  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  34  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  35  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  36  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  37  */
  38
  39 #include <linux/module.h>
  40 #include <linux/kernel.h>
  41 #include <linux/slab.h>
  42 #include <linux/interrupt.h>
  43 #include <linux/spinlock.h>
  44 #include <linux/platform_device.h>
  45 #include <linux/platform_data/dwc3-omap.h>
  46 #include <linux/dma-mapping.h>
  47 #include <linux/ioport.h>
  48 #include <linux/io.h>
  49 #include <linux/of.h>
  50
  51 #include <linux/usb/otg.h>
  52 #include <linux/usb/nop-usb-xceiv.h>
  53
  54 #include "core.h"
  55
  56 /*
  57  * All these registers belong to OMAP's Wrapper around the
  58  * DesignWare USB3 Core.
  59  */
  60
  61 #define USBOTGSS_REVISION                       0x0000
  62 #define USBOTGSS_SYSCONFIG                      0x0010
  63 #define USBOTGSS_IRQ_EOI                        0x0020
  64 #define USBOTGSS_IRQSTATUS_RAW_0                0x0024
  65 #define USBOTGSS_IRQSTATUS_0                    0x0028
  66 #define USBOTGSS_IRQENABLE_SET_0                0x002c
  67 #define USBOTGSS_IRQENABLE_CLR_0                0x0030
  68 #define USBOTGSS_IRQSTATUS_RAW_1                0x0034
  69 #define USBOTGSS_IRQSTATUS_1                    0x0038
  70 #define USBOTGSS_IRQENABLE_SET_1                0x003c
  71 #define USBOTGSS_IRQENABLE_CLR_1                0x0040
  72 #define USBOTGSS_UTMI_OTG_CTRL                  0x0080
  73 #define USBOTGSS_UTMI_OTG_STATUS                0x0084
  74 #define USBOTGSS_MMRAM_OFFSET                   0x0100
  75 #define USBOTGSS_FLADJ                          0x0104
  76 #define USBOTGSS_DEBUG_CFG                      0x0108
  77 #define USBOTGSS_DEBUG_DATA                     0x010c
  78
  79 /* SYSCONFIG REGISTER */
  80 #define USBOTGSS_SYSCONFIG_DMADISABLE           (1 << 16)
  81 #define USBOTGSS_SYSCONFIG_STANDBYMODE(x)       ((x) << 4)
  82
  83 #define USBOTGSS_STANDBYMODE_FORCE_STANDBY      0
  84 #define USBOTGSS_STANDBYMODE_NO_STANDBY         1
  85 #define USBOTGSS_STANDBYMODE_SMART_STANDBY      2
  86 #define USBOTGSS_STANDBYMODE_SMART_WAKEUP       3
  87
  88 #define USBOTGSS_STANDBYMODE_MASK               (0x03 << 4)
  89
  90 #define USBOTGSS_SYSCONFIG_IDLEMODE(x)          ((x) << 2)
  91
  92 #define USBOTGSS_IDLEMODE_FORCE_IDLE            0
  93 #define USBOTGSS_IDLEMODE_NO_IDLE               1
  94 #define USBOTGSS_IDLEMODE_SMART_IDLE            2
  95 #define USBOTGSS_IDLEMODE_SMART_WAKEUP          3
  96
  97 #define USBOTGSS_IDLEMODE_MASK                  (0x03 << 2)
  98
  99 /* IRQ_EOI REGISTER */
 100 #define USBOTGSS_IRQ_EOI_LINE_NUMBER            (1 << 0)
 101
 102 /* IRQS0 BITS */
 103 #define USBOTGSS_IRQO_COREIRQ_ST                (1 << 0)
 104
 105 /* IRQ1 BITS */
 106 #define USBOTGSS_IRQ1_DMADISABLECLR             (1 << 17)
 107 #define USBOTGSS_IRQ1_OEVT                      (1 << 16)
 108 #define USBOTGSS_IRQ1_DRVVBUS_RISE              (1 << 13)
 109 #define USBOTGSS_IRQ1_CHRGVBUS_RISE             (1 << 12)
 110 #define USBOTGSS_IRQ1_DISCHRGVBUS_RISE          (1 << 11)
 111 #define USBOTGSS_IRQ1_IDPULLUP_RISE             (1 << 8)
 112 #define USBOTGSS_IRQ1_DRVVBUS_FALL              (1 << 5)
 113 #define USBOTGSS_IRQ1_CHRGVBUS_FALL             (1 << 4)
 114 #define USBOTGSS_IRQ1_DISCHRGVBUS_FALL          (1 << 3)
 115 #define USBOTGSS_IRQ1_IDPULLUP_FALL             (1 << 0)
 116
 117 /* UTMI_OTG_CTRL REGISTER */
 118 #define USBOTGSS_UTMI_OTG_CTRL_DRVVBUS          (1 << 5)
 119 #define USBOTGSS_UTMI_OTG_CTRL_CHRGVBUS         (1 << 4)
 120 #define USBOTGSS_UTMI_OTG_CTRL_DISCHRGVBUS      (1 << 3)
 121 #define USBOTGSS_UTMI_OTG_CTRL_IDPULLUP         (1 << 0)
 122
 123 /* UTMI_OTG_STATUS REGISTER */
 124 #define USBOTGSS_UTMI_OTG_STATUS_SW_MODE        (1 << 31)
 125 #define USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT   (1 << 9)
 126 #define USBOTGSS_UTMI_OTG_STATUS_TXBITSTUFFENABLE (1 << 8)
 127 #define USBOTGSS_UTMI_OTG_STATUS_IDDIG          (1 << 4)
 128 #define USBOTGSS_UTMI_OTG_STATUS_SESSEND        (1 << 3)
 129 #define USBOTGSS_UTMI_OTG_STATUS_SESSVALID      (1 << 2)
 130 #define USBOTGSS_UTMI_OTG_STATUS_VBUSVALID      (1 << 1)
 131
 132 struct dwc3_omap {
 133         /* device lock */
 134         spinlock_t              lock;
 135
 136         struct platform_device  *dwc3;
 137         struct platform_device  *usb2_phy;
 138         struct platform_device  *usb3_phy;
 139         struct device           *dev;
 140
 141         int                     irq;
 142         void __iomem            *base;
 143
 144         void                    *context;
 145         u32                     resource_size;
 146
 147         u32                     dma_status:1;
 148 };
 149
 150 static inline u32 dwc3_omap_readl(void __iomem *base, u32 offset)
 151 {
 152         return readl(base + offset);
 153 }
 154
 155 static inline void dwc3_omap_writel(void __iomem *base, u32 offset, u32 value)
 156 {
 157         writel(value, base + offset);
 158 }
 159
 160 static int dwc3_omap_register_phys(struct dwc3_omap *omap)
 161 {
 162         struct nop_usb_xceiv_platform_data pdata;
 163         struct platform_device  *pdev;
 164         int                     ret;
 165
 166         memset(&pdata, 0x00, sizeof(pdata));
 167
 168         pdev = platform_device_alloc("nop_usb_xceiv", 0);
 169         if (!pdev)
 170                 return -ENOMEM;
 171
 172         omap->usb2_phy = pdev;
 173         pdata.type = USB_PHY_TYPE_USB2;
 174
 175         ret = platform_device_add_data(omap->usb2_phy, &pdata, sizeof(pdata));
 176         if (ret)
 177                 goto err1;
 178
 179         pdev = platform_device_alloc("nop_usb_xceiv", 1);
 180         if (!pdev) {
 181                 ret = -ENOMEM;
 182                 goto err1;
 183         }
 184
 185         omap->usb3_phy = pdev;
 186         pdata.type = USB_PHY_TYPE_USB3;
 187
 188         ret = platform_device_add_data(omap->usb3_phy, &pdata, sizeof(pdata));
 189         if (ret)
 190                 goto err2;
 191
 192         ret = platform_device_add(omap->usb2_phy);
 193         if (ret)
 194                 goto err2;
 195
 196         ret = platform_device_add(omap->usb3_phy);
 197         if (ret)
 198                 goto err3;
 199
 200         return 0;
 201
 202 err3:
 203         platform_device_del(omap->usb2_phy);
 204
 205 err2:
 206         platform_device_put(omap->usb3_phy);
 207
 208 err1:
 209         platform_device_put(omap->usb2_phy);
 210
 211         return ret;
 212 }
 213
 214 static irqreturn_t dwc3_omap_interrupt(int irq, void *_omap)
 215 {
 216         struct dwc3_omap        *omap = _omap;
 217         u32                     reg;
 218
 219         spin_lock(&omap->lock);
 220
 221         reg = dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_1);
 222
 223         if (reg & USBOTGSS_IRQ1_DMADISABLECLR) {
 224                 dev_dbg(omap->dev, "DMA Disable was Cleared\n");
 225                 omap->dma_status = false;
 226         }
 227
 228         if (reg & USBOTGSS_IRQ1_OEVT)
 229                 dev_dbg(omap->dev, "OTG Event\n");
 230
 231         if (reg & USBOTGSS_IRQ1_DRVVBUS_RISE)
 232                 dev_dbg(omap->dev, "DRVVBUS Rise\n");
 233
 234         if (reg & USBOTGSS_IRQ1_CHRGVBUS_RISE)
 235                 dev_dbg(omap->dev, "CHRGVBUS Rise\n");
 236
 237         if (reg & USBOTGSS_IRQ1_DISCHRGVBUS_RISE)
 238                 dev_dbg(omap->dev, "DISCHRGVBUS Rise\n");
 239
 240         if (reg & USBOTGSS_IRQ1_IDPULLUP_RISE)
 241                 dev_dbg(omap->dev, "IDPULLUP Rise\n");
 242
 243         if (reg & USBOTGSS_IRQ1_DRVVBUS_FALL)
 244                 dev_dbg(omap->dev, "DRVVBUS Fall\n");
 245
 246         if (reg & USBOTGSS_IRQ1_CHRGVBUS_FALL)
 247                 dev_dbg(omap->dev, "CHRGVBUS Fall\n");
 248
 249         if (reg & USBOTGSS_IRQ1_DISCHRGVBUS_FALL)
 250                 dev_dbg(omap->dev, "DISCHRGVBUS Fall\n");
 251
 252         if (reg & USBOTGSS_IRQ1_IDPULLUP_FALL)
 253                 dev_dbg(omap->dev, "IDPULLUP Fall\n");
 254
 255         dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_1, reg);
 256
 257         reg = dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_0);
 258         dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_0, reg);
 259
 260         spin_unlock(&omap->lock);
 261
 262         return IRQ_HANDLED;
 263 }
 264
 265 static int dwc3_omap_probe(struct platform_device *pdev)
 266 {
 267         struct dwc3_omap_data   *pdata = pdev->dev.platform_data;
 268         struct device_node      *node = pdev->dev.of_node;
 269
 270         struct platform_device  *dwc3;
 271         struct dwc3_omap        *omap;
 272         struct resource         *res;
 273         struct device           *dev = &pdev->dev;
 274
 275         int                     size;
 276         int                     ret = -ENOMEM;
 277         int                     irq;
 278
 279         const u32               *utmi_mode;
 280         u32                     reg;
 281
 282         void __iomem            *base;
 283         void                    *context;
 284
 285         omap = devm_kzalloc(dev, sizeof(*omap), GFP_KERNEL);
 286         if (!omap) {
 287                 dev_err(dev, "not enough memory\n");
 288                 return -ENOMEM;
 289         }
 290
 291         platform_set_drvdata(pdev, omap);
 292
 293         irq = platform_get_irq(pdev, 1);
 294         if (irq < 0) {
 295                 dev_err(dev, "missing IRQ resource\n");
 296                 return -EINVAL;
 297         }
 298
 299         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 300         if (!res) {
 301                 dev_err(dev, "missing memory base resource\n");
 302                 return -EINVAL;
 303         }
 304
 305         base = devm_ioremap_nocache(dev, res->start, resource_size(res));
 306         if (!base) {
 307                 dev_err(dev, "ioremap failed\n");
 308                 return -ENOMEM;
 309         }
 310
 311         ret = dwc3_omap_register_phys(omap);
 312         if (ret) {
 313                 dev_err(dev, "couldn't register PHYs\n");
 314                 return ret;
 315         }
 316
 317         dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO);
 318         if (!dwc3) {
 319                 dev_err(dev, "couldn't allocate dwc3 device\n");
 320                 return -ENOMEM;
 321         }
 322
 323         context = devm_kzalloc(dev, resource_size(res), GFP_KERNEL);
 324         if (!context) {
 325                 dev_err(dev, "couldn't allocate dwc3 context memory\n");
 326                 goto err2;
 327         }
 328
 329         spin_lock_init(&omap->lock);
 330         dma_set_coherent_mask(&dwc3->dev, dev->coherent_dma_mask);
 331
 332         dwc3->dev.parent = dev;
 333         dwc3->dev.dma_mask = dev->dma_mask;
 334         dwc3->dev.dma_parms = dev->dma_parms;
 335         omap->resource_size = resource_size(res);
 336         omap->context   = context;
 337         omap->dev       = dev;
 338         omap->irq       = irq;
 339         omap->base      = base;
 340         omap->dwc3      = dwc3;
 341
 342         reg = dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_STATUS);
 343
 344         utmi_mode = of_get_property(node, "utmi-mode", &size);
 345         if (utmi_mode && size == sizeof(*utmi_mode)) {
 346                 reg |= *utmi_mode;
 347         } else {
 348                 if (!pdata) {
 349                         dev_dbg(dev, "missing platform data\n");
 350                 } else {
 351                         switch (pdata->utmi_mode) {
 352                         case DWC3_OMAP_UTMI_MODE_SW:
 353                                 reg |= USBOTGSS_UTMI_OTG_STATUS_SW_MODE;
 354                                 break;
 355                         case DWC3_OMAP_UTMI_MODE_HW:
 356                                 reg &= ~USBOTGSS_UTMI_OTG_STATUS_SW_MODE;
 357                                 break;
 358                         default:
 359                                 dev_dbg(dev, "UNKNOWN utmi mode %d\n",
 360                                                 pdata->utmi_mode);
 361                         }
 362                 }
 363         }
 364
 365         dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_STATUS, reg);
 366
 367         /* check the DMA Status */
 368         reg = dwc3_omap_readl(omap->base, USBOTGSS_SYSCONFIG);
 369         omap->dma_status = !!(reg & USBOTGSS_SYSCONFIG_DMADISABLE);
 370
 371         /* Set No-Idle and No-Standby */
 372         reg &= ~(USBOTGSS_STANDBYMODE_MASK
 373                         | USBOTGSS_IDLEMODE_MASK);
 374
 375         reg |= (USBOTGSS_SYSCONFIG_STANDBYMODE(USBOTGSS_STANDBYMODE_NO_STANDBY)
 376                 | USBOTGSS_SYSCONFIG_IDLEMODE(USBOTGSS_IDLEMODE_NO_IDLE));
 377
 378         dwc3_omap_writel(omap->base, USBOTGSS_SYSCONFIG, reg);
 379
 380         ret = devm_request_irq(dev, omap->irq, dwc3_omap_interrupt, 0,
 381                         "dwc3-omap", omap);
 382         if (ret) {
 383                 dev_err(dev, "failed to request IRQ #%d --> %d\n",
 384                                 omap->irq, ret);
 385                 goto err2;
 386         }
 387
 388         /* enable all IRQs */
 389         reg = USBOTGSS_IRQO_COREIRQ_ST;
 390         dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_0, reg);
 391
 392         reg = (USBOTGSS_IRQ1_OEVT |
 393                         USBOTGSS_IRQ1_DRVVBUS_RISE |
 394                         USBOTGSS_IRQ1_CHRGVBUS_RISE |
 395                         USBOTGSS_IRQ1_DISCHRGVBUS_RISE |
 396                         USBOTGSS_IRQ1_IDPULLUP_RISE |
 397                         USBOTGSS_IRQ1_DRVVBUS_FALL |
 398                         USBOTGSS_IRQ1_CHRGVBUS_FALL |
 399                         USBOTGSS_IRQ1_DISCHRGVBUS_FALL |
 400                         USBOTGSS_IRQ1_IDPULLUP_FALL);
 401
 402         dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_1, reg);
 403
 404         ret = platform_device_add_resources(dwc3, pdev->resource,
 405                         pdev->num_resources);
 406         if (ret) {
 407                 dev_err(dev, "couldn't add resources to dwc3 device\n");
 408                 goto err2;
 409         }
 410
 411         ret = platform_device_add(dwc3);
 412         if (ret) {
 413                 dev_err(dev, "failed to register dwc3 device\n");
 414                 goto err2;
 415         }
 416
 417         return 0;
 418
 419 err2:
 420         platform_device_put(dwc3);
 421         return ret;
 422 }
 423
 424 static int dwc3_omap_remove(struct platform_device *pdev)
 425 {
 426         struct dwc3_omap        *omap = platform_get_drvdata(pdev);
 427
 428         platform_device_unregister(omap->dwc3);
 429         platform_device_unregister(omap->usb2_phy);
 430         platform_device_unregister(omap->usb3_phy);
 431         return 0;
 432 }
 433
 434 static const struct of_device_id of_dwc3_matach[] = {
 435         {
 436                 "ti,dwc3",
 437         },
 438         { },
 439 };
 440 MODULE_DEVICE_TABLE(of, of_dwc3_matach);
 441
 442 static struct platform_driver dwc3_omap_driver = {
 443         .probe          = dwc3_omap_probe,
 444         .remove         = dwc3_omap_remove,
 445         .driver         = {
 446                 .name   = "omap-dwc3",
 447                 .of_match_table = of_dwc3_matach,
 448         },
 449 };
 450
 451 module_platform_driver(dwc3_omap_driver);
 452
 453 MODULE_ALIAS("platform:omap-dwc3");
 454 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
 455 MODULE_LICENSE("Dual BSD/GPL");
 456 MODULE_DESCRIPTION("DesignWare USB3 OMAP Glue Layer");