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Linux 3.0.58
[linux/fpc-iii.git] / drivers / pci / probe.c
blob0d5d0bfcb6631060a946fdc4480a1d096392602a
1 /*
2 * probe.c - PCI detection and setup code
3 */
4
5 #include <linux/kernel.h>
6 #include <linux/delay.h>
7 #include <linux/init.h>
8 #include <linux/pci.h>
9 #include <linux/slab.h>
10 #include <linux/module.h>
11 #include <linux/cpumask.h>
12 #include <linux/pci-aspm.h>
13 #include "pci.h"
14
15 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
16 #define CARDBUS_RESERVE_BUSNR 3
17
18 /* Ugh. Need to stop exporting this to modules. */
19 LIST_HEAD(pci_root_buses);
20 EXPORT_SYMBOL(pci_root_buses);
21
22
23 static int find_anything(struct device *dev, void *data)
24 {
25 return 1;
26 }
27
28 /*
29 * Some device drivers need know if pci is initiated.
30 * Basically, we think pci is not initiated when there
31 * is no device to be found on the pci_bus_type.
32 */
33 int no_pci_devices(void)
34 {
35 struct device *dev;
36 int no_devices;
37
38 dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything);
39 no_devices = (dev == NULL);
40 put_device(dev);
41 return no_devices;
42 }
43 EXPORT_SYMBOL(no_pci_devices);
44
45 /*
46 * PCI Bus Class
47 */
48 static void release_pcibus_dev(struct device *dev)
49 {
50 struct pci_bus *pci_bus = to_pci_bus(dev);
51
52 if (pci_bus->bridge)
53 put_device(pci_bus->bridge);
54 pci_bus_remove_resources(pci_bus);
55 kfree(pci_bus);
56 }
57
58 static struct class pcibus_class = {
59 .name = "pci_bus",
60 .dev_release = &release_pcibus_dev,
61 .dev_attrs = pcibus_dev_attrs,
62 };
63
64 static int __init pcibus_class_init(void)
65 {
66 return class_register(&pcibus_class);
67 }
68 postcore_initcall(pcibus_class_init);
69
70 /*
71 * Translate the low bits of the PCI base
72 * to the resource type
73 */
74 static inline unsigned int pci_calc_resource_flags(unsigned int flags)
75 {
76 if (flags & PCI_BASE_ADDRESS_SPACE_IO)
77 return IORESOURCE_IO;
78
79 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
80 return IORESOURCE_MEM | IORESOURCE_PREFETCH;
81
82 return IORESOURCE_MEM;
83 }
84
85 static u64 pci_size(u64 base, u64 maxbase, u64 mask)
86 {
87 u64 size = mask & maxbase; /* Find the significant bits */
88 if (!size)
89 return 0;
90
91 /* Get the lowest of them to find the decode size, and
92 from that the extent. */
93 size = (size & ~(size-1)) - 1;
94
95 /* base == maxbase can be valid only if the BAR has
96 already been programmed with all 1s. */
97 if (base == maxbase && ((base | size) & mask) != mask)
98 return 0;
99
100 return size;
101 }
102
103 static inline enum pci_bar_type decode_bar(struct resource *res, u32 bar)
104 {
105 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
106 res->flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
107 return pci_bar_io;
108 }
109
110 res->flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
111
112 if (res->flags & PCI_BASE_ADDRESS_MEM_TYPE_64)
113 return pci_bar_mem64;
114 return pci_bar_mem32;
115 }
116
117 /**
118 * pci_read_base - read a PCI BAR
119 * @dev: the PCI device
120 * @type: type of the BAR
121 * @res: resource buffer to be filled in
122 * @pos: BAR position in the config space
123 *
124 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
125 */
126 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
127 struct resource *res, unsigned int pos)
128 {
129 u32 l, sz, mask;
130 u16 orig_cmd;
131
132 mask = type ? PCI_ROM_ADDRESS_MASK : ~0;
133
134 if (!dev->mmio_always_on) {
135 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);
136 pci_write_config_word(dev, PCI_COMMAND,
137 orig_cmd & ~(PCI_COMMAND_MEMORY | PCI_COMMAND_IO));
138 }
139
140 res->name = pci_name(dev);
141
142 pci_read_config_dword(dev, pos, &l);
143 pci_write_config_dword(dev, pos, l | mask);
144 pci_read_config_dword(dev, pos, &sz);
145 pci_write_config_dword(dev, pos, l);
146
147 if (!dev->mmio_always_on)
148 pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
149
150 /*
151 * All bits set in sz means the device isn't working properly.
152 * If the BAR isn't implemented, all bits must be 0. If it's a
153 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
154 * 1 must be clear.
155 */
156 if (!sz || sz == 0xffffffff)
157 goto fail;
158
159 /*
160 * I don't know how l can have all bits set. Copied from old code.
161 * Maybe it fixes a bug on some ancient platform.
162 */
163 if (l == 0xffffffff)
164 l = 0;
165
166 if (type == pci_bar_unknown) {
167 type = decode_bar(res, l);
168 res->flags |= pci_calc_resource_flags(l) | IORESOURCE_SIZEALIGN;
169 if (type == pci_bar_io) {
170 l &= PCI_BASE_ADDRESS_IO_MASK;
171 mask = PCI_BASE_ADDRESS_IO_MASK & (u32) IO_SPACE_LIMIT;
172 } else {
173 l &= PCI_BASE_ADDRESS_MEM_MASK;
174 mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
175 }
176 } else {
177 res->flags |= (l & IORESOURCE_ROM_ENABLE);
178 l &= PCI_ROM_ADDRESS_MASK;
179 mask = (u32)PCI_ROM_ADDRESS_MASK;
180 }
181
182 if (type == pci_bar_mem64) {
183 u64 l64 = l;
184 u64 sz64 = sz;
185 u64 mask64 = mask | (u64)~0 << 32;
186
187 pci_read_config_dword(dev, pos + 4, &l);
188 pci_write_config_dword(dev, pos + 4, ~0);
189 pci_read_config_dword(dev, pos + 4, &sz);
190 pci_write_config_dword(dev, pos + 4, l);
191
192 l64 |= ((u64)l << 32);
193 sz64 |= ((u64)sz << 32);
194
195 sz64 = pci_size(l64, sz64, mask64);
196
197 if (!sz64)
198 goto fail;
199
200 if ((sizeof(resource_size_t) < 8) && (sz64 > 0x100000000ULL)) {
201 dev_err(&dev->dev, "reg %x: can't handle 64-bit BAR\n",
202 pos);
203 goto fail;
204 }
205
206 res->flags |= IORESOURCE_MEM_64;
207 if ((sizeof(resource_size_t) < 8) && l) {
208 /* Address above 32-bit boundary; disable the BAR */
209 pci_write_config_dword(dev, pos, 0);
210 pci_write_config_dword(dev, pos + 4, 0);
211 res->start = 0;
212 res->end = sz64;
213 } else {
214 res->start = l64;
215 res->end = l64 + sz64;
216 dev_printk(KERN_DEBUG, &dev->dev, "reg %x: %pR\n",
217 pos, res);
218 }
219 } else {
220 sz = pci_size(l, sz, mask);
221
222 if (!sz)
223 goto fail;
224
225 res->start = l;
226 res->end = l + sz;
227
228 dev_printk(KERN_DEBUG, &dev->dev, "reg %x: %pR\n", pos, res);
229 }
230
231 out:
232 return (type == pci_bar_mem64) ? 1 : 0;
233 fail:
234 res->flags = 0;
235 goto out;
236 }
237
238 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
239 {
240 unsigned int pos, reg;
241
242 for (pos = 0; pos < howmany; pos++) {
243 struct resource *res = &dev->resource[pos];
244 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
245 pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
246 }
247
248 if (rom) {
249 struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
250 dev->rom_base_reg = rom;
251 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
252 IORESOURCE_READONLY | IORESOURCE_CACHEABLE |
253 IORESOURCE_SIZEALIGN;
254 __pci_read_base(dev, pci_bar_mem32, res, rom);
255 }
256 }
257
258 static void __devinit pci_read_bridge_io(struct pci_bus *child)
259 {
260 struct pci_dev *dev = child->self;
261 u8 io_base_lo, io_limit_lo;
262 unsigned long base, limit;
263 struct resource *res;
264
265 res = child->resource[0];
266 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
267 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
268 base = (io_base_lo & PCI_IO_RANGE_MASK) << 8;
269 limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8;
270
271 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
272 u16 io_base_hi, io_limit_hi;
273 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
274 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
275 base |= (io_base_hi << 16);
276 limit |= (io_limit_hi << 16);
277 }
278
279 if (base && base <= limit) {
280 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
281 if (!res->start)
282 res->start = base;
283 if (!res->end)
284 res->end = limit + 0xfff;
285 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
286 } else {
287 dev_printk(KERN_DEBUG, &dev->dev,
288 " bridge window [io %#06lx-%#06lx] (disabled)\n",
289 base, limit);
290 }
291 }
292
293 static void __devinit pci_read_bridge_mmio(struct pci_bus *child)
294 {
295 struct pci_dev *dev = child->self;
296 u16 mem_base_lo, mem_limit_lo;
297 unsigned long base, limit;
298 struct resource *res;
299
300 res = child->resource[1];
301 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
302 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
303 base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
304 limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
305 if (base && base <= limit) {
306 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
307 res->start = base;
308 res->end = limit + 0xfffff;
309 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
310 } else {
311 dev_printk(KERN_DEBUG, &dev->dev,
312 " bridge window [mem %#010lx-%#010lx] (disabled)\n",
313 base, limit + 0xfffff);
314 }
315 }
316
317 static void __devinit pci_read_bridge_mmio_pref(struct pci_bus *child)
318 {
319 struct pci_dev *dev = child->self;
320 u16 mem_base_lo, mem_limit_lo;
321 unsigned long base, limit;
322 struct resource *res;
323
324 res = child->resource[2];
325 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
326 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
327 base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
328 limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
329
330 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
331 u32 mem_base_hi, mem_limit_hi;
332 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
333 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
334
335 /*
336 * Some bridges set the base > limit by default, and some
337 * (broken) BIOSes do not initialize them. If we find
338 * this, just assume they are not being used.
339 */
340 if (mem_base_hi <= mem_limit_hi) {
341 #if BITS_PER_LONG == 64
342 base |= ((long) mem_base_hi) << 32;
343 limit |= ((long) mem_limit_hi) << 32;
344 #else
345 if (mem_base_hi || mem_limit_hi) {
346 dev_err(&dev->dev, "can't handle 64-bit "
347 "address space for bridge\n");
348 return;
349 }
350 #endif
351 }
352 }
353 if (base && base <= limit) {
354 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) |
355 IORESOURCE_MEM | IORESOURCE_PREFETCH;
356 if (res->flags & PCI_PREF_RANGE_TYPE_64)
357 res->flags |= IORESOURCE_MEM_64;
358 res->start = base;
359 res->end = limit + 0xfffff;
360 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
361 } else {
362 dev_printk(KERN_DEBUG, &dev->dev,
363 " bridge window [mem %#010lx-%#010lx pref] (disabled)\n",
364 base, limit + 0xfffff);
365 }
366 }
367
368 void __devinit pci_read_bridge_bases(struct pci_bus *child)
369 {
370 struct pci_dev *dev = child->self;
371 struct resource *res;
372 int i;
373
374 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */
375 return;
376
377 dev_info(&dev->dev, "PCI bridge to [bus %02x-%02x]%s\n",
378 child->secondary, child->subordinate,
379 dev->transparent ? " (subtractive decode)" : "");
380
381 pci_bus_remove_resources(child);
382 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
383 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
384
385 pci_read_bridge_io(child);
386 pci_read_bridge_mmio(child);
387 pci_read_bridge_mmio_pref(child);
388
389 if (dev->transparent) {
390 pci_bus_for_each_resource(child->parent, res, i) {
391 if (res) {
392 pci_bus_add_resource(child, res,
393 PCI_SUBTRACTIVE_DECODE);
394 dev_printk(KERN_DEBUG, &dev->dev,
395 " bridge window %pR (subtractive decode)\n",
396 res);
397 }
398 }
399 }
400 }
401
402 static struct pci_bus * pci_alloc_bus(void)
403 {
404 struct pci_bus *b;
405
406 b = kzalloc(sizeof(*b), GFP_KERNEL);
407 if (b) {
408 INIT_LIST_HEAD(&b->node);
409 INIT_LIST_HEAD(&b->children);
410 INIT_LIST_HEAD(&b->devices);
411 INIT_LIST_HEAD(&b->slots);
412 INIT_LIST_HEAD(&b->resources);
413 b->max_bus_speed = PCI_SPEED_UNKNOWN;
414 b->cur_bus_speed = PCI_SPEED_UNKNOWN;
415 }
416 return b;
417 }
418
419 static unsigned char pcix_bus_speed[] = {
420 PCI_SPEED_UNKNOWN, /* 0 */
421 PCI_SPEED_66MHz_PCIX, /* 1 */
422 PCI_SPEED_100MHz_PCIX, /* 2 */
423 PCI_SPEED_133MHz_PCIX, /* 3 */
424 PCI_SPEED_UNKNOWN, /* 4 */
425 PCI_SPEED_66MHz_PCIX_ECC, /* 5 */
426 PCI_SPEED_100MHz_PCIX_ECC, /* 6 */
427 PCI_SPEED_133MHz_PCIX_ECC, /* 7 */
428 PCI_SPEED_UNKNOWN, /* 8 */
429 PCI_SPEED_66MHz_PCIX_266, /* 9 */
430 PCI_SPEED_100MHz_PCIX_266, /* A */
431 PCI_SPEED_133MHz_PCIX_266, /* B */
432 PCI_SPEED_UNKNOWN, /* C */
433 PCI_SPEED_66MHz_PCIX_533, /* D */
434 PCI_SPEED_100MHz_PCIX_533, /* E */
435 PCI_SPEED_133MHz_PCIX_533 /* F */
436 };
437
438 static unsigned char pcie_link_speed[] = {
439 PCI_SPEED_UNKNOWN, /* 0 */
440 PCIE_SPEED_2_5GT, /* 1 */
441 PCIE_SPEED_5_0GT, /* 2 */
442 PCIE_SPEED_8_0GT, /* 3 */
443 PCI_SPEED_UNKNOWN, /* 4 */
444 PCI_SPEED_UNKNOWN, /* 5 */
445 PCI_SPEED_UNKNOWN, /* 6 */
446 PCI_SPEED_UNKNOWN, /* 7 */
447 PCI_SPEED_UNKNOWN, /* 8 */
448 PCI_SPEED_UNKNOWN, /* 9 */
449 PCI_SPEED_UNKNOWN, /* A */
450 PCI_SPEED_UNKNOWN, /* B */
451 PCI_SPEED_UNKNOWN, /* C */
452 PCI_SPEED_UNKNOWN, /* D */
453 PCI_SPEED_UNKNOWN, /* E */
454 PCI_SPEED_UNKNOWN /* F */
455 };
456
457 void pcie_update_link_speed(struct pci_bus *bus, u16 linksta)
458 {
459 bus->cur_bus_speed = pcie_link_speed[linksta & 0xf];
460 }
461 EXPORT_SYMBOL_GPL(pcie_update_link_speed);
462
463 static unsigned char agp_speeds[] = {
464 AGP_UNKNOWN,
465 AGP_1X,
466 AGP_2X,
467 AGP_4X,
468 AGP_8X
469 };
470
471 static enum pci_bus_speed agp_speed(int agp3, int agpstat)
472 {
473 int index = 0;
474
475 if (agpstat & 4)
476 index = 3;
477 else if (agpstat & 2)
478 index = 2;
479 else if (agpstat & 1)
480 index = 1;
481 else
482 goto out;
483
484 if (agp3) {
485 index += 2;
486 if (index == 5)
487 index = 0;
488 }
489
490 out:
491 return agp_speeds[index];
492 }
493
494
495 static void pci_set_bus_speed(struct pci_bus *bus)
496 {
497 struct pci_dev *bridge = bus->self;
498 int pos;
499
500 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP);
501 if (!pos)
502 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3);
503 if (pos) {
504 u32 agpstat, agpcmd;
505
506 pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat);
507 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7);
508
509 pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd);
510 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7);
511 }
512
513 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
514 if (pos) {
515 u16 status;
516 enum pci_bus_speed max;
517 pci_read_config_word(bridge, pos + 2, &status);
518
519 if (status & 0x8000) {
520 max = PCI_SPEED_133MHz_PCIX_533;
521 } else if (status & 0x4000) {
522 max = PCI_SPEED_133MHz_PCIX_266;
523 } else if (status & 0x0002) {
524 if (((status >> 12) & 0x3) == 2) {
525 max = PCI_SPEED_133MHz_PCIX_ECC;
526 } else {
527 max = PCI_SPEED_133MHz_PCIX;
528 }
529 } else {
530 max = PCI_SPEED_66MHz_PCIX;
531 }
532
533 bus->max_bus_speed = max;
534 bus->cur_bus_speed = pcix_bus_speed[(status >> 6) & 0xf];
535
536 return;
537 }
538
539 pos = pci_find_capability(bridge, PCI_CAP_ID_EXP);
540 if (pos) {
541 u32 linkcap;
542 u16 linksta;
543
544 pci_read_config_dword(bridge, pos + PCI_EXP_LNKCAP, &linkcap);
545 bus->max_bus_speed = pcie_link_speed[linkcap & 0xf];
546
547 pci_read_config_word(bridge, pos + PCI_EXP_LNKSTA, &linksta);
548 pcie_update_link_speed(bus, linksta);
549 }
550 }
551
552
553 static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
554 struct pci_dev *bridge, int busnr)
555 {
556 struct pci_bus *child;
557 int i;
558
559 /*
560 * Allocate a new bus, and inherit stuff from the parent..
561 */
562 child = pci_alloc_bus();
563 if (!child)
564 return NULL;
565
566 child->parent = parent;
567 child->ops = parent->ops;
568 child->sysdata = parent->sysdata;
569 child->bus_flags = parent->bus_flags;
570
571 /* initialize some portions of the bus device, but don't register it
572 * now as the parent is not properly set up yet. This device will get
573 * registered later in pci_bus_add_devices()
574 */
575 child->dev.class = &pcibus_class;
576 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
577
578 /*
579 * Set up the primary, secondary and subordinate
580 * bus numbers.
581 */
582 child->number = child->secondary = busnr;
583 child->primary = parent->secondary;
584 child->subordinate = 0xff;
585
586 if (!bridge)
587 return child;
588
589 child->self = bridge;
590 child->bridge = get_device(&bridge->dev);
591
592 pci_set_bus_speed(child);
593
594 /* Set up default resource pointers and names.. */
595 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
596 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
597 child->resource[i]->name = child->name;
598 }
599 bridge->subordinate = child;
600
601 return child;
602 }
603
604 struct pci_bus *__ref pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr)
605 {
606 struct pci_bus *child;
607
608 child = pci_alloc_child_bus(parent, dev, busnr);
609 if (child) {
610 down_write(&pci_bus_sem);
611 list_add_tail(&child->node, &parent->children);
612 up_write(&pci_bus_sem);
613 }
614 return child;
615 }
616
617 static void pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max)
618 {
619 struct pci_bus *parent = child->parent;
620
621 /* Attempts to fix that up are really dangerous unless
622 we're going to re-assign all bus numbers. */
623 if (!pcibios_assign_all_busses())
624 return;
625
626 while (parent->parent && parent->subordinate < max) {
627 parent->subordinate = max;
628 pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max);
629 parent = parent->parent;
630 }
631 }
632
633 /*
634 * If it's a bridge, configure it and scan the bus behind it.
635 * For CardBus bridges, we don't scan behind as the devices will
636 * be handled by the bridge driver itself.
637 *
638 * We need to process bridges in two passes -- first we scan those
639 * already configured by the BIOS and after we are done with all of
640 * them, we proceed to assigning numbers to the remaining buses in
641 * order to avoid overlaps between old and new bus numbers.
642 */
643 int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
644 {
645 struct pci_bus *child;
646 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
647 u32 buses, i, j = 0;
648 u16 bctl;
649 u8 primary, secondary, subordinate;
650 int broken = 0;
651
652 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
653 primary = buses & 0xFF;
654 secondary = (buses >> 8) & 0xFF;
655 subordinate = (buses >> 16) & 0xFF;
656
657 dev_dbg(&dev->dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
658 secondary, subordinate, pass);
659
660 if (!primary && (primary != bus->number) && secondary && subordinate) {
661 dev_warn(&dev->dev, "Primary bus is hard wired to 0\n");
662 primary = bus->number;
663 }
664
665 /* Check if setup is sensible at all */
666 if (!pass &&
667 (primary != bus->number || secondary <= bus->number ||
668 secondary > subordinate)) {
669 dev_info(&dev->dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n",
670 secondary, subordinate);
671 broken = 1;
672 }
673
674 /* Disable MasterAbortMode during probing to avoid reporting
675 of bus errors (in some architectures) */
676 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
677 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
678 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
679
680 if ((secondary || subordinate) && !pcibios_assign_all_busses() &&
681 !is_cardbus && !broken) {
682 unsigned int cmax;
683 /*
684 * Bus already configured by firmware, process it in the first
685 * pass and just note the configuration.
686 */
687 if (pass)
688 goto out;
689
690 /*
691 * If we already got to this bus through a different bridge,
692 * don't re-add it. This can happen with the i450NX chipset.
693 *
694 * However, we continue to descend down the hierarchy and
695 * scan remaining child buses.
696 */
697 child = pci_find_bus(pci_domain_nr(bus), secondary);
698 if (!child) {
699 child = pci_add_new_bus(bus, dev, secondary);
700 if (!child)
701 goto out;
702 child->primary = primary;
703 child->subordinate = subordinate;
704 child->bridge_ctl = bctl;
705 }
706
707 cmax = pci_scan_child_bus(child);
708 if (cmax > max)
709 max = cmax;
710 if (child->subordinate > max)
711 max = child->subordinate;
712 } else {
713 /*
714 * We need to assign a number to this bus which we always
715 * do in the second pass.
716 */
717 if (!pass) {
718 if (pcibios_assign_all_busses() || broken)
719 /* Temporarily disable forwarding of the
720 configuration cycles on all bridges in
721 this bus segment to avoid possible
722 conflicts in the second pass between two
723 bridges programmed with overlapping
724 bus ranges. */
725 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
726 buses & ~0xffffff);
727 goto out;
728 }
729
730 /* Clear errors */
731 pci_write_config_word(dev, PCI_STATUS, 0xffff);
732
733 /* Prevent assigning a bus number that already exists.
734 * This can happen when a bridge is hot-plugged */
735 if (pci_find_bus(pci_domain_nr(bus), max+1))
736 goto out;
737 child = pci_add_new_bus(bus, dev, ++max);
738 if (!child)
739 goto out;
740 buses = (buses & 0xff000000)
741 | ((unsigned int)(child->primary) << 0)
742 | ((unsigned int)(child->secondary) << 8)
743 | ((unsigned int)(child->subordinate) << 16);
744
745 /*
746 * yenta.c forces a secondary latency timer of 176.
747 * Copy that behaviour here.
748 */
749 if (is_cardbus) {
750 buses &= ~0xff000000;
751 buses |= CARDBUS_LATENCY_TIMER << 24;
752 }
753
754 /*
755 * We need to blast all three values with a single write.
756 */
757 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
758
759 if (!is_cardbus) {
760 child->bridge_ctl = bctl;
761 /*
762 * Adjust subordinate busnr in parent buses.
763 * We do this before scanning for children because
764 * some devices may not be detected if the bios
765 * was lazy.
766 */
767 pci_fixup_parent_subordinate_busnr(child, max);
768 /* Now we can scan all subordinate buses... */
769 max = pci_scan_child_bus(child);
770 /*
771 * now fix it up again since we have found
772 * the real value of max.
773 */
774 pci_fixup_parent_subordinate_busnr(child, max);
775 } else {
776 /*
777 * For CardBus bridges, we leave 4 bus numbers
778 * as cards with a PCI-to-PCI bridge can be
779 * inserted later.
780 */
781 for (i=0; i<CARDBUS_RESERVE_BUSNR; i++) {
782 struct pci_bus *parent = bus;
783 if (pci_find_bus(pci_domain_nr(bus),
784 max+i+1))
785 break;
786 while (parent->parent) {
787 if ((!pcibios_assign_all_busses()) &&
788 (parent->subordinate > max) &&
789 (parent->subordinate <= max+i)) {
790 j = 1;
791 }
792 parent = parent->parent;
793 }
794 if (j) {
795 /*
796 * Often, there are two cardbus bridges
797 * -- try to leave one valid bus number
798 * for each one.
799 */
800 i /= 2;
801 break;
802 }
803 }
804 max += i;
805 pci_fixup_parent_subordinate_busnr(child, max);
806 }
807 /*
808 * Set the subordinate bus number to its real value.
809 */
810 child->subordinate = max;
811 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
812 }
813
814 sprintf(child->name,
815 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
816 pci_domain_nr(bus), child->number);
817
818 /* Has only triggered on CardBus, fixup is in yenta_socket */
819 while (bus->parent) {
820 if ((child->subordinate > bus->subordinate) ||
821 (child->number > bus->subordinate) ||
822 (child->number < bus->number) ||
823 (child->subordinate < bus->number)) {
824 dev_info(&child->dev, "[bus %02x-%02x] %s "
825 "hidden behind%s bridge %s [bus %02x-%02x]\n",
826 child->number, child->subordinate,
827 (bus->number > child->subordinate &&
828 bus->subordinate < child->number) ?
829 "wholly" : "partially",
830 bus->self->transparent ? " transparent" : "",
831 dev_name(&bus->dev),
832 bus->number, bus->subordinate);
833 }
834 bus = bus->parent;
835 }
836
837 out:
838 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
839
840 return max;
841 }
842
843 /*
844 * Read interrupt line and base address registers.
845 * The architecture-dependent code can tweak these, of course.
846 */
847 static void pci_read_irq(struct pci_dev *dev)
848 {
849 unsigned char irq;
850
851 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
852 dev->pin = irq;
853 if (irq)
854 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
855 dev->irq = irq;
856 }
857
858 void set_pcie_port_type(struct pci_dev *pdev)
859 {
860 int pos;
861 u16 reg16;
862
863 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
864 if (!pos)
865 return;
866 pdev->is_pcie = 1;
867 pdev->pcie_cap = pos;
868 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
869 pdev->pcie_type = (reg16 & PCI_EXP_FLAGS_TYPE) >> 4;
870 }
871
872 void set_pcie_hotplug_bridge(struct pci_dev *pdev)
873 {
874 int pos;
875 u16 reg16;
876 u32 reg32;
877
878 pos = pci_pcie_cap(pdev);
879 if (!pos)
880 return;
881 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
882 if (!(reg16 & PCI_EXP_FLAGS_SLOT))
883 return;
884 pci_read_config_dword(pdev, pos + PCI_EXP_SLTCAP, &reg32);
885 if (reg32 & PCI_EXP_SLTCAP_HPC)
886 pdev->is_hotplug_bridge = 1;
887 }
888
889 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
890
891 /**
892 * pci_setup_device - fill in class and map information of a device
893 * @dev: the device structure to fill
894 *
895 * Initialize the device structure with information about the device's
896 * vendor,class,memory and IO-space addresses,IRQ lines etc.
897 * Called at initialisation of the PCI subsystem and by CardBus services.
898 * Returns 0 on success and negative if unknown type of device (not normal,
899 * bridge or CardBus).
900 */
901 int pci_setup_device(struct pci_dev *dev)
902 {
903 u32 class;
904 u8 hdr_type;
905 struct pci_slot *slot;
906 int pos = 0;
907
908 if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type))
909 return -EIO;
910
911 dev->sysdata = dev->bus->sysdata;
912 dev->dev.parent = dev->bus->bridge;
913 dev->dev.bus = &pci_bus_type;
914 dev->hdr_type = hdr_type & 0x7f;
915 dev->multifunction = !!(hdr_type & 0x80);
916 dev->error_state = pci_channel_io_normal;
917 set_pcie_port_type(dev);
918
919 list_for_each_entry(slot, &dev->bus->slots, list)
920 if (PCI_SLOT(dev->devfn) == slot->number)
921 dev->slot = slot;
922
923 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
924 set this higher, assuming the system even supports it. */
925 dev->dma_mask = 0xffffffff;
926
927 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
928 dev->bus->number, PCI_SLOT(dev->devfn),
929 PCI_FUNC(dev->devfn));
930
931 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
932 dev->revision = class & 0xff;
933 class >>= 8; /* upper 3 bytes */
934 dev->class = class;
935 class >>= 8;
936
937 dev_printk(KERN_DEBUG, &dev->dev, "[%04x:%04x] type %d class %#08x\n",
938 dev->vendor, dev->device, dev->hdr_type, class);
939
940 /* need to have dev->class ready */
941 dev->cfg_size = pci_cfg_space_size(dev);
942
943 /* "Unknown power state" */
944 dev->current_state = PCI_UNKNOWN;
945
946 /* Early fixups, before probing the BARs */
947 pci_fixup_device(pci_fixup_early, dev);
948 /* device class may be changed after fixup */
949 class = dev->class >> 8;
950
951 switch (dev->hdr_type) { /* header type */
952 case PCI_HEADER_TYPE_NORMAL: /* standard header */
953 if (class == PCI_CLASS_BRIDGE_PCI)
954 goto bad;
955 pci_read_irq(dev);
956 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
957 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
958 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
959
960 /*
961 * Do the ugly legacy mode stuff here rather than broken chip
962 * quirk code. Legacy mode ATA controllers have fixed
963 * addresses. These are not always echoed in BAR0-3, and
964 * BAR0-3 in a few cases contain junk!
965 */
966 if (class == PCI_CLASS_STORAGE_IDE) {
967 u8 progif;
968 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
969 if ((progif & 1) == 0) {
970 dev->resource[0].start = 0x1F0;
971 dev->resource[0].end = 0x1F7;
972 dev->resource[0].flags = LEGACY_IO_RESOURCE;
973 dev->resource[1].start = 0x3F6;
974 dev->resource[1].end = 0x3F6;
975 dev->resource[1].flags = LEGACY_IO_RESOURCE;
976 }
977 if ((progif & 4) == 0) {
978 dev->resource[2].start = 0x170;
979 dev->resource[2].end = 0x177;
980 dev->resource[2].flags = LEGACY_IO_RESOURCE;
981 dev->resource[3].start = 0x376;
982 dev->resource[3].end = 0x376;
983 dev->resource[3].flags = LEGACY_IO_RESOURCE;
984 }
985 }
986 break;
987
988 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
989 if (class != PCI_CLASS_BRIDGE_PCI)
990 goto bad;
991 /* The PCI-to-PCI bridge spec requires that subtractive
992 decoding (i.e. transparent) bridge must have programming
993 interface code of 0x01. */
994 pci_read_irq(dev);
995 dev->transparent = ((dev->class & 0xff) == 1);
996 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
997 set_pcie_hotplug_bridge(dev);
998 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID);
999 if (pos) {
1000 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor);
1001 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device);
1002 }
1003 break;
1004
1005 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
1006 if (class != PCI_CLASS_BRIDGE_CARDBUS)
1007 goto bad;
1008 pci_read_irq(dev);
1009 pci_read_bases(dev, 1, 0);
1010 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1011 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
1012 break;
1013
1014 default: /* unknown header */
1015 dev_err(&dev->dev, "unknown header type %02x, "
1016 "ignoring device\n", dev->hdr_type);
1017 return -EIO;
1018
1019 bad:
1020 dev_err(&dev->dev, "ignoring class %02x (doesn't match header "
1021 "type %02x)\n", class, dev->hdr_type);
1022 dev->class = PCI_CLASS_NOT_DEFINED;
1023 }
1024
1025 /* We found a fine healthy device, go go go... */
1026 return 0;
1027 }
1028
1029 static void pci_release_capabilities(struct pci_dev *dev)
1030 {
1031 pci_vpd_release(dev);
1032 pci_iov_release(dev);
1033 }
1034
1035 /**
1036 * pci_release_dev - free a pci device structure when all users of it are finished.
1037 * @dev: device that's been disconnected
1038 *
1039 * Will be called only by the device core when all users of this pci device are
1040 * done.
1041 */
1042 static void pci_release_dev(struct device *dev)
1043 {
1044 struct pci_dev *pci_dev;
1045
1046 pci_dev = to_pci_dev(dev);
1047 pci_release_capabilities(pci_dev);
1048 kfree(pci_dev);
1049 }
1050
1051 /**
1052 * pci_cfg_space_size - get the configuration space size of the PCI device.
1053 * @dev: PCI device
1054 *
1055 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
1056 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
1057 * access it. Maybe we don't have a way to generate extended config space
1058 * accesses, or the device is behind a reverse Express bridge. So we try
1059 * reading the dword at 0x100 which must either be 0 or a valid extended
1060 * capability header.
1061 */
1062 int pci_cfg_space_size_ext(struct pci_dev *dev)
1063 {
1064 u32 status;
1065 int pos = PCI_CFG_SPACE_SIZE;
1066
1067 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
1068 goto fail;
1069 if (status == 0xffffffff)
1070 goto fail;
1071
1072 return PCI_CFG_SPACE_EXP_SIZE;
1073
1074 fail:
1075 return PCI_CFG_SPACE_SIZE;
1076 }
1077
1078 int pci_cfg_space_size(struct pci_dev *dev)
1079 {
1080 int pos;
1081 u32 status;
1082 u16 class;
1083
1084 class = dev->class >> 8;
1085 if (class == PCI_CLASS_BRIDGE_HOST)
1086 return pci_cfg_space_size_ext(dev);
1087
1088 pos = pci_pcie_cap(dev);
1089 if (!pos) {
1090 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1091 if (!pos)
1092 goto fail;
1093
1094 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
1095 if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
1096 goto fail;
1097 }
1098
1099 return pci_cfg_space_size_ext(dev);
1100
1101 fail:
1102 return PCI_CFG_SPACE_SIZE;
1103 }
1104
1105 static void pci_release_bus_bridge_dev(struct device *dev)
1106 {
1107 kfree(dev);
1108 }
1109
1110 struct pci_dev *alloc_pci_dev(void)
1111 {
1112 struct pci_dev *dev;
1113
1114 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
1115 if (!dev)
1116 return NULL;
1117
1118 INIT_LIST_HEAD(&dev->bus_list);
1119
1120 return dev;
1121 }
1122 EXPORT_SYMBOL(alloc_pci_dev);
1123
1124 /*
1125 * Read the config data for a PCI device, sanity-check it
1126 * and fill in the dev structure...
1127 */
1128 static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
1129 {
1130 struct pci_dev *dev;
1131 u32 l;
1132 int delay = 1;
1133
1134 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
1135 return NULL;
1136
1137 /* some broken boards return 0 or ~0 if a slot is empty: */
1138 if (l == 0xffffffff || l == 0x00000000 ||
1139 l == 0x0000ffff || l == 0xffff0000)
1140 return NULL;
1141
1142 /* Configuration request Retry Status */
1143 while (l == 0xffff0001) {
1144 msleep(delay);
1145 delay *= 2;
1146 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
1147 return NULL;
1148 /* Card hasn't responded in 60 seconds? Must be stuck. */
1149 if (delay > 60 * 1000) {
1150 printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not "
1151 "responding\n", pci_domain_nr(bus),
1152 bus->number, PCI_SLOT(devfn),
1153 PCI_FUNC(devfn));
1154 return NULL;
1155 }
1156 }
1157
1158 dev = alloc_pci_dev();
1159 if (!dev)
1160 return NULL;
1161
1162 dev->bus = bus;
1163 dev->devfn = devfn;
1164 dev->vendor = l & 0xffff;
1165 dev->device = (l >> 16) & 0xffff;
1166
1167 if (pci_setup_device(dev)) {
1168 kfree(dev);
1169 return NULL;
1170 }
1171
1172 return dev;
1173 }
1174
1175 static void pci_init_capabilities(struct pci_dev *dev)
1176 {
1177 /* MSI/MSI-X list */
1178 pci_msi_init_pci_dev(dev);
1179
1180 /* Buffers for saving PCIe and PCI-X capabilities */
1181 pci_allocate_cap_save_buffers(dev);
1182
1183 /* Power Management */
1184 pci_pm_init(dev);
1185 platform_pci_wakeup_init(dev);
1186
1187 /* Vital Product Data */
1188 pci_vpd_pci22_init(dev);
1189
1190 /* Alternative Routing-ID Forwarding */
1191 pci_enable_ari(dev);
1192
1193 /* Single Root I/O Virtualization */
1194 pci_iov_init(dev);
1195
1196 /* Enable ACS P2P upstream forwarding */
1197 pci_enable_acs(dev);
1198 }
1199
1200 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
1201 {
1202 device_initialize(&dev->dev);
1203 dev->dev.release = pci_release_dev;
1204 pci_dev_get(dev);
1205
1206 dev->dev.dma_mask = &dev->dma_mask;
1207 dev->dev.dma_parms = &dev->dma_parms;
1208 dev->dev.coherent_dma_mask = 0xffffffffull;
1209
1210 pci_set_dma_max_seg_size(dev, 65536);
1211 pci_set_dma_seg_boundary(dev, 0xffffffff);
1212
1213 /* Fix up broken headers */
1214 pci_fixup_device(pci_fixup_header, dev);
1215
1216 /* Clear the state_saved flag. */
1217 dev->state_saved = false;
1218
1219 /* Initialize various capabilities */
1220 pci_init_capabilities(dev);
1221
1222 /*
1223 * Add the device to our list of discovered devices
1224 * and the bus list for fixup functions, etc.
1225 */
1226 down_write(&pci_bus_sem);
1227 list_add_tail(&dev->bus_list, &bus->devices);
1228 up_write(&pci_bus_sem);
1229 }
1230
1231 struct pci_dev *__ref pci_scan_single_device(struct pci_bus *bus, int devfn)
1232 {
1233 struct pci_dev *dev;
1234
1235 dev = pci_get_slot(bus, devfn);
1236 if (dev) {
1237 pci_dev_put(dev);
1238 return dev;
1239 }
1240
1241 dev = pci_scan_device(bus, devfn);
1242 if (!dev)
1243 return NULL;
1244
1245 pci_device_add(dev, bus);
1246
1247 return dev;
1248 }
1249 EXPORT_SYMBOL(pci_scan_single_device);
1250
1251 static unsigned next_ari_fn(struct pci_dev *dev, unsigned fn)
1252 {
1253 u16 cap;
1254 unsigned pos, next_fn;
1255
1256 if (!dev)
1257 return 0;
1258
1259 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
1260 if (!pos)
1261 return 0;
1262 pci_read_config_word(dev, pos + 4, &cap);
1263 next_fn = cap >> 8;
1264 if (next_fn <= fn)
1265 return 0;
1266 return next_fn;
1267 }
1268
1269 static unsigned next_trad_fn(struct pci_dev *dev, unsigned fn)
1270 {
1271 return (fn + 1) % 8;
1272 }
1273
1274 static unsigned no_next_fn(struct pci_dev *dev, unsigned fn)
1275 {
1276 return 0;
1277 }
1278
1279 static int only_one_child(struct pci_bus *bus)
1280 {
1281 struct pci_dev *parent = bus->self;
1282 if (!parent || !pci_is_pcie(parent))
1283 return 0;
1284 if (parent->pcie_type == PCI_EXP_TYPE_ROOT_PORT ||
1285 parent->pcie_type == PCI_EXP_TYPE_DOWNSTREAM)
1286 return 1;
1287 return 0;
1288 }
1289
1290 /**
1291 * pci_scan_slot - scan a PCI slot on a bus for devices.
1292 * @bus: PCI bus to scan
1293 * @devfn: slot number to scan (must have zero function.)
1294 *
1295 * Scan a PCI slot on the specified PCI bus for devices, adding
1296 * discovered devices to the @bus->devices list. New devices
1297 * will not have is_added set.
1298 *
1299 * Returns the number of new devices found.
1300 */
1301 int pci_scan_slot(struct pci_bus *bus, int devfn)
1302 {
1303 unsigned fn, nr = 0;
1304 struct pci_dev *dev;
1305 unsigned (*next_fn)(struct pci_dev *, unsigned) = no_next_fn;
1306
1307 if (only_one_child(bus) && (devfn > 0))
1308 return 0; /* Already scanned the entire slot */
1309
1310 dev = pci_scan_single_device(bus, devfn);
1311 if (!dev)
1312 return 0;
1313 if (!dev->is_added)
1314 nr++;
1315
1316 if (pci_ari_enabled(bus))
1317 next_fn = next_ari_fn;
1318 else if (dev->multifunction)
1319 next_fn = next_trad_fn;
1320
1321 for (fn = next_fn(dev, 0); fn > 0; fn = next_fn(dev, fn)) {
1322 dev = pci_scan_single_device(bus, devfn + fn);
1323 if (dev) {
1324 if (!dev->is_added)
1325 nr++;
1326 dev->multifunction = 1;
1327 }
1328 }
1329
1330 /* only one slot has pcie device */
1331 if (bus->self && nr)
1332 pcie_aspm_init_link_state(bus->self);
1333
1334 return nr;
1335 }
1336
1337 unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus)
1338 {
1339 unsigned int devfn, pass, max = bus->secondary;
1340 struct pci_dev *dev;
1341
1342 dev_dbg(&bus->dev, "scanning bus\n");
1343
1344 /* Go find them, Rover! */
1345 for (devfn = 0; devfn < 0x100; devfn += 8)
1346 pci_scan_slot(bus, devfn);
1347
1348 /* Reserve buses for SR-IOV capability. */
1349 max += pci_iov_bus_range(bus);
1350
1351 /*
1352 * After performing arch-dependent fixup of the bus, look behind
1353 * all PCI-to-PCI bridges on this bus.
1354 */
1355 if (!bus->is_added) {
1356 dev_dbg(&bus->dev, "fixups for bus\n");
1357 pcibios_fixup_bus(bus);
1358 if (pci_is_root_bus(bus))
1359 bus->is_added = 1;
1360 }
1361
1362 for (pass=0; pass < 2; pass++)
1363 list_for_each_entry(dev, &bus->devices, bus_list) {
1364 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
1365 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
1366 max = pci_scan_bridge(bus, dev, max, pass);
1367 }
1368
1369 /*
1370 * We've scanned the bus and so we know all about what's on
1371 * the other side of any bridges that may be on this bus plus
1372 * any devices.
1373 *
1374 * Return how far we've got finding sub-buses.
1375 */
1376 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max);
1377 return max;
1378 }
1379
1380 struct pci_bus * pci_create_bus(struct device *parent,
1381 int bus, struct pci_ops *ops, void *sysdata)
1382 {
1383 int error;
1384 struct pci_bus *b, *b2;
1385 struct device *dev;
1386
1387 b = pci_alloc_bus();
1388 if (!b)
1389 return NULL;
1390
1391 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1392 if (!dev){
1393 kfree(b);
1394 return NULL;
1395 }
1396
1397 b->sysdata = sysdata;
1398 b->ops = ops;
1399
1400 b2 = pci_find_bus(pci_domain_nr(b), bus);
1401 if (b2) {
1402 /* If we already got to this bus through a different bridge, ignore it */
1403 dev_dbg(&b2->dev, "bus already known\n");
1404 goto err_out;
1405 }
1406
1407 down_write(&pci_bus_sem);
1408 list_add_tail(&b->node, &pci_root_buses);
1409 up_write(&pci_bus_sem);
1410
1411 dev->parent = parent;
1412 dev->release = pci_release_bus_bridge_dev;
1413 dev_set_name(dev, "pci%04x:%02x", pci_domain_nr(b), bus);
1414 error = device_register(dev);
1415 if (error)
1416 goto dev_reg_err;
1417 b->bridge = get_device(dev);
1418 device_enable_async_suspend(b->bridge);
1419
1420 if (!parent)
1421 set_dev_node(b->bridge, pcibus_to_node(b));
1422
1423 b->dev.class = &pcibus_class;
1424 b->dev.parent = b->bridge;
1425 dev_set_name(&b->dev, "%04x:%02x", pci_domain_nr(b), bus);
1426 error = device_register(&b->dev);
1427 if (error)
1428 goto class_dev_reg_err;
1429
1430 /* Create legacy_io and legacy_mem files for this bus */
1431 pci_create_legacy_files(b);
1432
1433 b->number = b->secondary = bus;
1434 b->resource[0] = &ioport_resource;
1435 b->resource[1] = &iomem_resource;
1436
1437 return b;
1438
1439 class_dev_reg_err:
1440 device_unregister(dev);
1441 dev_reg_err:
1442 down_write(&pci_bus_sem);
1443 list_del(&b->node);
1444 up_write(&pci_bus_sem);
1445 err_out:
1446 kfree(dev);
1447 kfree(b);
1448 return NULL;
1449 }
1450
1451 struct pci_bus * __devinit pci_scan_bus_parented(struct device *parent,
1452 int bus, struct pci_ops *ops, void *sysdata)
1453 {
1454 struct pci_bus *b;
1455
1456 b = pci_create_bus(parent, bus, ops, sysdata);
1457 if (b)
1458 b->subordinate = pci_scan_child_bus(b);
1459 return b;
1460 }
1461 EXPORT_SYMBOL(pci_scan_bus_parented);
1462
1463 #ifdef CONFIG_HOTPLUG
1464 /**
1465 * pci_rescan_bus - scan a PCI bus for devices.
1466 * @bus: PCI bus to scan
1467 *
1468 * Scan a PCI bus and child buses for new devices, adds them,
1469 * and enables them.
1470 *
1471 * Returns the max number of subordinate bus discovered.
1472 */
1473 unsigned int __ref pci_rescan_bus(struct pci_bus *bus)
1474 {
1475 unsigned int max;
1476 struct pci_dev *dev;
1477
1478 max = pci_scan_child_bus(bus);
1479
1480 down_read(&pci_bus_sem);
1481 list_for_each_entry(dev, &bus->devices, bus_list)
1482 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
1483 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
1484 if (dev->subordinate)
1485 pci_bus_size_bridges(dev->subordinate);
1486 up_read(&pci_bus_sem);
1487
1488 pci_bus_assign_resources(bus);
1489 pci_enable_bridges(bus);
1490 pci_bus_add_devices(bus);
1491
1492 return max;
1493 }
1494 EXPORT_SYMBOL_GPL(pci_rescan_bus);
1495
1496 EXPORT_SYMBOL(pci_add_new_bus);
1497 EXPORT_SYMBOL(pci_scan_slot);
1498 EXPORT_SYMBOL(pci_scan_bridge);
1499 EXPORT_SYMBOL_GPL(pci_scan_child_bus);
1500 #endif
1501
1502 static int __init pci_sort_bf_cmp(const struct device *d_a, const struct device *d_b)
1503 {
1504 const struct pci_dev *a = to_pci_dev(d_a);
1505 const struct pci_dev *b = to_pci_dev(d_b);
1506
1507 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
1508 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
1509
1510 if (a->bus->number < b->bus->number) return -1;
1511 else if (a->bus->number > b->bus->number) return 1;
1512
1513 if (a->devfn < b->devfn) return -1;
1514 else if (a->devfn > b->devfn) return 1;
1515
1516 return 0;
1517 }
1518
1519 void __init pci_sort_breadthfirst(void)
1520 {
1521 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp);
1522 }
Linux with added FPC-III support