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Merge branch 'fix/pcm-hwptr' into for-linus
[linux/fpc-iii.git] / drivers / media / dvb / frontends / stv0900_sw.c
bloba5a31536cbcb113fbcd5690b24c98395cb4a69d0
1 /*
2 * stv0900_sw.c
3 *
4 * Driver for ST STV0900 satellite demodulator IC.
5 *
6 * Copyright (C) ST Microelectronics.
7 * Copyright (C) 2009 NetUP Inc.
8 * Copyright (C) 2009 Igor M. Liplianin <liplianin@netup.ru>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 *
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
26 #include "stv0900.h"
27 #include "stv0900_reg.h"
28 #include "stv0900_priv.h"
29
30 int stv0900_check_signal_presence(struct stv0900_internal *i_params,
31 enum fe_stv0900_demod_num demod)
32 {
33 s32 carr_offset,
34 agc2_integr,
35 max_carrier;
36
37 int no_signal;
38
39 switch (demod) {
40 case STV0900_DEMOD_1:
41 default:
42 carr_offset = (stv0900_read_reg(i_params, R0900_P1_CFR2) << 8)
43 | stv0900_read_reg(i_params,
44 R0900_P1_CFR1);
45 carr_offset = ge2comp(carr_offset, 16);
46 agc2_integr = (stv0900_read_reg(i_params, R0900_P1_AGC2I1) << 8)
47 | stv0900_read_reg(i_params,
48 R0900_P1_AGC2I0);
49 max_carrier = i_params->dmd1_srch_range / 1000;
50 break;
51 case STV0900_DEMOD_2:
52 carr_offset = (stv0900_read_reg(i_params, R0900_P2_CFR2) << 8)
53 | stv0900_read_reg(i_params,
54 R0900_P2_CFR1);
55 carr_offset = ge2comp(carr_offset, 16);
56 agc2_integr = (stv0900_read_reg(i_params, R0900_P2_AGC2I1) << 8)
57 | stv0900_read_reg(i_params,
58 R0900_P2_AGC2I0);
59 max_carrier = i_params->dmd2_srch_range / 1000;
60 break;
61 }
62
63 max_carrier += (max_carrier / 10);
64 max_carrier = 65536 * (max_carrier / 2);
65 max_carrier /= i_params->mclk / 1000;
66 if (max_carrier > 0x4000)
67 max_carrier = 0x4000;
68
69 if ((agc2_integr > 0x2000)
70 || (carr_offset > + 2*max_carrier)
71 || (carr_offset < -2*max_carrier))
72 no_signal = TRUE;
73 else
74 no_signal = FALSE;
75
76 return no_signal;
77 }
78
79 static void stv0900_get_sw_loop_params(struct stv0900_internal *i_params,
80 s32 *frequency_inc, s32 *sw_timeout,
81 s32 *steps,
82 enum fe_stv0900_demod_num demod)
83 {
84 s32 timeout, freq_inc, max_steps, srate, max_carrier;
85
86 enum fe_stv0900_search_standard standard;
87
88 switch (demod) {
89 case STV0900_DEMOD_1:
90 default:
91 srate = i_params->dmd1_symbol_rate;
92 max_carrier = i_params->dmd1_srch_range / 1000;
93 max_carrier += max_carrier / 10;
94 standard = i_params->dmd1_srch_standard;
95 break;
96 case STV0900_DEMOD_2:
97 srate = i_params->dmd2_symbol_rate;
98 max_carrier = i_params->dmd2_srch_range / 1000;
99 max_carrier += max_carrier / 10;
100 standard = i_params->dmd2_srch_stndrd;
101 break;
102 }
103
104 max_carrier = 65536 * (max_carrier / 2);
105 max_carrier /= i_params->mclk / 1000;
106
107 if (max_carrier > 0x4000)
108 max_carrier = 0x4000;
109
110 freq_inc = srate;
111 freq_inc /= i_params->mclk >> 10;
112 freq_inc = freq_inc << 6;
113
114 switch (standard) {
115 case STV0900_SEARCH_DVBS1:
116 case STV0900_SEARCH_DSS:
117 freq_inc *= 3;
118 timeout = 20;
119 break;
120 case STV0900_SEARCH_DVBS2:
121 freq_inc *= 4;
122 timeout = 25;
123 break;
124 case STV0900_AUTO_SEARCH:
125 default:
126 freq_inc *= 3;
127 timeout = 25;
128 break;
129 }
130
131 freq_inc /= 100;
132
133 if ((freq_inc > max_carrier) || (freq_inc < 0))
134 freq_inc = max_carrier / 2;
135
136 timeout *= 27500;
137
138 if (srate > 0)
139 timeout /= srate / 1000;
140
141 if ((timeout > 100) || (timeout < 0))
142 timeout = 100;
143
144 max_steps = (max_carrier / freq_inc) + 1;
145
146 if ((max_steps > 100) || (max_steps < 0)) {
147 max_steps = 100;
148 freq_inc = max_carrier / max_steps;
149 }
150
151 *frequency_inc = freq_inc;
152 *sw_timeout = timeout;
153 *steps = max_steps;
154
155 }
156
157 static int stv0900_search_carr_sw_loop(struct stv0900_internal *i_params,
158 s32 FreqIncr, s32 Timeout, int zigzag,
159 s32 MaxStep, enum fe_stv0900_demod_num demod)
160 {
161 int no_signal,
162 lock = FALSE;
163 s32 stepCpt,
164 freqOffset,
165 max_carrier;
166
167 switch (demod) {
168 case STV0900_DEMOD_1:
169 default:
170 max_carrier = i_params->dmd1_srch_range / 1000;
171 max_carrier += (max_carrier / 10);
172 break;
173 case STV0900_DEMOD_2:
174 max_carrier = i_params->dmd2_srch_range / 1000;
175 max_carrier += (max_carrier / 10);
176 break;
177 }
178
179 max_carrier = 65536 * (max_carrier / 2);
180 max_carrier /= i_params->mclk / 1000;
181
182 if (max_carrier > 0x4000)
183 max_carrier = 0x4000;
184
185 if (zigzag == TRUE)
186 freqOffset = 0;
187 else
188 freqOffset = -max_carrier + FreqIncr;
189
190 stepCpt = 0;
191
192 do {
193 switch (demod) {
194 case STV0900_DEMOD_1:
195 default:
196 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x1C);
197 stv0900_write_reg(i_params, R0900_P1_CFRINIT1,
198 (freqOffset / 256) & 0xFF);
199 stv0900_write_reg(i_params, R0900_P1_CFRINIT0,
200 freqOffset & 0xFF);
201 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x18);
202 stv0900_write_bits(i_params, F0900_P1_ALGOSWRST, 1);
203
204 if (i_params->chip_id == 0x12) {
205 stv0900_write_bits(i_params,
206 F0900_P1_RST_HWARE, 1);
207 stv0900_write_bits(i_params,
208 F0900_P1_RST_HWARE, 0);
209 }
210 break;
211 case STV0900_DEMOD_2:
212 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x1C);
213 stv0900_write_reg(i_params, R0900_P2_CFRINIT1,
214 (freqOffset / 256) & 0xFF);
215 stv0900_write_reg(i_params, R0900_P2_CFRINIT0,
216 freqOffset & 0xFF);
217 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x18);
218 stv0900_write_bits(i_params, F0900_P2_ALGOSWRST, 1);
219
220 if (i_params->chip_id == 0x12) {
221 stv0900_write_bits(i_params,
222 F0900_P2_RST_HWARE, 1);
223 stv0900_write_bits(i_params,
224 F0900_P2_RST_HWARE, 0);
225 }
226 break;
227 }
228
229 if (zigzag == TRUE) {
230 if (freqOffset >= 0)
231 freqOffset = -freqOffset - 2 * FreqIncr;
232 else
233 freqOffset = -freqOffset;
234 } else
235 freqOffset += + 2 * FreqIncr;
236
237 stepCpt++;
238 lock = stv0900_get_demod_lock(i_params, demod, Timeout);
239 no_signal = stv0900_check_signal_presence(i_params, demod);
240
241 } while ((lock == FALSE)
242 && (no_signal == FALSE)
243 && ((freqOffset - FreqIncr) < max_carrier)
244 && ((freqOffset + FreqIncr) > -max_carrier)
245 && (stepCpt < MaxStep));
246
247 switch (demod) {
248 case STV0900_DEMOD_1:
249 default:
250 stv0900_write_bits(i_params, F0900_P1_ALGOSWRST, 0);
251 break;
252 case STV0900_DEMOD_2:
253 stv0900_write_bits(i_params, F0900_P2_ALGOSWRST, 0);
254 break;
255 }
256
257 return lock;
258 }
259
260 int stv0900_sw_algo(struct stv0900_internal *i_params,
261 enum fe_stv0900_demod_num demod)
262 {
263 int lock = FALSE;
264
265 int no_signal,
266 zigzag;
267 s32 dvbs2_fly_wheel;
268
269 s32 freqIncrement, softStepTimeout, trialCounter, max_steps;
270
271 stv0900_get_sw_loop_params(i_params, &freqIncrement, &softStepTimeout,
272 &max_steps, demod);
273 switch (demod) {
274 case STV0900_DEMOD_1:
275 default:
276 switch (i_params->dmd1_srch_standard) {
277 case STV0900_SEARCH_DVBS1:
278 case STV0900_SEARCH_DSS:
279 if (i_params->chip_id >= 0x20)
280 stv0900_write_reg(i_params, R0900_P1_CARFREQ,
281 0x3B);
282 else
283 stv0900_write_reg(i_params, R0900_P1_CARFREQ,
284 0xef);
285
286 stv0900_write_reg(i_params, R0900_P1_DMDCFGMD, 0x49);
287 zigzag = FALSE;
288 break;
289 case STV0900_SEARCH_DVBS2:
290 if (i_params->chip_id >= 0x20)
291 stv0900_write_reg(i_params, R0900_P1_CORRELABS,
292 0x79);
293 else
294 stv0900_write_reg(i_params, R0900_P1_CORRELABS,
295 0x68);
296
297 stv0900_write_reg(i_params, R0900_P1_DMDCFGMD,
298 0x89);
299
300 zigzag = TRUE;
301 break;
302 case STV0900_AUTO_SEARCH:
303 default:
304 if (i_params->chip_id >= 0x20) {
305 stv0900_write_reg(i_params, R0900_P1_CARFREQ,
306 0x3B);
307 stv0900_write_reg(i_params, R0900_P1_CORRELABS,
308 0x79);
309 } else {
310 stv0900_write_reg(i_params, R0900_P1_CARFREQ,
311 0xef);
312 stv0900_write_reg(i_params, R0900_P1_CORRELABS,
313 0x68);
314 }
315
316 stv0900_write_reg(i_params, R0900_P1_DMDCFGMD,
317 0xc9);
318 zigzag = FALSE;
319 break;
320 }
321
322 trialCounter = 0;
323 do {
324 lock = stv0900_search_carr_sw_loop(i_params,
325 freqIncrement,
326 softStepTimeout,
327 zigzag,
328 max_steps,
329 demod);
330 no_signal = stv0900_check_signal_presence(i_params,
331 demod);
332 trialCounter++;
333 if ((lock == TRUE)
334 || (no_signal == TRUE)
335 || (trialCounter == 2)) {
336
337 if (i_params->chip_id >= 0x20) {
338 stv0900_write_reg(i_params,
339 R0900_P1_CARFREQ,
340 0x49);
341 stv0900_write_reg(i_params,
342 R0900_P1_CORRELABS,
343 0x9e);
344 } else {
345 stv0900_write_reg(i_params,
346 R0900_P1_CARFREQ,
347 0xed);
348 stv0900_write_reg(i_params,
349 R0900_P1_CORRELABS,
350 0x88);
351 }
352
353 if ((lock == TRUE) && (stv0900_get_bits(i_params, F0900_P1_HEADER_MODE) == STV0900_DVBS2_FOUND)) {
354 msleep(softStepTimeout);
355 dvbs2_fly_wheel = stv0900_get_bits(i_params, F0900_P1_FLYWHEEL_CPT);
356
357 if (dvbs2_fly_wheel < 0xd) {
358 msleep(softStepTimeout);
359 dvbs2_fly_wheel = stv0900_get_bits(i_params, F0900_P1_FLYWHEEL_CPT);
360 }
361
362 if (dvbs2_fly_wheel < 0xd) {
363 lock = FALSE;
364
365 if (trialCounter < 2) {
366 if (i_params->chip_id >= 0x20)
367 stv0900_write_reg(i_params, R0900_P1_CORRELABS, 0x79);
368 else
369 stv0900_write_reg(i_params, R0900_P1_CORRELABS, 0x68);
370
371 stv0900_write_reg(i_params, R0900_P1_DMDCFGMD, 0x89);
372 }
373 }
374 }
375 }
376
377 } while ((lock == FALSE)
378 && (trialCounter < 2)
379 && (no_signal == FALSE));
380
381 break;
382 case STV0900_DEMOD_2:
383 switch (i_params->dmd2_srch_stndrd) {
384 case STV0900_SEARCH_DVBS1:
385 case STV0900_SEARCH_DSS:
386 if (i_params->chip_id >= 0x20)
387 stv0900_write_reg(i_params, R0900_P2_CARFREQ,
388 0x3b);
389 else
390 stv0900_write_reg(i_params, R0900_P2_CARFREQ,
391 0xef);
392
393 stv0900_write_reg(i_params, R0900_P2_DMDCFGMD,
394 0x49);
395 zigzag = FALSE;
396 break;
397 case STV0900_SEARCH_DVBS2:
398 if (i_params->chip_id >= 0x20)
399 stv0900_write_reg(i_params, R0900_P2_CORRELABS,
400 0x79);
401 else
402 stv0900_write_reg(i_params, R0900_P2_CORRELABS,
403 0x68);
404
405 stv0900_write_reg(i_params, R0900_P2_DMDCFGMD, 0x89);
406 zigzag = TRUE;
407 break;
408 case STV0900_AUTO_SEARCH:
409 default:
410 if (i_params->chip_id >= 0x20) {
411 stv0900_write_reg(i_params, R0900_P2_CARFREQ,
412 0x3b);
413 stv0900_write_reg(i_params, R0900_P2_CORRELABS,
414 0x79);
415 } else {
416 stv0900_write_reg(i_params, R0900_P2_CARFREQ,
417 0xef);
418 stv0900_write_reg(i_params, R0900_P2_CORRELABS,
419 0x68);
420 }
421
422 stv0900_write_reg(i_params, R0900_P2_DMDCFGMD, 0xc9);
423
424 zigzag = FALSE;
425 break;
426 }
427
428 trialCounter = 0;
429
430 do {
431 lock = stv0900_search_carr_sw_loop(i_params,
432 freqIncrement,
433 softStepTimeout,
434 zigzag,
435 max_steps,
436 demod);
437 no_signal = stv0900_check_signal_presence(i_params,
438 demod);
439 trialCounter++;
440 if ((lock == TRUE)
441 || (no_signal == TRUE)
442 || (trialCounter == 2)) {
443 if (i_params->chip_id >= 0x20) {
444 stv0900_write_reg(i_params,
445 R0900_P2_CARFREQ,
446 0x49);
447 stv0900_write_reg(i_params,
448 R0900_P2_CORRELABS,
449 0x9e);
450 } else {
451 stv0900_write_reg(i_params,
452 R0900_P2_CARFREQ,
453 0xed);
454 stv0900_write_reg(i_params,
455 R0900_P2_CORRELABS,
456 0x88);
457 }
458
459 if ((lock == TRUE) && (stv0900_get_bits(i_params, F0900_P2_HEADER_MODE) == STV0900_DVBS2_FOUND)) {
460 msleep(softStepTimeout);
461 dvbs2_fly_wheel = stv0900_get_bits(i_params, F0900_P2_FLYWHEEL_CPT);
462 if (dvbs2_fly_wheel < 0xd) {
463 msleep(softStepTimeout);
464 dvbs2_fly_wheel = stv0900_get_bits(i_params, F0900_P2_FLYWHEEL_CPT);
465 }
466
467 if (dvbs2_fly_wheel < 0xd) {
468 lock = FALSE;
469 if (trialCounter < 2) {
470 if (i_params->chip_id >= 0x20)
471 stv0900_write_reg(i_params, R0900_P2_CORRELABS, 0x79);
472 else
473 stv0900_write_reg(i_params, R0900_P2_CORRELABS, 0x68);
474
475 stv0900_write_reg(i_params, R0900_P2_DMDCFGMD, 0x89);
476 }
477 }
478 }
479 }
480
481 } while ((lock == FALSE) && (trialCounter < 2) && (no_signal == FALSE));
482
483 break;
484 }
485
486 return lock;
487 }
488
489 static u32 stv0900_get_symbol_rate(struct stv0900_internal *i_params,
490 u32 mclk,
491 enum fe_stv0900_demod_num demod)
492 {
493 s32 sfr_field3, sfr_field2, sfr_field1, sfr_field0,
494 rem1, rem2, intval1, intval2, srate;
495
496 dmd_reg(sfr_field3, F0900_P1_SYMB_FREQ3, F0900_P2_SYMB_FREQ3);
497 dmd_reg(sfr_field2, F0900_P1_SYMB_FREQ2, F0900_P2_SYMB_FREQ2);
498 dmd_reg(sfr_field1, F0900_P1_SYMB_FREQ1, F0900_P2_SYMB_FREQ1);
499 dmd_reg(sfr_field0, F0900_P1_SYMB_FREQ0, F0900_P2_SYMB_FREQ0);
500
501 srate = (stv0900_get_bits(i_params, sfr_field3) << 24) +
502 (stv0900_get_bits(i_params, sfr_field2) << 16) +
503 (stv0900_get_bits(i_params, sfr_field1) << 8) +
504 (stv0900_get_bits(i_params, sfr_field0));
505 dprintk("lock: srate=%d r0=0x%x r1=0x%x r2=0x%x r3=0x%x \n",
506 srate, stv0900_get_bits(i_params, sfr_field0),
507 stv0900_get_bits(i_params, sfr_field1),
508 stv0900_get_bits(i_params, sfr_field2),
509 stv0900_get_bits(i_params, sfr_field3));
510
511 intval1 = (mclk) >> 16;
512 intval2 = (srate) >> 16;
513
514 rem1 = (mclk) % 0x10000;
515 rem2 = (srate) % 0x10000;
516 srate = (intval1 * intval2) +
517 ((intval1 * rem2) >> 16) +
518 ((intval2 * rem1) >> 16);
519
520 return srate;
521 }
522
523 static void stv0900_set_symbol_rate(struct stv0900_internal *i_params,
524 u32 mclk, u32 srate,
525 enum fe_stv0900_demod_num demod)
526 {
527 s32 sfr_init_reg;
528 u32 symb;
529
530 dprintk(KERN_INFO "%s: Mclk %d, SR %d, Dmd %d\n", __func__, mclk,
531 srate, demod);
532
533 dmd_reg(sfr_init_reg, R0900_P1_SFRINIT1, R0900_P2_SFRINIT1);
534
535 if (srate > 60000000) {
536 symb = srate << 4;
537 symb /= (mclk >> 12);
538 } else if (srate > 6000000) {
539 symb = srate << 6;
540 symb /= (mclk >> 10);
541 } else {
542 symb = srate << 9;
543 symb /= (mclk >> 7);
544 }
545
546 stv0900_write_reg(i_params, sfr_init_reg, (symb >> 8) & 0x7F);
547 stv0900_write_reg(i_params, sfr_init_reg + 1, (symb & 0xFF));
548 }
549
550 static void stv0900_set_max_symbol_rate(struct stv0900_internal *i_params,
551 u32 mclk, u32 srate,
552 enum fe_stv0900_demod_num demod)
553 {
554 s32 sfr_max_reg;
555 u32 symb;
556
557 dmd_reg(sfr_max_reg, R0900_P1_SFRUP1, R0900_P2_SFRUP1);
558
559 srate = 105 * (srate / 100);
560
561 if (srate > 60000000) {
562 symb = srate << 4;
563 symb /= (mclk >> 12);
564 } else if (srate > 6000000) {
565 symb = srate << 6;
566 symb /= (mclk >> 10);
567 } else {
568 symb = srate << 9;
569 symb /= (mclk >> 7);
570 }
571
572 if (symb < 0x7fff) {
573 stv0900_write_reg(i_params, sfr_max_reg, (symb >> 8) & 0x7F);
574 stv0900_write_reg(i_params, sfr_max_reg + 1, (symb & 0xFF));
575 } else {
576 stv0900_write_reg(i_params, sfr_max_reg, 0x7F);
577 stv0900_write_reg(i_params, sfr_max_reg + 1, 0xFF);
578 }
579 }
580
581 static void stv0900_set_min_symbol_rate(struct stv0900_internal *i_params,
582 u32 mclk, u32 srate,
583 enum fe_stv0900_demod_num demod)
584 {
585 s32 sfr_min_reg;
586 u32 symb;
587
588 dmd_reg(sfr_min_reg, R0900_P1_SFRLOW1, R0900_P2_SFRLOW1);
589
590 srate = 95 * (srate / 100);
591 if (srate > 60000000) {
592 symb = srate << 4;
593 symb /= (mclk >> 12);
594
595 } else if (srate > 6000000) {
596 symb = srate << 6;
597 symb /= (mclk >> 10);
598
599 } else {
600 symb = srate << 9;
601 symb /= (mclk >> 7);
602 }
603
604 stv0900_write_reg(i_params, sfr_min_reg, (symb >> 8) & 0xFF);
605 stv0900_write_reg(i_params, sfr_min_reg + 1, (symb & 0xFF));
606 }
607
608 static s32 stv0900_get_timing_offst(struct stv0900_internal *i_params,
609 u32 srate,
610 enum fe_stv0900_demod_num demod)
611 {
612 s32 tmgreg,
613 timingoffset;
614
615 dmd_reg(tmgreg, R0900_P1_TMGREG2, R0900_P2_TMGREG2);
616
617 timingoffset = (stv0900_read_reg(i_params, tmgreg) << 16) +
618 (stv0900_read_reg(i_params, tmgreg + 1) << 8) +
619 (stv0900_read_reg(i_params, tmgreg + 2));
620
621 timingoffset = ge2comp(timingoffset, 24);
622
623
624 if (timingoffset == 0)
625 timingoffset = 1;
626
627 timingoffset = ((s32)srate * 10) / ((s32)0x1000000 / timingoffset);
628 timingoffset /= 320;
629
630 return timingoffset;
631 }
632
633 static void stv0900_set_dvbs2_rolloff(struct stv0900_internal *i_params,
634 enum fe_stv0900_demod_num demod)
635 {
636 s32 rolloff, man_fld, matstr_reg, rolloff_ctl_fld;
637
638 dmd_reg(man_fld, F0900_P1_MANUAL_ROLLOFF, F0900_P2_MANUAL_ROLLOFF);
639 dmd_reg(matstr_reg, R0900_P1_MATSTR1, R0900_P2_MATSTR1);
640 dmd_reg(rolloff_ctl_fld, F0900_P1_ROLLOFF_CONTROL,
641 F0900_P2_ROLLOFF_CONTROL);
642
643 if (i_params->chip_id == 0x10) {
644 stv0900_write_bits(i_params, man_fld, 1);
645 rolloff = stv0900_read_reg(i_params, matstr_reg) & 0x03;
646 stv0900_write_bits(i_params, rolloff_ctl_fld, rolloff);
647 } else
648 stv0900_write_bits(i_params, man_fld, 0);
649 }
650
651 static u32 stv0900_carrier_width(u32 srate, enum fe_stv0900_rolloff ro)
652 {
653 u32 rolloff;
654
655 switch (ro) {
656 case STV0900_20:
657 rolloff = 20;
658 break;
659 case STV0900_25:
660 rolloff = 25;
661 break;
662 case STV0900_35:
663 default:
664 rolloff = 35;
665 break;
666 }
667
668 return srate + (srate * rolloff) / 100;
669 }
670
671 static int stv0900_check_timing_lock(struct stv0900_internal *i_params,
672 enum fe_stv0900_demod_num demod)
673 {
674 int timingLock = FALSE;
675 s32 i,
676 timingcpt = 0;
677 u8 carFreq,
678 tmgTHhigh,
679 tmgTHLow;
680
681 switch (demod) {
682 case STV0900_DEMOD_1:
683 default:
684 carFreq = stv0900_read_reg(i_params, R0900_P1_CARFREQ);
685 tmgTHhigh = stv0900_read_reg(i_params, R0900_P1_TMGTHRISE);
686 tmgTHLow = stv0900_read_reg(i_params, R0900_P1_TMGTHFALL);
687 stv0900_write_reg(i_params, R0900_P1_TMGTHRISE, 0x20);
688 stv0900_write_reg(i_params, R0900_P1_TMGTHFALL, 0x0);
689 stv0900_write_bits(i_params, F0900_P1_CFR_AUTOSCAN, 0);
690 stv0900_write_reg(i_params, R0900_P1_RTC, 0x80);
691 stv0900_write_reg(i_params, R0900_P1_RTCS2, 0x40);
692 stv0900_write_reg(i_params, R0900_P1_CARFREQ, 0x0);
693 stv0900_write_reg(i_params, R0900_P1_CFRINIT1, 0x0);
694 stv0900_write_reg(i_params, R0900_P1_CFRINIT0, 0x0);
695 stv0900_write_reg(i_params, R0900_P1_AGC2REF, 0x65);
696 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x18);
697 msleep(7);
698
699 for (i = 0; i < 10; i++) {
700 if (stv0900_get_bits(i_params, F0900_P1_TMGLOCK_QUALITY) >= 2)
701 timingcpt++;
702
703 msleep(1);
704 }
705
706 if (timingcpt >= 3)
707 timingLock = TRUE;
708
709 stv0900_write_reg(i_params, R0900_P1_AGC2REF, 0x38);
710 stv0900_write_reg(i_params, R0900_P1_RTC, 0x88);
711 stv0900_write_reg(i_params, R0900_P1_RTCS2, 0x68);
712 stv0900_write_reg(i_params, R0900_P1_CARFREQ, carFreq);
713 stv0900_write_reg(i_params, R0900_P1_TMGTHRISE, tmgTHhigh);
714 stv0900_write_reg(i_params, R0900_P1_TMGTHFALL, tmgTHLow);
715 break;
716 case STV0900_DEMOD_2:
717 carFreq = stv0900_read_reg(i_params, R0900_P2_CARFREQ);
718 tmgTHhigh = stv0900_read_reg(i_params, R0900_P2_TMGTHRISE);
719 tmgTHLow = stv0900_read_reg(i_params, R0900_P2_TMGTHFALL);
720 stv0900_write_reg(i_params, R0900_P2_TMGTHRISE, 0x20);
721 stv0900_write_reg(i_params, R0900_P2_TMGTHFALL, 0);
722 stv0900_write_bits(i_params, F0900_P2_CFR_AUTOSCAN, 0);
723 stv0900_write_reg(i_params, R0900_P2_RTC, 0x80);
724 stv0900_write_reg(i_params, R0900_P2_RTCS2, 0x40);
725 stv0900_write_reg(i_params, R0900_P2_CARFREQ, 0x0);
726 stv0900_write_reg(i_params, R0900_P2_CFRINIT1, 0x0);
727 stv0900_write_reg(i_params, R0900_P2_CFRINIT0, 0x0);
728 stv0900_write_reg(i_params, R0900_P2_AGC2REF, 0x65);
729 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x18);
730 msleep(5);
731 for (i = 0; i < 10; i++) {
732 if (stv0900_get_bits(i_params, F0900_P2_TMGLOCK_QUALITY) >= 2)
733 timingcpt++;
734
735 msleep(1);
736 }
737
738 if (timingcpt >= 3)
739 timingLock = TRUE;
740
741 stv0900_write_reg(i_params, R0900_P2_AGC2REF, 0x38);
742 stv0900_write_reg(i_params, R0900_P2_RTC, 0x88);
743 stv0900_write_reg(i_params, R0900_P2_RTCS2, 0x68);
744 stv0900_write_reg(i_params, R0900_P2_CARFREQ, carFreq);
745 stv0900_write_reg(i_params, R0900_P2_TMGTHRISE, tmgTHhigh);
746 stv0900_write_reg(i_params, R0900_P2_TMGTHFALL, tmgTHLow);
747 break;
748 }
749
750 return timingLock;
751 }
752
753 static int stv0900_get_demod_cold_lock(struct dvb_frontend *fe,
754 s32 demod_timeout)
755 {
756 struct stv0900_state *state = fe->demodulator_priv;
757 struct stv0900_internal *i_params = state->internal;
758 enum fe_stv0900_demod_num demod = state->demod;
759
760 int lock = FALSE;
761 s32 srate, search_range, locktimeout,
762 currier_step, nb_steps, current_step,
763 direction, tuner_freq, timeout;
764
765 switch (demod) {
766 case STV0900_DEMOD_1:
767 default:
768 srate = i_params->dmd1_symbol_rate;
769 search_range = i_params->dmd1_srch_range;
770 break;
771
772 case STV0900_DEMOD_2:
773 srate = i_params->dmd2_symbol_rate;
774 search_range = i_params->dmd2_srch_range;
775 break;
776 }
777
778 if (srate >= 10000000)
779 locktimeout = demod_timeout / 3;
780 else
781 locktimeout = demod_timeout / 2;
782
783 lock = stv0900_get_demod_lock(i_params, demod, locktimeout);
784
785 if (lock == FALSE) {
786 if (srate >= 10000000) {
787 if (stv0900_check_timing_lock(i_params, demod) == TRUE) {
788 switch (demod) {
789 case STV0900_DEMOD_1:
790 default:
791 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x1f);
792 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x15);
793 break;
794 case STV0900_DEMOD_2:
795 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x1f);
796 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x15);
797 break;
798 }
799
800 lock = stv0900_get_demod_lock(i_params, demod, demod_timeout);
801 } else
802 lock = FALSE;
803 } else {
804 if (srate <= 4000000)
805 currier_step = 1000;
806 else if (srate <= 7000000)
807 currier_step = 2000;
808 else if (srate <= 10000000)
809 currier_step = 3000;
810 else
811 currier_step = 5000;
812
813 nb_steps = ((search_range / 1000) / currier_step);
814 nb_steps /= 2;
815 nb_steps = (2 * (nb_steps + 1));
816 if (nb_steps < 0)
817 nb_steps = 2;
818 else if (nb_steps > 12)
819 nb_steps = 12;
820
821 current_step = 1;
822 direction = 1;
823 timeout = (demod_timeout / 3);
824 if (timeout > 1000)
825 timeout = 1000;
826
827 switch (demod) {
828 case STV0900_DEMOD_1:
829 default:
830 if (lock == FALSE) {
831 tuner_freq = i_params->tuner1_freq;
832 i_params->tuner1_bw = stv0900_carrier_width(i_params->dmd1_symbol_rate, i_params->rolloff) + i_params->dmd1_symbol_rate;
833
834 while ((current_step <= nb_steps) && (lock == FALSE)) {
835
836 if (direction > 0)
837 tuner_freq += (current_step * currier_step);
838 else
839 tuner_freq -= (current_step * currier_step);
840
841 stv0900_set_tuner(fe, tuner_freq, i_params->tuner1_bw);
842 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x1C);
843 if (i_params->dmd1_srch_standard == STV0900_SEARCH_DVBS2) {
844 stv0900_write_bits(i_params, F0900_P1_DVBS1_ENABLE, 0);
845 stv0900_write_bits(i_params, F0900_P1_DVBS2_ENABLE, 0);
846 stv0900_write_bits(i_params, F0900_P1_DVBS1_ENABLE, 1);
847 stv0900_write_bits(i_params, F0900_P1_DVBS2_ENABLE, 1);
848 }
849
850 stv0900_write_reg(i_params, R0900_P1_CFRINIT1, 0);
851 stv0900_write_reg(i_params, R0900_P1_CFRINIT0, 0);
852 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x1F);
853 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x15);
854 lock = stv0900_get_demod_lock(i_params, demod, timeout);
855 direction *= -1;
856 current_step++;
857 }
858 }
859 break;
860 case STV0900_DEMOD_2:
861 if (lock == FALSE) {
862 tuner_freq = i_params->tuner2_freq;
863 i_params->tuner2_bw = stv0900_carrier_width(srate, i_params->rolloff) + srate;
864
865 while ((current_step <= nb_steps) && (lock == FALSE)) {
866
867 if (direction > 0)
868 tuner_freq += (current_step * currier_step);
869 else
870 tuner_freq -= (current_step * currier_step);
871
872 stv0900_set_tuner(fe, tuner_freq, i_params->tuner2_bw);
873 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x1C);
874 if (i_params->dmd2_srch_stndrd == STV0900_SEARCH_DVBS2) {
875 stv0900_write_bits(i_params, F0900_P2_DVBS1_ENABLE, 0);
876 stv0900_write_bits(i_params, F0900_P2_DVBS2_ENABLE, 0);
877 stv0900_write_bits(i_params, F0900_P2_DVBS1_ENABLE, 1);
878 stv0900_write_bits(i_params, F0900_P2_DVBS2_ENABLE, 1);
879 }
880
881 stv0900_write_reg(i_params, R0900_P2_CFRINIT1, 0);
882 stv0900_write_reg(i_params, R0900_P2_CFRINIT0, 0);
883 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x1F);
884 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x15);
885 lock = stv0900_get_demod_lock(i_params, demod, timeout);
886 direction *= -1;
887 current_step++;
888 }
889 }
890 break;
891 }
892 }
893 }
894
895 return lock;
896 }
897
898 static void stv0900_get_lock_timeout(s32 *demod_timeout, s32 *fec_timeout,
899 s32 srate,
900 enum fe_stv0900_search_algo algo)
901 {
902 switch (algo) {
903 case STV0900_BLIND_SEARCH:
904 if (srate <= 1500000) {
905 (*demod_timeout) = 1500;
906 (*fec_timeout) = 400;
907 } else if (srate <= 5000000) {
908 (*demod_timeout) = 1000;
909 (*fec_timeout) = 300;
910 } else {
911 (*demod_timeout) = 700;
912 (*fec_timeout) = 100;
913 }
914
915 break;
916 case STV0900_COLD_START:
917 case STV0900_WARM_START:
918 default:
919 if (srate <= 1000000) {
920 (*demod_timeout) = 3000;
921 (*fec_timeout) = 1700;
922 } else if (srate <= 2000000) {
923 (*demod_timeout) = 2500;
924 (*fec_timeout) = 1100;
925 } else if (srate <= 5000000) {
926 (*demod_timeout) = 1000;
927 (*fec_timeout) = 550;
928 } else if (srate <= 10000000) {
929 (*demod_timeout) = 700;
930 (*fec_timeout) = 250;
931 } else if (srate <= 20000000) {
932 (*demod_timeout) = 400;
933 (*fec_timeout) = 130;
934 }
935
936 else {
937 (*demod_timeout) = 300;
938 (*fec_timeout) = 100;
939 }
940
941 break;
942
943 }
944
945 if (algo == STV0900_WARM_START)
946 (*demod_timeout) /= 2;
947 }
948
949 static void stv0900_set_viterbi_tracq(struct stv0900_internal *i_params,
950 enum fe_stv0900_demod_num demod)
951 {
952
953 s32 vth_reg;
954
955 dprintk(KERN_INFO "%s\n", __func__);
956
957 dmd_reg(vth_reg, R0900_P1_VTH12, R0900_P2_VTH12);
958
959 stv0900_write_reg(i_params, vth_reg++, 0xd0);
960 stv0900_write_reg(i_params, vth_reg++, 0x7d);
961 stv0900_write_reg(i_params, vth_reg++, 0x53);
962 stv0900_write_reg(i_params, vth_reg++, 0x2F);
963 stv0900_write_reg(i_params, vth_reg++, 0x24);
964 stv0900_write_reg(i_params, vth_reg++, 0x1F);
965 }
966
967 static void stv0900_set_viterbi_standard(struct stv0900_internal *i_params,
968 enum fe_stv0900_search_standard Standard,
969 enum fe_stv0900_fec PunctureRate,
970 enum fe_stv0900_demod_num demod)
971 {
972
973 s32 fecmReg,
974 prvitReg;
975
976 dprintk(KERN_INFO "%s: ViterbiStandard = ", __func__);
977
978 switch (demod) {
979 case STV0900_DEMOD_1:
980 default:
981 fecmReg = R0900_P1_FECM;
982 prvitReg = R0900_P1_PRVIT;
983 break;
984 case STV0900_DEMOD_2:
985 fecmReg = R0900_P2_FECM;
986 prvitReg = R0900_P2_PRVIT;
987 break;
988 }
989
990 switch (Standard) {
991 case STV0900_AUTO_SEARCH:
992 dprintk("Auto\n");
993 stv0900_write_reg(i_params, fecmReg, 0x10);
994 stv0900_write_reg(i_params, prvitReg, 0x3F);
995 break;
996 case STV0900_SEARCH_DVBS1:
997 dprintk("DVBS1\n");
998 stv0900_write_reg(i_params, fecmReg, 0x00);
999 switch (PunctureRate) {
1000 case STV0900_FEC_UNKNOWN:
1001 default:
1002 stv0900_write_reg(i_params, prvitReg, 0x2F);
1003 break;
1004 case STV0900_FEC_1_2:
1005 stv0900_write_reg(i_params, prvitReg, 0x01);
1006 break;
1007 case STV0900_FEC_2_3:
1008 stv0900_write_reg(i_params, prvitReg, 0x02);
1009 break;
1010 case STV0900_FEC_3_4:
1011 stv0900_write_reg(i_params, prvitReg, 0x04);
1012 break;
1013 case STV0900_FEC_5_6:
1014 stv0900_write_reg(i_params, prvitReg, 0x08);
1015 break;
1016 case STV0900_FEC_7_8:
1017 stv0900_write_reg(i_params, prvitReg, 0x20);
1018 break;
1019 }
1020
1021 break;
1022 case STV0900_SEARCH_DSS:
1023 dprintk("DSS\n");
1024 stv0900_write_reg(i_params, fecmReg, 0x80);
1025 switch (PunctureRate) {
1026 case STV0900_FEC_UNKNOWN:
1027 default:
1028 stv0900_write_reg(i_params, prvitReg, 0x13);
1029 break;
1030 case STV0900_FEC_1_2:
1031 stv0900_write_reg(i_params, prvitReg, 0x01);
1032 break;
1033 case STV0900_FEC_2_3:
1034 stv0900_write_reg(i_params, prvitReg, 0x02);
1035 break;
1036 case STV0900_FEC_6_7:
1037 stv0900_write_reg(i_params, prvitReg, 0x10);
1038 break;
1039 }
1040 break;
1041 default:
1042 break;
1043 }
1044 }
1045
1046 static void stv0900_track_optimization(struct dvb_frontend *fe)
1047 {
1048 struct stv0900_state *state = fe->demodulator_priv;
1049 struct stv0900_internal *i_params = state->internal;
1050 enum fe_stv0900_demod_num demod = state->demod;
1051
1052 s32 srate, pilots, aclc, freq1, freq0,
1053 i = 0, timed, timef, blindTunSw = 0;
1054
1055 enum fe_stv0900_rolloff rolloff;
1056 enum fe_stv0900_modcode foundModcod;
1057
1058 dprintk(KERN_INFO "%s\n", __func__);
1059
1060 srate = stv0900_get_symbol_rate(i_params, i_params->mclk, demod);
1061 srate += stv0900_get_timing_offst(i_params, srate, demod);
1062
1063 switch (demod) {
1064 case STV0900_DEMOD_1:
1065 default:
1066 switch (i_params->dmd1_rslts.standard) {
1067 case STV0900_DVBS1_STANDARD:
1068 if (i_params->dmd1_srch_standard == STV0900_AUTO_SEARCH) {
1069 stv0900_write_bits(i_params, F0900_P1_DVBS1_ENABLE, 1);
1070 stv0900_write_bits(i_params, F0900_P1_DVBS2_ENABLE, 0);
1071 }
1072
1073 stv0900_write_bits(i_params, F0900_P1_ROLLOFF_CONTROL, i_params->rolloff);
1074 stv0900_write_bits(i_params, F0900_P1_MANUAL_ROLLOFF, 1);
1075 stv0900_write_reg(i_params, R0900_P1_ERRCTRL1, 0x75);
1076 break;
1077 case STV0900_DSS_STANDARD:
1078 if (i_params->dmd1_srch_standard == STV0900_AUTO_SEARCH) {
1079 stv0900_write_bits(i_params, F0900_P1_DVBS1_ENABLE, 1);
1080 stv0900_write_bits(i_params, F0900_P1_DVBS2_ENABLE, 0);
1081 }
1082
1083 stv0900_write_bits(i_params, F0900_P1_ROLLOFF_CONTROL, i_params->rolloff);
1084 stv0900_write_bits(i_params, F0900_P1_MANUAL_ROLLOFF, 1);
1085 stv0900_write_reg(i_params, R0900_P1_ERRCTRL1, 0x75);
1086 break;
1087 case STV0900_DVBS2_STANDARD:
1088 stv0900_write_bits(i_params, F0900_P1_DVBS1_ENABLE, 0);
1089 stv0900_write_bits(i_params, F0900_P1_DVBS2_ENABLE, 1);
1090 stv0900_write_reg(i_params, R0900_P1_ACLC, 0);
1091 stv0900_write_reg(i_params, R0900_P1_BCLC, 0);
1092 if (i_params->dmd1_rslts.frame_length == STV0900_LONG_FRAME) {
1093 foundModcod = stv0900_get_bits(i_params, F0900_P1_DEMOD_MODCOD);
1094 pilots = stv0900_get_bits(i_params, F0900_P1_DEMOD_TYPE) & 0x01;
1095 aclc = stv0900_get_optim_carr_loop(srate, foundModcod, pilots, i_params->chip_id);
1096 if (foundModcod <= STV0900_QPSK_910)
1097 stv0900_write_reg(i_params, R0900_P1_ACLC2S2Q, aclc);
1098 else if (foundModcod <= STV0900_8PSK_910) {
1099 stv0900_write_reg(i_params, R0900_P1_ACLC2S2Q, 0x2a);
1100 stv0900_write_reg(i_params, R0900_P1_ACLC2S28, aclc);
1101 }
1102
1103 if ((i_params->demod_mode == STV0900_SINGLE) && (foundModcod > STV0900_8PSK_910)) {
1104 if (foundModcod <= STV0900_16APSK_910) {
1105 stv0900_write_reg(i_params, R0900_P1_ACLC2S2Q, 0x2a);
1106 stv0900_write_reg(i_params, R0900_P1_ACLC2S216A, aclc);
1107 } else if (foundModcod <= STV0900_32APSK_910) {
1108 stv0900_write_reg(i_params, R0900_P1_ACLC2S2Q, 0x2a);
1109 stv0900_write_reg(i_params, R0900_P1_ACLC2S232A, aclc);
1110 }
1111 }
1112
1113 } else {
1114 aclc = stv0900_get_optim_short_carr_loop(srate, i_params->dmd1_rslts.modulation, i_params->chip_id);
1115 if (i_params->dmd1_rslts.modulation == STV0900_QPSK)
1116 stv0900_write_reg(i_params, R0900_P1_ACLC2S2Q, aclc);
1117
1118 else if (i_params->dmd1_rslts.modulation == STV0900_8PSK) {
1119 stv0900_write_reg(i_params, R0900_P1_ACLC2S2Q, 0x2a);
1120 stv0900_write_reg(i_params, R0900_P1_ACLC2S28, aclc);
1121 } else if (i_params->dmd1_rslts.modulation == STV0900_16APSK) {
1122 stv0900_write_reg(i_params, R0900_P1_ACLC2S2Q, 0x2a);
1123 stv0900_write_reg(i_params, R0900_P1_ACLC2S216A, aclc);
1124 } else if (i_params->dmd1_rslts.modulation == STV0900_32APSK) {
1125 stv0900_write_reg(i_params, R0900_P1_ACLC2S2Q, 0x2a);
1126 stv0900_write_reg(i_params, R0900_P1_ACLC2S232A, aclc);
1127 }
1128
1129 }
1130
1131 if (i_params->chip_id <= 0x11) {
1132 if (i_params->demod_mode != STV0900_SINGLE)
1133 stv0900_activate_s2_modcode(i_params, demod);
1134
1135 }
1136
1137 stv0900_write_reg(i_params, R0900_P1_ERRCTRL1, 0x67);
1138 break;
1139 case STV0900_UNKNOWN_STANDARD:
1140 default:
1141 stv0900_write_bits(i_params, F0900_P1_DVBS1_ENABLE, 1);
1142 stv0900_write_bits(i_params, F0900_P1_DVBS2_ENABLE, 1);
1143 break;
1144 }
1145
1146 freq1 = stv0900_read_reg(i_params, R0900_P1_CFR2);
1147 freq0 = stv0900_read_reg(i_params, R0900_P1_CFR1);
1148 rolloff = stv0900_get_bits(i_params, F0900_P1_ROLLOFF_STATUS);
1149 if (i_params->dmd1_srch_algo == STV0900_BLIND_SEARCH) {
1150 stv0900_write_reg(i_params, R0900_P1_SFRSTEP, 0x00);
1151 stv0900_write_bits(i_params, F0900_P1_SCAN_ENABLE, 0);
1152 stv0900_write_bits(i_params, F0900_P1_CFR_AUTOSCAN, 0);
1153 stv0900_write_reg(i_params, R0900_P1_TMGCFG2, 0x01);
1154 stv0900_set_symbol_rate(i_params, i_params->mclk, srate, demod);
1155 stv0900_set_max_symbol_rate(i_params, i_params->mclk, srate, demod);
1156 stv0900_set_min_symbol_rate(i_params, i_params->mclk, srate, demod);
1157 blindTunSw = 1;
1158 }
1159
1160 if (i_params->chip_id >= 0x20) {
1161 if ((i_params->dmd1_srch_standard == STV0900_SEARCH_DVBS1) || (i_params->dmd1_srch_standard == STV0900_SEARCH_DSS) || (i_params->dmd1_srch_standard == STV0900_AUTO_SEARCH)) {
1162 stv0900_write_reg(i_params, R0900_P1_VAVSRVIT, 0x0a);
1163 stv0900_write_reg(i_params, R0900_P1_VITSCALE, 0x0);
1164 }
1165 }
1166
1167 if (i_params->chip_id < 0x20)
1168 stv0900_write_reg(i_params, R0900_P1_CARHDR, 0x08);
1169
1170 if (i_params->chip_id == 0x10)
1171 stv0900_write_reg(i_params, R0900_P1_CORRELEXP, 0x0A);
1172
1173 stv0900_write_reg(i_params, R0900_P1_AGC2REF, 0x38);
1174
1175 if ((i_params->chip_id >= 0x20) || (blindTunSw == 1) || (i_params->dmd1_symbol_rate < 10000000)) {
1176 stv0900_write_reg(i_params, R0900_P1_CFRINIT1, freq1);
1177 stv0900_write_reg(i_params, R0900_P1_CFRINIT0, freq0);
1178 i_params->tuner1_bw = stv0900_carrier_width(srate, i_params->rolloff) + 10000000;
1179
1180 if ((i_params->chip_id >= 0x20) || (blindTunSw == 1)) {
1181 if (i_params->dmd1_srch_algo != STV0900_WARM_START)
1182 stv0900_set_bandwidth(fe, i_params->tuner1_bw);
1183 }
1184
1185 if ((i_params->dmd1_srch_algo == STV0900_BLIND_SEARCH) || (i_params->dmd1_symbol_rate < 10000000))
1186 msleep(50);
1187 else
1188 msleep(5);
1189
1190 stv0900_get_lock_timeout(&timed, &timef, srate, STV0900_WARM_START);
1191
1192 if (stv0900_get_demod_lock(i_params, demod, timed / 2) == FALSE) {
1193 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x1F);
1194 stv0900_write_reg(i_params, R0900_P1_CFRINIT1, freq1);
1195 stv0900_write_reg(i_params, R0900_P1_CFRINIT0, freq0);
1196 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x18);
1197 i = 0;
1198 while ((stv0900_get_demod_lock(i_params, demod, timed / 2) == FALSE) && (i <= 2)) {
1199 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x1F);
1200 stv0900_write_reg(i_params, R0900_P1_CFRINIT1, freq1);
1201 stv0900_write_reg(i_params, R0900_P1_CFRINIT0, freq0);
1202 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x18);
1203 i++;
1204 }
1205 }
1206
1207 }
1208
1209 if (i_params->chip_id >= 0x20)
1210 stv0900_write_reg(i_params, R0900_P1_CARFREQ, 0x49);
1211
1212 if ((i_params->dmd1_rslts.standard == STV0900_DVBS1_STANDARD) || (i_params->dmd1_rslts.standard == STV0900_DSS_STANDARD))
1213 stv0900_set_viterbi_tracq(i_params, demod);
1214
1215 break;
1216
1217 case STV0900_DEMOD_2:
1218 switch (i_params->dmd2_rslts.standard) {
1219 case STV0900_DVBS1_STANDARD:
1220
1221 if (i_params->dmd2_srch_stndrd == STV0900_AUTO_SEARCH) {
1222 stv0900_write_bits(i_params, F0900_P2_DVBS1_ENABLE, 1);
1223 stv0900_write_bits(i_params, F0900_P2_DVBS2_ENABLE, 0);
1224 }
1225
1226 stv0900_write_bits(i_params, F0900_P2_ROLLOFF_CONTROL, i_params->rolloff);
1227 stv0900_write_bits(i_params, F0900_P2_MANUAL_ROLLOFF, 1);
1228 stv0900_write_reg(i_params, R0900_P2_ERRCTRL1, 0x75);
1229 break;
1230 case STV0900_DSS_STANDARD:
1231 if (i_params->dmd2_srch_stndrd == STV0900_AUTO_SEARCH) {
1232 stv0900_write_bits(i_params, F0900_P2_DVBS1_ENABLE, 1);
1233 stv0900_write_bits(i_params, F0900_P2_DVBS2_ENABLE, 0);
1234 }
1235
1236 stv0900_write_bits(i_params, F0900_P2_ROLLOFF_CONTROL, i_params->rolloff);
1237 stv0900_write_bits(i_params, F0900_P2_MANUAL_ROLLOFF, 1);
1238 stv0900_write_reg(i_params, R0900_P2_ERRCTRL1, 0x75);
1239 break;
1240 case STV0900_DVBS2_STANDARD:
1241 stv0900_write_bits(i_params, F0900_P2_DVBS1_ENABLE, 0);
1242 stv0900_write_bits(i_params, F0900_P2_DVBS2_ENABLE, 1);
1243 stv0900_write_reg(i_params, R0900_P2_ACLC, 0);
1244 stv0900_write_reg(i_params, R0900_P2_BCLC, 0);
1245 if (i_params->dmd2_rslts.frame_length == STV0900_LONG_FRAME) {
1246 foundModcod = stv0900_get_bits(i_params, F0900_P2_DEMOD_MODCOD);
1247 pilots = stv0900_get_bits(i_params, F0900_P2_DEMOD_TYPE) & 0x01;
1248 aclc = stv0900_get_optim_carr_loop(srate, foundModcod, pilots, i_params->chip_id);
1249 if (foundModcod <= STV0900_QPSK_910)
1250 stv0900_write_reg(i_params, R0900_P2_ACLC2S2Q, aclc);
1251 else if (foundModcod <= STV0900_8PSK_910) {
1252 stv0900_write_reg(i_params, R0900_P2_ACLC2S2Q, 0x2a);
1253 stv0900_write_reg(i_params, R0900_P2_ACLC2S28, aclc);
1254 }
1255
1256 if ((i_params->demod_mode == STV0900_SINGLE) && (foundModcod > STV0900_8PSK_910)) {
1257 if (foundModcod <= STV0900_16APSK_910) {
1258 stv0900_write_reg(i_params, R0900_P2_ACLC2S2Q, 0x2a);
1259 stv0900_write_reg(i_params, R0900_P2_ACLC2S216A, aclc);
1260 } else if (foundModcod <= STV0900_32APSK_910) {
1261 stv0900_write_reg(i_params, R0900_P2_ACLC2S2Q, 0x2a);
1262 stv0900_write_reg(i_params, R0900_P2_ACLC2S232A, aclc);
1263 }
1264
1265 }
1266
1267 } else {
1268 aclc = stv0900_get_optim_short_carr_loop(srate,
1269 i_params->dmd2_rslts.modulation,
1270 i_params->chip_id);
1271
1272 if (i_params->dmd2_rslts.modulation == STV0900_QPSK)
1273 stv0900_write_reg(i_params, R0900_P2_ACLC2S2Q, aclc);
1274
1275 else if (i_params->dmd2_rslts.modulation == STV0900_8PSK) {
1276 stv0900_write_reg(i_params, R0900_P2_ACLC2S2Q, 0x2a);
1277 stv0900_write_reg(i_params, R0900_P2_ACLC2S28, aclc);
1278 } else if (i_params->dmd2_rslts.modulation == STV0900_16APSK) {
1279 stv0900_write_reg(i_params, R0900_P2_ACLC2S2Q, 0x2a);
1280 stv0900_write_reg(i_params, R0900_P2_ACLC2S216A, aclc);
1281 } else if (i_params->dmd2_rslts.modulation == STV0900_32APSK) {
1282 stv0900_write_reg(i_params, R0900_P2_ACLC2S2Q, 0x2a);
1283 stv0900_write_reg(i_params, R0900_P2_ACLC2S232A, aclc);
1284 }
1285 }
1286
1287 stv0900_write_reg(i_params, R0900_P2_ERRCTRL1, 0x67);
1288
1289 break;
1290 case STV0900_UNKNOWN_STANDARD:
1291 default:
1292 stv0900_write_bits(i_params, F0900_P2_DVBS1_ENABLE, 1);
1293 stv0900_write_bits(i_params, F0900_P2_DVBS2_ENABLE, 1);
1294 break;
1295 }
1296
1297 freq1 = stv0900_read_reg(i_params, R0900_P2_CFR2);
1298 freq0 = stv0900_read_reg(i_params, R0900_P2_CFR1);
1299 rolloff = stv0900_get_bits(i_params, F0900_P2_ROLLOFF_STATUS);
1300 if (i_params->dmd2_srch_algo == STV0900_BLIND_SEARCH) {
1301 stv0900_write_reg(i_params, R0900_P2_SFRSTEP, 0x00);
1302 stv0900_write_bits(i_params, F0900_P2_SCAN_ENABLE, 0);
1303 stv0900_write_bits(i_params, F0900_P2_CFR_AUTOSCAN, 0);
1304 stv0900_write_reg(i_params, R0900_P2_TMGCFG2, 0x01);
1305 stv0900_set_symbol_rate(i_params, i_params->mclk, srate, demod);
1306 stv0900_set_max_symbol_rate(i_params, i_params->mclk, srate, demod);
1307 stv0900_set_min_symbol_rate(i_params, i_params->mclk, srate, demod);
1308 blindTunSw = 1;
1309 }
1310
1311 if (i_params->chip_id >= 0x20) {
1312 if ((i_params->dmd2_srch_stndrd == STV0900_SEARCH_DVBS1) || (i_params->dmd2_srch_stndrd == STV0900_SEARCH_DSS) || (i_params->dmd2_srch_stndrd == STV0900_AUTO_SEARCH)) {
1313 stv0900_write_reg(i_params, R0900_P2_VAVSRVIT, 0x0a);
1314 stv0900_write_reg(i_params, R0900_P2_VITSCALE, 0x0);
1315 }
1316 }
1317
1318 if (i_params->chip_id < 0x20)
1319 stv0900_write_reg(i_params, R0900_P2_CARHDR, 0x08);
1320
1321 if (i_params->chip_id == 0x10)
1322 stv0900_write_reg(i_params, R0900_P2_CORRELEXP, 0x0a);
1323
1324 stv0900_write_reg(i_params, R0900_P2_AGC2REF, 0x38);
1325 if ((i_params->chip_id >= 0x20) || (blindTunSw == 1) || (i_params->dmd2_symbol_rate < 10000000)) {
1326 stv0900_write_reg(i_params, R0900_P2_CFRINIT1, freq1);
1327 stv0900_write_reg(i_params, R0900_P2_CFRINIT0, freq0);
1328 i_params->tuner2_bw = stv0900_carrier_width(srate, i_params->rolloff) + 10000000;
1329
1330 if ((i_params->chip_id >= 0x20) || (blindTunSw == 1)) {
1331 if (i_params->dmd2_srch_algo != STV0900_WARM_START)
1332 stv0900_set_bandwidth(fe, i_params->tuner2_bw);
1333 }
1334
1335 if ((i_params->dmd2_srch_algo == STV0900_BLIND_SEARCH) || (i_params->dmd2_symbol_rate < 10000000))
1336 msleep(50);
1337 else
1338 msleep(5);
1339
1340 stv0900_get_lock_timeout(&timed, &timef, srate, STV0900_WARM_START);
1341 if (stv0900_get_demod_lock(i_params, demod, timed / 2) == FALSE) {
1342 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x1F);
1343 stv0900_write_reg(i_params, R0900_P2_CFRINIT1, freq1);
1344 stv0900_write_reg(i_params, R0900_P2_CFRINIT0, freq0);
1345 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x18);
1346 i = 0;
1347 while ((stv0900_get_demod_lock(i_params, demod, timed / 2) == FALSE) && (i <= 2)) {
1348 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x1F);
1349 stv0900_write_reg(i_params, R0900_P2_CFRINIT1, freq1);
1350 stv0900_write_reg(i_params, R0900_P2_CFRINIT0, freq0);
1351 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x18);
1352 i++;
1353 }
1354 }
1355 }
1356
1357 if (i_params->chip_id >= 0x20)
1358 stv0900_write_reg(i_params, R0900_P2_CARFREQ, 0x49);
1359
1360 if ((i_params->dmd2_rslts.standard == STV0900_DVBS1_STANDARD) || (i_params->dmd2_rslts.standard == STV0900_DSS_STANDARD))
1361 stv0900_set_viterbi_tracq(i_params, demod);
1362
1363 break;
1364 }
1365 }
1366
1367 static int stv0900_get_fec_lock(struct stv0900_internal *i_params, enum fe_stv0900_demod_num demod, s32 time_out)
1368 {
1369 s32 timer = 0, lock = 0, header_field, pktdelin_field, lock_vit_field;
1370
1371 enum fe_stv0900_search_state dmd_state;
1372
1373 dprintk(KERN_INFO "%s\n", __func__);
1374
1375 dmd_reg(header_field, F0900_P1_HEADER_MODE, F0900_P2_HEADER_MODE);
1376 dmd_reg(pktdelin_field, F0900_P1_PKTDELIN_LOCK, F0900_P2_PKTDELIN_LOCK);
1377 dmd_reg(lock_vit_field, F0900_P1_LOCKEDVIT, F0900_P2_LOCKEDVIT);
1378
1379 dmd_state = stv0900_get_bits(i_params, header_field);
1380
1381 while ((timer < time_out) && (lock == 0)) {
1382 switch (dmd_state) {
1383 case STV0900_SEARCH:
1384 case STV0900_PLH_DETECTED:
1385 default:
1386 lock = 0;
1387 break;
1388 case STV0900_DVBS2_FOUND:
1389 lock = stv0900_get_bits(i_params, pktdelin_field);
1390 break;
1391 case STV0900_DVBS_FOUND:
1392 lock = stv0900_get_bits(i_params, lock_vit_field);
1393 break;
1394 }
1395
1396 if (lock == 0) {
1397 msleep(10);
1398 timer += 10;
1399 }
1400 }
1401
1402 if (lock)
1403 dprintk("DEMOD FEC LOCK OK\n");
1404 else
1405 dprintk("DEMOD FEC LOCK FAIL\n");
1406
1407 return lock;
1408 }
1409
1410 static int stv0900_wait_for_lock(struct stv0900_internal *i_params,
1411 enum fe_stv0900_demod_num demod,
1412 s32 dmd_timeout, s32 fec_timeout)
1413 {
1414
1415 s32 timer = 0, lock = 0, str_merg_rst_fld, str_merg_lock_fld;
1416
1417 dprintk(KERN_INFO "%s\n", __func__);
1418
1419 dmd_reg(str_merg_rst_fld, F0900_P1_RST_HWARE, F0900_P2_RST_HWARE);
1420 dmd_reg(str_merg_lock_fld, F0900_P1_TSFIFO_LINEOK, F0900_P2_TSFIFO_LINEOK);
1421
1422 lock = stv0900_get_demod_lock(i_params, demod, dmd_timeout);
1423
1424 if (lock)
1425 lock = lock && stv0900_get_fec_lock(i_params, demod, fec_timeout);
1426
1427 if (lock) {
1428 lock = 0;
1429
1430 dprintk(KERN_INFO "%s: Timer = %d, time_out = %d\n", __func__, timer, fec_timeout);
1431
1432 while ((timer < fec_timeout) && (lock == 0)) {
1433 lock = stv0900_get_bits(i_params, str_merg_lock_fld);
1434 msleep(1);
1435 timer++;
1436 }
1437 }
1438
1439 if (lock)
1440 dprintk(KERN_INFO "%s: DEMOD LOCK OK\n", __func__);
1441 else
1442 dprintk(KERN_INFO "%s: DEMOD LOCK FAIL\n", __func__);
1443
1444 if (lock)
1445 return TRUE;
1446 else
1447 return FALSE;
1448 }
1449
1450 enum fe_stv0900_tracking_standard stv0900_get_standard(struct dvb_frontend *fe,
1451 enum fe_stv0900_demod_num demod)
1452 {
1453 struct stv0900_state *state = fe->demodulator_priv;
1454 struct stv0900_internal *i_params = state->internal;
1455 enum fe_stv0900_tracking_standard fnd_standard;
1456 s32 state_field,
1457 dss_dvb_field;
1458
1459 dprintk(KERN_INFO "%s\n", __func__);
1460
1461 dmd_reg(state_field, F0900_P1_HEADER_MODE, F0900_P2_HEADER_MODE);
1462 dmd_reg(dss_dvb_field, F0900_P1_DSS_DVB, F0900_P2_DSS_DVB);
1463
1464 if (stv0900_get_bits(i_params, state_field) == 2)
1465 fnd_standard = STV0900_DVBS2_STANDARD;
1466
1467 else if (stv0900_get_bits(i_params, state_field) == 3) {
1468 if (stv0900_get_bits(i_params, dss_dvb_field) == 1)
1469 fnd_standard = STV0900_DSS_STANDARD;
1470 else
1471 fnd_standard = STV0900_DVBS1_STANDARD;
1472 } else
1473 fnd_standard = STV0900_UNKNOWN_STANDARD;
1474
1475 return fnd_standard;
1476 }
1477
1478 static s32 stv0900_get_carr_freq(struct stv0900_internal *i_params, u32 mclk,
1479 enum fe_stv0900_demod_num demod)
1480 {
1481 s32 cfr_field2, cfr_field1, cfr_field0,
1482 derot, rem1, rem2, intval1, intval2;
1483
1484 dmd_reg(cfr_field2, F0900_P1_CAR_FREQ2, F0900_P2_CAR_FREQ2);
1485 dmd_reg(cfr_field1, F0900_P1_CAR_FREQ1, F0900_P2_CAR_FREQ1);
1486 dmd_reg(cfr_field0, F0900_P1_CAR_FREQ0, F0900_P2_CAR_FREQ0);
1487
1488 derot = (stv0900_get_bits(i_params, cfr_field2) << 16) +
1489 (stv0900_get_bits(i_params, cfr_field1) << 8) +
1490 (stv0900_get_bits(i_params, cfr_field0));
1491
1492 derot = ge2comp(derot, 24);
1493 intval1 = mclk >> 12;
1494 intval2 = derot >> 12;
1495 rem1 = mclk % 0x1000;
1496 rem2 = derot % 0x1000;
1497 derot = (intval1 * intval2) +
1498 ((intval1 * rem2) >> 12) +
1499 ((intval2 * rem1) >> 12);
1500
1501 return derot;
1502 }
1503
1504 static u32 stv0900_get_tuner_freq(struct dvb_frontend *fe)
1505 {
1506 struct dvb_frontend_ops *frontend_ops = NULL;
1507 struct dvb_tuner_ops *tuner_ops = NULL;
1508 u32 frequency = 0;
1509
1510 if (&fe->ops)
1511 frontend_ops = &fe->ops;
1512
1513 if (&frontend_ops->tuner_ops)
1514 tuner_ops = &frontend_ops->tuner_ops;
1515
1516 if (tuner_ops->get_frequency) {
1517 if ((tuner_ops->get_frequency(fe, &frequency)) < 0)
1518 dprintk("%s: Invalid parameter\n", __func__);
1519 else
1520 dprintk("%s: Frequency=%d\n", __func__, frequency);
1521
1522 }
1523
1524 return frequency;
1525 }
1526
1527 static enum fe_stv0900_fec stv0900_get_vit_fec(struct stv0900_internal *i_params,
1528 enum fe_stv0900_demod_num demod)
1529 {
1530 s32 rate_fld, vit_curpun_fld;
1531 enum fe_stv0900_fec prate;
1532
1533 dmd_reg(vit_curpun_fld, F0900_P1_VIT_CURPUN, F0900_P2_VIT_CURPUN);
1534 rate_fld = stv0900_get_bits(i_params, vit_curpun_fld);
1535
1536 switch (rate_fld) {
1537 case 13:
1538 prate = STV0900_FEC_1_2;
1539 break;
1540 case 18:
1541 prate = STV0900_FEC_2_3;
1542 break;
1543 case 21:
1544 prate = STV0900_FEC_3_4;
1545 break;
1546 case 24:
1547 prate = STV0900_FEC_5_6;
1548 break;
1549 case 25:
1550 prate = STV0900_FEC_6_7;
1551 break;
1552 case 26:
1553 prate = STV0900_FEC_7_8;
1554 break;
1555 default:
1556 prate = STV0900_FEC_UNKNOWN;
1557 break;
1558 }
1559
1560 return prate;
1561 }
1562
1563 static enum fe_stv0900_signal_type stv0900_get_signal_params(struct dvb_frontend *fe)
1564 {
1565 struct stv0900_state *state = fe->demodulator_priv;
1566 struct stv0900_internal *i_params = state->internal;
1567 enum fe_stv0900_demod_num demod = state->demod;
1568 enum fe_stv0900_signal_type range = STV0900_OUTOFRANGE;
1569 s32 offsetFreq,
1570 srate_offset,
1571 i = 0;
1572
1573 u8 timing;
1574
1575 msleep(5);
1576 switch (demod) {
1577 case STV0900_DEMOD_1:
1578 default:
1579 if (i_params->dmd1_srch_algo == STV0900_BLIND_SEARCH) {
1580 timing = stv0900_read_reg(i_params, R0900_P1_TMGREG2);
1581 i = 0;
1582 stv0900_write_reg(i_params, R0900_P1_SFRSTEP, 0x5c);
1583
1584 while ((i <= 50) && (timing != 0) && (timing != 0xFF)) {
1585 timing = stv0900_read_reg(i_params, R0900_P1_TMGREG2);
1586 msleep(5);
1587 i += 5;
1588 }
1589 }
1590
1591 i_params->dmd1_rslts.standard = stv0900_get_standard(fe, demod);
1592 i_params->dmd1_rslts.frequency = stv0900_get_tuner_freq(fe);
1593 offsetFreq = stv0900_get_carr_freq(i_params, i_params->mclk, demod) / 1000;
1594 i_params->dmd1_rslts.frequency += offsetFreq;
1595 i_params->dmd1_rslts.symbol_rate = stv0900_get_symbol_rate(i_params, i_params->mclk, demod);
1596 srate_offset = stv0900_get_timing_offst(i_params, i_params->dmd1_rslts.symbol_rate, demod);
1597 i_params->dmd1_rslts.symbol_rate += srate_offset;
1598 i_params->dmd1_rslts.fec = stv0900_get_vit_fec(i_params, demod);
1599 i_params->dmd1_rslts.modcode = stv0900_get_bits(i_params, F0900_P1_DEMOD_MODCOD);
1600 i_params->dmd1_rslts.pilot = stv0900_get_bits(i_params, F0900_P1_DEMOD_TYPE) & 0x01;
1601 i_params->dmd1_rslts.frame_length = ((u32)stv0900_get_bits(i_params, F0900_P1_DEMOD_TYPE)) >> 1;
1602 i_params->dmd1_rslts.rolloff = stv0900_get_bits(i_params, F0900_P1_ROLLOFF_STATUS);
1603 switch (i_params->dmd1_rslts.standard) {
1604 case STV0900_DVBS2_STANDARD:
1605 i_params->dmd1_rslts.spectrum = stv0900_get_bits(i_params, F0900_P1_SPECINV_DEMOD);
1606 if (i_params->dmd1_rslts.modcode <= STV0900_QPSK_910)
1607 i_params->dmd1_rslts.modulation = STV0900_QPSK;
1608 else if (i_params->dmd1_rslts.modcode <= STV0900_8PSK_910)
1609 i_params->dmd1_rslts.modulation = STV0900_8PSK;
1610 else if (i_params->dmd1_rslts.modcode <= STV0900_16APSK_910)
1611 i_params->dmd1_rslts.modulation = STV0900_16APSK;
1612 else if (i_params->dmd1_rslts.modcode <= STV0900_32APSK_910)
1613 i_params->dmd1_rslts.modulation = STV0900_32APSK;
1614 else
1615 i_params->dmd1_rslts.modulation = STV0900_UNKNOWN;
1616 break;
1617 case STV0900_DVBS1_STANDARD:
1618 case STV0900_DSS_STANDARD:
1619 i_params->dmd1_rslts.spectrum = stv0900_get_bits(i_params, F0900_P1_IQINV);
1620 i_params->dmd1_rslts.modulation = STV0900_QPSK;
1621 break;
1622 default:
1623 break;
1624 }
1625
1626 if ((i_params->dmd1_srch_algo == STV0900_BLIND_SEARCH) || (i_params->dmd1_symbol_rate < 10000000)) {
1627 offsetFreq = i_params->dmd1_rslts.frequency - i_params->tuner1_freq;
1628 i_params->tuner1_freq = stv0900_get_tuner_freq(fe);
1629 if (ABS(offsetFreq) <= ((i_params->dmd1_srch_range / 2000) + 500))
1630 range = STV0900_RANGEOK;
1631 else
1632 if (ABS(offsetFreq) <= (stv0900_carrier_width(i_params->dmd1_rslts.symbol_rate, i_params->dmd1_rslts.rolloff) / 2000))
1633 range = STV0900_RANGEOK;
1634 else
1635 range = STV0900_OUTOFRANGE;
1636
1637 } else {
1638 if (ABS(offsetFreq) <= ((i_params->dmd1_srch_range / 2000) + 500))
1639 range = STV0900_RANGEOK;
1640 else
1641 range = STV0900_OUTOFRANGE;
1642 }
1643 break;
1644 case STV0900_DEMOD_2:
1645 if (i_params->dmd2_srch_algo == STV0900_BLIND_SEARCH) {
1646 timing = stv0900_read_reg(i_params, R0900_P2_TMGREG2);
1647 i = 0;
1648 stv0900_write_reg(i_params, R0900_P2_SFRSTEP, 0x5c);
1649
1650 while ((i <= 50) && (timing != 0) && (timing != 0xff)) {
1651 timing = stv0900_read_reg(i_params, R0900_P2_TMGREG2);
1652 msleep(5);
1653 i += 5;
1654 }
1655 }
1656
1657 i_params->dmd2_rslts.standard = stv0900_get_standard(fe, demod);
1658 i_params->dmd2_rslts.frequency = stv0900_get_tuner_freq(fe);
1659 offsetFreq = stv0900_get_carr_freq(i_params, i_params->mclk, demod) / 1000;
1660 i_params->dmd2_rslts.frequency += offsetFreq;
1661 i_params->dmd2_rslts.symbol_rate = stv0900_get_symbol_rate(i_params, i_params->mclk, demod);
1662 srate_offset = stv0900_get_timing_offst(i_params, i_params->dmd2_rslts.symbol_rate, demod);
1663 i_params->dmd2_rslts.symbol_rate += srate_offset;
1664 i_params->dmd2_rslts.fec = stv0900_get_vit_fec(i_params, demod);
1665 i_params->dmd2_rslts.modcode = stv0900_get_bits(i_params, F0900_P2_DEMOD_MODCOD);
1666 i_params->dmd2_rslts.pilot = stv0900_get_bits(i_params, F0900_P2_DEMOD_TYPE) & 0x01;
1667 i_params->dmd2_rslts.frame_length = ((u32)stv0900_get_bits(i_params, F0900_P2_DEMOD_TYPE)) >> 1;
1668 i_params->dmd2_rslts.rolloff = stv0900_get_bits(i_params, F0900_P2_ROLLOFF_STATUS);
1669 switch (i_params->dmd2_rslts.standard) {
1670 case STV0900_DVBS2_STANDARD:
1671 i_params->dmd2_rslts.spectrum = stv0900_get_bits(i_params, F0900_P2_SPECINV_DEMOD);
1672 if (i_params->dmd2_rslts.modcode <= STV0900_QPSK_910)
1673 i_params->dmd2_rslts.modulation = STV0900_QPSK;
1674 else if (i_params->dmd2_rslts.modcode <= STV0900_8PSK_910)
1675 i_params->dmd2_rslts.modulation = STV0900_8PSK;
1676 else if (i_params->dmd2_rslts.modcode <= STV0900_16APSK_910)
1677 i_params->dmd2_rslts.modulation = STV0900_16APSK;
1678 else if (i_params->dmd2_rslts.modcode <= STV0900_32APSK_910)
1679 i_params->dmd2_rslts.modulation = STV0900_32APSK;
1680 else
1681 i_params->dmd2_rslts.modulation = STV0900_UNKNOWN;
1682 break;
1683 case STV0900_DVBS1_STANDARD:
1684 case STV0900_DSS_STANDARD:
1685 i_params->dmd2_rslts.spectrum = stv0900_get_bits(i_params, F0900_P2_IQINV);
1686 i_params->dmd2_rslts.modulation = STV0900_QPSK;
1687 break;
1688 default:
1689 break;
1690 }
1691
1692 if ((i_params->dmd2_srch_algo == STV0900_BLIND_SEARCH) || (i_params->dmd2_symbol_rate < 10000000)) {
1693 offsetFreq = i_params->dmd2_rslts.frequency - i_params->tuner2_freq;
1694 i_params->tuner2_freq = stv0900_get_tuner_freq(fe);
1695
1696 if (ABS(offsetFreq) <= ((i_params->dmd2_srch_range / 2000) + 500))
1697 range = STV0900_RANGEOK;
1698 else
1699 if (ABS(offsetFreq) <= (stv0900_carrier_width(i_params->dmd2_rslts.symbol_rate, i_params->dmd2_rslts.rolloff) / 2000))
1700 range = STV0900_RANGEOK;
1701 else
1702 range = STV0900_OUTOFRANGE;
1703 } else {
1704 if (ABS(offsetFreq) <= ((i_params->dmd2_srch_range / 2000) + 500))
1705 range = STV0900_RANGEOK;
1706 else
1707 range = STV0900_OUTOFRANGE;
1708 }
1709
1710 break;
1711 }
1712
1713 return range;
1714 }
1715
1716 static enum fe_stv0900_signal_type stv0900_dvbs1_acq_workaround(struct dvb_frontend *fe)
1717 {
1718 struct stv0900_state *state = fe->demodulator_priv;
1719 struct stv0900_internal *i_params = state->internal;
1720 enum fe_stv0900_demod_num demod = state->demod;
1721
1722 s32 srate, demod_timeout,
1723 fec_timeout, freq1, freq0;
1724 enum fe_stv0900_signal_type signal_type = STV0900_NODATA;;
1725
1726 switch (demod) {
1727 case STV0900_DEMOD_1:
1728 default:
1729 i_params->dmd1_rslts.locked = FALSE;
1730 if (stv0900_get_bits(i_params, F0900_P1_HEADER_MODE) == STV0900_DVBS_FOUND) {
1731 srate = stv0900_get_symbol_rate(i_params, i_params->mclk, demod);
1732 srate += stv0900_get_timing_offst(i_params, srate, demod);
1733 if (i_params->dmd1_srch_algo == STV0900_BLIND_SEARCH)
1734 stv0900_set_symbol_rate(i_params, i_params->mclk, srate, demod);
1735
1736 stv0900_get_lock_timeout(&demod_timeout, &fec_timeout, srate, STV0900_WARM_START);
1737 freq1 = stv0900_read_reg(i_params, R0900_P1_CFR2);
1738 freq0 = stv0900_read_reg(i_params, R0900_P1_CFR1);
1739 stv0900_write_bits(i_params, F0900_P1_CFR_AUTOSCAN, 0);
1740 stv0900_write_bits(i_params, F0900_P1_SPECINV_CONTROL, STV0900_IQ_FORCE_SWAPPED);
1741 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x1C);
1742 stv0900_write_reg(i_params, R0900_P1_CFRINIT1, freq1);
1743 stv0900_write_reg(i_params, R0900_P1_CFRINIT0, freq0);
1744 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x18);
1745 if (stv0900_wait_for_lock(i_params, demod, demod_timeout, fec_timeout) == TRUE) {
1746 i_params->dmd1_rslts.locked = TRUE;
1747 signal_type = stv0900_get_signal_params(fe);
1748 stv0900_track_optimization(fe);
1749 } else {
1750 stv0900_write_bits(i_params, F0900_P1_SPECINV_CONTROL, STV0900_IQ_FORCE_NORMAL);
1751 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x1c);
1752 stv0900_write_reg(i_params, R0900_P1_CFRINIT1, freq1);
1753 stv0900_write_reg(i_params, R0900_P1_CFRINIT0, freq0);
1754 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x18);
1755 if (stv0900_wait_for_lock(i_params, demod, demod_timeout, fec_timeout) == TRUE) {
1756 i_params->dmd1_rslts.locked = TRUE;
1757 signal_type = stv0900_get_signal_params(fe);
1758 stv0900_track_optimization(fe);
1759 }
1760
1761 }
1762
1763 } else
1764 i_params->dmd1_rslts.locked = FALSE;
1765
1766 break;
1767 case STV0900_DEMOD_2:
1768 i_params->dmd2_rslts.locked = FALSE;
1769 if (stv0900_get_bits(i_params, F0900_P2_HEADER_MODE) == STV0900_DVBS_FOUND) {
1770 srate = stv0900_get_symbol_rate(i_params, i_params->mclk, demod);
1771 srate += stv0900_get_timing_offst(i_params, srate, demod);
1772
1773 if (i_params->dmd2_srch_algo == STV0900_BLIND_SEARCH)
1774 stv0900_set_symbol_rate(i_params, i_params->mclk, srate, demod);
1775
1776 stv0900_get_lock_timeout(&demod_timeout, &fec_timeout, srate, STV0900_WARM_START);
1777 freq1 = stv0900_read_reg(i_params, R0900_P2_CFR2);
1778 freq0 = stv0900_read_reg(i_params, R0900_P2_CFR1);
1779 stv0900_write_bits(i_params, F0900_P2_CFR_AUTOSCAN, 0);
1780 stv0900_write_bits(i_params, F0900_P2_SPECINV_CONTROL, STV0900_IQ_FORCE_SWAPPED);
1781 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x1C);
1782 stv0900_write_reg(i_params, R0900_P2_CFRINIT1, freq1);
1783 stv0900_write_reg(i_params, R0900_P2_CFRINIT0, freq0);
1784 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x18);
1785
1786 if (stv0900_wait_for_lock(i_params, demod, demod_timeout, fec_timeout) == TRUE) {
1787 i_params->dmd2_rslts.locked = TRUE;
1788 signal_type = stv0900_get_signal_params(fe);
1789 stv0900_track_optimization(fe);
1790 } else {
1791 stv0900_write_bits(i_params, F0900_P2_SPECINV_CONTROL, STV0900_IQ_FORCE_NORMAL);
1792 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x1c);
1793 stv0900_write_reg(i_params, R0900_P2_CFRINIT1, freq1);
1794 stv0900_write_reg(i_params, R0900_P2_CFRINIT0, freq0);
1795 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x18);
1796
1797 if (stv0900_wait_for_lock(i_params, demod, demod_timeout, fec_timeout) == TRUE) {
1798 i_params->dmd2_rslts.locked = TRUE;
1799 signal_type = stv0900_get_signal_params(fe);
1800 stv0900_track_optimization(fe);
1801 }
1802
1803 }
1804
1805 } else
1806 i_params->dmd1_rslts.locked = FALSE;
1807
1808 break;
1809 }
1810
1811 return signal_type;
1812 }
1813
1814 static u16 stv0900_blind_check_agc2_min_level(struct stv0900_internal *i_params,
1815 enum fe_stv0900_demod_num demod)
1816 {
1817 u32 minagc2level = 0xffff,
1818 agc2level,
1819 init_freq, freq_step;
1820
1821 s32 i, j, nb_steps, direction;
1822
1823 dprintk(KERN_INFO "%s\n", __func__);
1824
1825 switch (demod) {
1826 case STV0900_DEMOD_1:
1827 default:
1828 stv0900_write_reg(i_params, R0900_P1_AGC2REF, 0x38);
1829 stv0900_write_bits(i_params, F0900_P1_SCAN_ENABLE, 1);
1830 stv0900_write_bits(i_params, F0900_P1_CFR_AUTOSCAN, 1);
1831
1832 stv0900_write_reg(i_params, R0900_P1_SFRUP1, 0x83);
1833 stv0900_write_reg(i_params, R0900_P1_SFRUP0, 0xc0);
1834
1835 stv0900_write_reg(i_params, R0900_P1_SFRLOW1, 0x82);
1836 stv0900_write_reg(i_params, R0900_P1_SFRLOW0, 0xa0);
1837 stv0900_write_reg(i_params, R0900_P1_DMDT0M, 0x0);
1838
1839 stv0900_set_symbol_rate(i_params, i_params->mclk, 1000000, demod);
1840 nb_steps = -1 + (i_params->dmd1_srch_range / 1000000);
1841 nb_steps /= 2;
1842 nb_steps = (2 * nb_steps) + 1;
1843
1844 if (nb_steps < 0)
1845 nb_steps = 1;
1846
1847 direction = 1;
1848
1849 freq_step = (1000000 << 8) / (i_params->mclk >> 8);
1850
1851 init_freq = 0;
1852
1853 for (i = 0; i < nb_steps; i++) {
1854 if (direction > 0)
1855 init_freq = init_freq + (freq_step * i);
1856 else
1857 init_freq = init_freq - (freq_step * i);
1858
1859 direction *= -1;
1860 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x5C);
1861 stv0900_write_reg(i_params, R0900_P1_CFRINIT1, (init_freq >> 8) & 0xff);
1862 stv0900_write_reg(i_params, R0900_P1_CFRINIT0, init_freq & 0xff);
1863 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x58);
1864 msleep(10);
1865 agc2level = 0;
1866
1867 for (j = 0; j < 10; j++)
1868 agc2level += (stv0900_read_reg(i_params, R0900_P1_AGC2I1) << 8)
1869 | stv0900_read_reg(i_params, R0900_P1_AGC2I0);
1870
1871 agc2level /= 10;
1872
1873 if (agc2level < minagc2level)
1874 minagc2level = agc2level;
1875 }
1876 break;
1877 case STV0900_DEMOD_2:
1878 stv0900_write_reg(i_params, R0900_P2_AGC2REF, 0x38);
1879 stv0900_write_bits(i_params, F0900_P2_SCAN_ENABLE, 1);
1880 stv0900_write_bits(i_params, F0900_P2_CFR_AUTOSCAN, 1);
1881 stv0900_write_reg(i_params, R0900_P2_SFRUP1, 0x83);
1882 stv0900_write_reg(i_params, R0900_P2_SFRUP0, 0xc0);
1883 stv0900_write_reg(i_params, R0900_P2_SFRLOW1, 0x82);
1884 stv0900_write_reg(i_params, R0900_P2_SFRLOW0, 0xa0);
1885 stv0900_write_reg(i_params, R0900_P2_DMDT0M, 0x0);
1886 stv0900_set_symbol_rate(i_params, i_params->mclk, 1000000, demod);
1887 nb_steps = -1 + (i_params->dmd2_srch_range / 1000000);
1888 nb_steps /= 2;
1889 nb_steps = (2 * nb_steps) + 1;
1890
1891 if (nb_steps < 0)
1892 nb_steps = 1;
1893
1894 direction = 1;
1895 freq_step = (1000000 << 8) / (i_params->mclk >> 8);
1896 init_freq = 0;
1897 for (i = 0; i < nb_steps; i++) {
1898 if (direction > 0)
1899 init_freq = init_freq + (freq_step * i);
1900 else
1901 init_freq = init_freq - (freq_step * i);
1902
1903 direction *= -1;
1904
1905 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x5C);
1906 stv0900_write_reg(i_params, R0900_P2_CFRINIT1, (init_freq >> 8) & 0xff);
1907 stv0900_write_reg(i_params, R0900_P2_CFRINIT0, init_freq & 0xff);
1908 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x58);
1909
1910 msleep(10);
1911 agc2level = 0;
1912 for (j = 0; j < 10; j++)
1913 agc2level += (stv0900_read_reg(i_params, R0900_P2_AGC2I1) << 8)
1914 | stv0900_read_reg(i_params, R0900_P2_AGC2I0);
1915
1916 agc2level /= 10;
1917
1918 if (agc2level < minagc2level)
1919 minagc2level = agc2level;
1920 }
1921 break;
1922 }
1923
1924 return (u16)minagc2level;
1925 }
1926
1927 static u32 stv0900_search_srate_coarse(struct dvb_frontend *fe)
1928 {
1929 struct stv0900_state *state = fe->demodulator_priv;
1930 struct stv0900_internal *i_params = state->internal;
1931 enum fe_stv0900_demod_num demod = state->demod;
1932 int timingLock = FALSE;
1933 s32 i, timingcpt = 0,
1934 direction = 1,
1935 nb_steps,
1936 current_step = 0,
1937 tuner_freq;
1938
1939 u32 coarse_srate = 0, agc2_integr = 0, currier_step = 1200;
1940
1941 switch (demod) {
1942 case STV0900_DEMOD_1:
1943 default:
1944 stv0900_write_bits(i_params, F0900_P1_I2C_DEMOD_MODE, 0x1F);
1945 stv0900_write_reg(i_params, R0900_P1_TMGCFG, 0x12);
1946 stv0900_write_reg(i_params, R0900_P1_TMGTHRISE, 0xf0);
1947 stv0900_write_reg(i_params, R0900_P1_TMGTHFALL, 0xe0);
1948 stv0900_write_bits(i_params, F0900_P1_SCAN_ENABLE, 1);
1949 stv0900_write_bits(i_params, F0900_P1_CFR_AUTOSCAN, 1);
1950 stv0900_write_reg(i_params, R0900_P1_SFRUP1, 0x83);
1951 stv0900_write_reg(i_params, R0900_P1_SFRUP0, 0xc0);
1952 stv0900_write_reg(i_params, R0900_P1_SFRLOW1, 0x82);
1953 stv0900_write_reg(i_params, R0900_P1_SFRLOW0, 0xa0);
1954 stv0900_write_reg(i_params, R0900_P1_DMDT0M, 0x0);
1955 stv0900_write_reg(i_params, R0900_P1_AGC2REF, 0x50);
1956
1957 if (i_params->chip_id >= 0x20) {
1958 stv0900_write_reg(i_params, R0900_P1_CARFREQ, 0x6a);
1959 stv0900_write_reg(i_params, R0900_P1_SFRSTEP, 0x95);
1960 } else {
1961 stv0900_write_reg(i_params, R0900_P1_CARFREQ, 0xed);
1962 stv0900_write_reg(i_params, R0900_P1_SFRSTEP, 0x73);
1963 }
1964
1965 if (i_params->dmd1_symbol_rate <= 2000000)
1966 currier_step = 1000;
1967 else if (i_params->dmd1_symbol_rate <= 5000000)
1968 currier_step = 2000;
1969 else if (i_params->dmd1_symbol_rate <= 12000000)
1970 currier_step = 3000;
1971 else
1972 currier_step = 5000;
1973
1974 nb_steps = -1 + ((i_params->dmd1_srch_range / 1000) / currier_step);
1975 nb_steps /= 2;
1976 nb_steps = (2 * nb_steps) + 1;
1977
1978 if (nb_steps < 0)
1979 nb_steps = 1;
1980
1981 else if (nb_steps > 10) {
1982 nb_steps = 11;
1983 currier_step = (i_params->dmd1_srch_range / 1000) / 10;
1984 }
1985
1986 current_step = 0;
1987
1988 direction = 1;
1989 tuner_freq = i_params->tuner1_freq;
1990
1991 while ((timingLock == FALSE) && (current_step < nb_steps)) {
1992 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x5F);
1993 stv0900_write_bits(i_params, F0900_P1_I2C_DEMOD_MODE, 0x0);
1994
1995 msleep(50);
1996
1997 for (i = 0; i < 10; i++) {
1998 if (stv0900_get_bits(i_params, F0900_P1_TMGLOCK_QUALITY) >= 2)
1999 timingcpt++;
2000
2001 agc2_integr += (stv0900_read_reg(i_params, R0900_P1_AGC2I1) << 8) | stv0900_read_reg(i_params, R0900_P1_AGC2I0);
2002
2003 }
2004
2005 agc2_integr /= 10;
2006 coarse_srate = stv0900_get_symbol_rate(i_params, i_params->mclk, demod);
2007 current_step++;
2008 direction *= -1;
2009
2010 dprintk("lock: I2C_DEMOD_MODE_FIELD =0. Search started. tuner freq=%d agc2=0x%x srate_coarse=%d tmg_cpt=%d\n", tuner_freq, agc2_integr, coarse_srate, timingcpt);
2011
2012 if ((timingcpt >= 5) && (agc2_integr < 0x1F00) && (coarse_srate < 55000000) && (coarse_srate > 850000)) {
2013 timingLock = TRUE;
2014 }
2015
2016 else if (current_step < nb_steps) {
2017 if (direction > 0)
2018 tuner_freq += (current_step * currier_step);
2019 else
2020 tuner_freq -= (current_step * currier_step);
2021
2022 stv0900_set_tuner(fe, tuner_freq, i_params->tuner1_bw);
2023 }
2024 }
2025
2026 if (timingLock == FALSE)
2027 coarse_srate = 0;
2028 else
2029 coarse_srate = stv0900_get_symbol_rate(i_params, i_params->mclk, demod);
2030 break;
2031 case STV0900_DEMOD_2:
2032 stv0900_write_bits(i_params, F0900_P2_I2C_DEMOD_MODE, 0x1F);
2033 stv0900_write_reg(i_params, R0900_P2_TMGCFG, 0x12);
2034 stv0900_write_reg(i_params, R0900_P2_TMGTHRISE, 0xf0);
2035 stv0900_write_reg(i_params, R0900_P2_TMGTHFALL, 0xe0);
2036 stv0900_write_bits(i_params, F0900_P2_SCAN_ENABLE, 1);
2037 stv0900_write_bits(i_params, F0900_P2_CFR_AUTOSCAN, 1);
2038 stv0900_write_reg(i_params, R0900_P2_SFRUP1, 0x83);
2039 stv0900_write_reg(i_params, R0900_P2_SFRUP0, 0xc0);
2040 stv0900_write_reg(i_params, R0900_P2_SFRLOW1, 0x82);
2041 stv0900_write_reg(i_params, R0900_P2_SFRLOW0, 0xa0);
2042 stv0900_write_reg(i_params, R0900_P2_DMDT0M, 0x0);
2043 stv0900_write_reg(i_params, R0900_P2_AGC2REF, 0x50);
2044
2045 if (i_params->chip_id >= 0x20) {
2046 stv0900_write_reg(i_params, R0900_P2_CARFREQ, 0x6a);
2047 stv0900_write_reg(i_params, R0900_P2_SFRSTEP, 0x95);
2048 } else {
2049 stv0900_write_reg(i_params, R0900_P2_CARFREQ, 0xed);
2050 stv0900_write_reg(i_params, R0900_P2_SFRSTEP, 0x73);
2051 }
2052
2053 if (i_params->dmd2_symbol_rate <= 2000000)
2054 currier_step = 1000;
2055 else if (i_params->dmd2_symbol_rate <= 5000000)
2056 currier_step = 2000;
2057 else if (i_params->dmd2_symbol_rate <= 12000000)
2058 currier_step = 3000;
2059 else
2060 currier_step = 5000;
2061
2062
2063 nb_steps = -1 + ((i_params->dmd2_srch_range / 1000) / currier_step);
2064 nb_steps /= 2;
2065 nb_steps = (2 * nb_steps) + 1;
2066
2067 if (nb_steps < 0)
2068 nb_steps = 1;
2069 else if (nb_steps > 10) {
2070 nb_steps = 11;
2071 currier_step = (i_params->dmd2_srch_range / 1000) / 10;
2072 }
2073
2074 current_step = 0;
2075 direction = 1;
2076 tuner_freq = i_params->tuner2_freq;
2077
2078 while ((timingLock == FALSE) && (current_step < nb_steps)) {
2079 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x5F);
2080 stv0900_write_bits(i_params, F0900_P2_I2C_DEMOD_MODE, 0x0);
2081
2082 msleep(50);
2083 timingcpt = 0;
2084
2085 for (i = 0; i < 20; i++) {
2086 if (stv0900_get_bits(i_params, F0900_P2_TMGLOCK_QUALITY) >= 2)
2087 timingcpt++;
2088 agc2_integr += (stv0900_read_reg(i_params, R0900_P2_AGC2I1) << 8)
2089 | stv0900_read_reg(i_params, R0900_P2_AGC2I0);
2090 }
2091
2092 agc2_integr /= 20;
2093 coarse_srate = stv0900_get_symbol_rate(i_params, i_params->mclk, demod);
2094 if ((timingcpt >= 10) && (agc2_integr < 0x1F00) && (coarse_srate < 55000000) && (coarse_srate > 850000))
2095 timingLock = TRUE;
2096 else {
2097 current_step++;
2098 direction *= -1;
2099
2100 if (direction > 0)
2101 tuner_freq += (current_step * currier_step);
2102 else
2103 tuner_freq -= (current_step * currier_step);
2104
2105 stv0900_set_tuner(fe, tuner_freq, i_params->tuner2_bw);
2106 }
2107 }
2108
2109 if (timingLock == FALSE)
2110 coarse_srate = 0;
2111 else
2112 coarse_srate = stv0900_get_symbol_rate(i_params, i_params->mclk, demod);
2113 break;
2114 }
2115
2116 return coarse_srate;
2117 }
2118
2119 static u32 stv0900_search_srate_fine(struct dvb_frontend *fe)
2120 {
2121 struct stv0900_state *state = fe->demodulator_priv;
2122 struct stv0900_internal *i_params = state->internal;
2123 enum fe_stv0900_demod_num demod = state->demod;
2124 u32 coarse_srate,
2125 coarse_freq,
2126 symb;
2127
2128 coarse_srate = stv0900_get_symbol_rate(i_params, i_params->mclk, demod);
2129
2130 switch (demod) {
2131 case STV0900_DEMOD_1:
2132 default:
2133 coarse_freq = (stv0900_read_reg(i_params, R0900_P1_CFR2) << 8)
2134 | stv0900_read_reg(i_params, R0900_P1_CFR1);
2135 symb = 13 * (coarse_srate / 10);
2136
2137 if (symb < i_params->dmd1_symbol_rate)
2138 coarse_srate = 0;
2139 else {
2140 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x1F);
2141 stv0900_write_reg(i_params, R0900_P1_TMGCFG2, 0x01);
2142 stv0900_write_reg(i_params, R0900_P1_TMGTHRISE, 0x20);
2143 stv0900_write_reg(i_params, R0900_P1_TMGTHFALL, 0x00);
2144 stv0900_write_reg(i_params, R0900_P1_TMGCFG, 0xd2);
2145 stv0900_write_bits(i_params, F0900_P1_CFR_AUTOSCAN, 0);
2146
2147 if (i_params->chip_id >= 0x20)
2148 stv0900_write_reg(i_params, R0900_P1_CARFREQ, 0x49);
2149 else
2150 stv0900_write_reg(i_params, R0900_P1_CARFREQ, 0xed);
2151
2152 if (coarse_srate > 3000000) {
2153 symb = 13 * (coarse_srate / 10);
2154 symb = (symb / 1000) * 65536;
2155 symb /= (i_params->mclk / 1000);
2156 stv0900_write_reg(i_params, R0900_P1_SFRUP1, (symb >> 8) & 0x7F);
2157 stv0900_write_reg(i_params, R0900_P1_SFRUP0, (symb & 0xFF));
2158
2159 symb = 10 * (coarse_srate / 13);
2160 symb = (symb / 1000) * 65536;
2161 symb /= (i_params->mclk / 1000);
2162
2163 stv0900_write_reg(i_params, R0900_P1_SFRLOW1, (symb >> 8) & 0x7F);
2164 stv0900_write_reg(i_params, R0900_P1_SFRLOW0, (symb & 0xFF));
2165
2166 symb = (coarse_srate / 1000) * 65536;
2167 symb /= (i_params->mclk / 1000);
2168 stv0900_write_reg(i_params, R0900_P1_SFRINIT1, (symb >> 8) & 0xFF);
2169 stv0900_write_reg(i_params, R0900_P1_SFRINIT0, (symb & 0xFF));
2170 } else {
2171 symb = 13 * (coarse_srate / 10);
2172 symb = (symb / 100) * 65536;
2173 symb /= (i_params->mclk / 100);
2174 stv0900_write_reg(i_params, R0900_P1_SFRUP1, (symb >> 8) & 0x7F);
2175 stv0900_write_reg(i_params, R0900_P1_SFRUP0, (symb & 0xFF));
2176
2177 symb = 10 * (coarse_srate / 14);
2178 symb = (symb / 100) * 65536;
2179 symb /= (i_params->mclk / 100);
2180 stv0900_write_reg(i_params, R0900_P1_SFRLOW1, (symb >> 8) & 0x7F);
2181 stv0900_write_reg(i_params, R0900_P1_SFRLOW0, (symb & 0xFF));
2182
2183 symb = (coarse_srate / 100) * 65536;
2184 symb /= (i_params->mclk / 100);
2185 stv0900_write_reg(i_params, R0900_P1_SFRINIT1, (symb >> 8) & 0xFF);
2186 stv0900_write_reg(i_params, R0900_P1_SFRINIT0, (symb & 0xFF));
2187 }
2188
2189 stv0900_write_reg(i_params, R0900_P1_DMDT0M, 0x20);
2190 stv0900_write_reg(i_params, R0900_P1_CFRINIT1, (coarse_freq >> 8) & 0xff);
2191 stv0900_write_reg(i_params, R0900_P1_CFRINIT0, coarse_freq & 0xff);
2192 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x15);
2193 }
2194 break;
2195 case STV0900_DEMOD_2:
2196 coarse_freq = (stv0900_read_reg(i_params, R0900_P2_CFR2) << 8)
2197 | stv0900_read_reg(i_params, R0900_P2_CFR1);
2198
2199 symb = 13 * (coarse_srate / 10);
2200
2201 if (symb < i_params->dmd2_symbol_rate)
2202 coarse_srate = 0;
2203 else {
2204 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x1F);
2205 stv0900_write_reg(i_params, R0900_P2_TMGCFG2, 0x01);
2206 stv0900_write_reg(i_params, R0900_P2_TMGTHRISE, 0x20);
2207 stv0900_write_reg(i_params, R0900_P2_TMGTHFALL, 0x00);
2208 stv0900_write_reg(i_params, R0900_P2_TMGCFG, 0xd2);
2209 stv0900_write_bits(i_params, F0900_P2_CFR_AUTOSCAN, 0);
2210
2211 if (i_params->chip_id >= 0x20)
2212 stv0900_write_reg(i_params, R0900_P2_CARFREQ, 0x49);
2213 else
2214 stv0900_write_reg(i_params, R0900_P2_CARFREQ, 0xed);
2215
2216 if (coarse_srate > 3000000) {
2217 symb = 13 * (coarse_srate / 10);
2218 symb = (symb / 1000) * 65536;
2219 symb /= (i_params->mclk / 1000);
2220 stv0900_write_reg(i_params, R0900_P2_SFRUP1, (symb >> 8) & 0x7F);
2221 stv0900_write_reg(i_params, R0900_P2_SFRUP0, (symb & 0xFF));
2222
2223 symb = 10 * (coarse_srate / 13);
2224 symb = (symb / 1000) * 65536;
2225 symb /= (i_params->mclk / 1000);
2226
2227 stv0900_write_reg(i_params, R0900_P2_SFRLOW1, (symb >> 8) & 0x7F);
2228 stv0900_write_reg(i_params, R0900_P2_SFRLOW0, (symb & 0xFF));
2229
2230 symb = (coarse_srate / 1000) * 65536;
2231 symb /= (i_params->mclk / 1000);
2232 stv0900_write_reg(i_params, R0900_P2_SFRINIT1, (symb >> 8) & 0xFF);
2233 stv0900_write_reg(i_params, R0900_P2_SFRINIT0, (symb & 0xFF));
2234 } else {
2235 symb = 13 * (coarse_srate / 10);
2236 symb = (symb / 100) * 65536;
2237 symb /= (i_params->mclk / 100);
2238 stv0900_write_reg(i_params, R0900_P2_SFRUP1, (symb >> 8) & 0x7F);
2239 stv0900_write_reg(i_params, R0900_P2_SFRUP0, (symb & 0xFF));
2240
2241 symb = 10 * (coarse_srate / 14);
2242 symb = (symb / 100) * 65536;
2243 symb /= (i_params->mclk / 100);
2244 stv0900_write_reg(i_params, R0900_P2_SFRLOW1, (symb >> 8) & 0x7F);
2245 stv0900_write_reg(i_params, R0900_P2_SFRLOW0, (symb & 0xFF));
2246
2247 symb = (coarse_srate / 100) * 65536;
2248 symb /= (i_params->mclk / 100);
2249 stv0900_write_reg(i_params, R0900_P2_SFRINIT1, (symb >> 8) & 0xFF);
2250 stv0900_write_reg(i_params, R0900_P2_SFRINIT0, (symb & 0xFF));
2251 }
2252
2253 stv0900_write_reg(i_params, R0900_P2_DMDT0M, 0x20);
2254 stv0900_write_reg(i_params, R0900_P2_CFRINIT1, (coarse_freq >> 8) & 0xff);
2255 stv0900_write_reg(i_params, R0900_P2_CFRINIT0, coarse_freq & 0xff);
2256 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x15);
2257 }
2258
2259 break;
2260 }
2261
2262 return coarse_srate;
2263 }
2264
2265 static int stv0900_blind_search_algo(struct dvb_frontend *fe)
2266 {
2267 struct stv0900_state *state = fe->demodulator_priv;
2268 struct stv0900_internal *i_params = state->internal;
2269 enum fe_stv0900_demod_num demod = state->demod;
2270 u8 k_ref_tmg, k_ref_tmg_max, k_ref_tmg_min;
2271 u32 coarse_srate;
2272 int lock = FALSE, coarse_fail = FALSE;
2273 s32 demod_timeout = 500, fec_timeout = 50, kref_tmg_reg, fail_cpt, i, agc2_overflow;
2274 u16 agc2_integr;
2275 u8 dstatus2;
2276
2277 dprintk(KERN_INFO "%s\n", __func__);
2278
2279 if (i_params->chip_id < 0x20) {
2280 k_ref_tmg_max = 233;
2281 k_ref_tmg_min = 143;
2282 } else {
2283 k_ref_tmg_max = 120;
2284 k_ref_tmg_min = 30;
2285 }
2286
2287 agc2_integr = stv0900_blind_check_agc2_min_level(i_params, demod);
2288
2289 if (agc2_integr > STV0900_BLIND_SEARCH_AGC2_TH) {
2290 lock = FALSE;
2291
2292 } else {
2293 switch (demod) {
2294 case STV0900_DEMOD_1:
2295 default:
2296 if (i_params->chip_id == 0x10)
2297 stv0900_write_reg(i_params, R0900_P1_CORRELEXP, 0xAA);
2298
2299 if (i_params->chip_id < 0x20)
2300 stv0900_write_reg(i_params, R0900_P1_CARHDR, 0x55);
2301
2302 stv0900_write_reg(i_params, R0900_P1_CARCFG, 0xC4);
2303 stv0900_write_reg(i_params, R0900_P1_RTCS2, 0x44);
2304
2305 if (i_params->chip_id >= 0x20) {
2306 stv0900_write_reg(i_params, R0900_P1_EQUALCFG, 0x41);
2307 stv0900_write_reg(i_params, R0900_P1_FFECFG, 0x41);
2308 stv0900_write_reg(i_params, R0900_P1_VITSCALE, 0x82);
2309 stv0900_write_reg(i_params, R0900_P1_VAVSRVIT, 0x0);
2310 }
2311
2312 kref_tmg_reg = R0900_P1_KREFTMG;
2313 break;
2314 case STV0900_DEMOD_2:
2315 if (i_params->chip_id == 0x10)
2316 stv0900_write_reg(i_params, R0900_P2_CORRELEXP, 0xAA);
2317
2318 if (i_params->chip_id < 0x20)
2319 stv0900_write_reg(i_params, R0900_P2_CARHDR, 0x55);
2320
2321 stv0900_write_reg(i_params, R0900_P2_CARCFG, 0xC4);
2322 stv0900_write_reg(i_params, R0900_P2_RTCS2, 0x44);
2323
2324 if (i_params->chip_id >= 0x20) {
2325 stv0900_write_reg(i_params, R0900_P2_EQUALCFG, 0x41);
2326 stv0900_write_reg(i_params, R0900_P2_FFECFG, 0x41);
2327 stv0900_write_reg(i_params, R0900_P2_VITSCALE, 0x82);
2328 stv0900_write_reg(i_params, R0900_P2_VAVSRVIT, 0x0);
2329 }
2330
2331 kref_tmg_reg = R0900_P2_KREFTMG;
2332 break;
2333 }
2334
2335 k_ref_tmg = k_ref_tmg_max;
2336
2337 do {
2338 stv0900_write_reg(i_params, kref_tmg_reg, k_ref_tmg);
2339 if (stv0900_search_srate_coarse(fe) != 0) {
2340 coarse_srate = stv0900_search_srate_fine(fe);
2341
2342 if (coarse_srate != 0) {
2343 stv0900_get_lock_timeout(&demod_timeout, &fec_timeout, coarse_srate, STV0900_BLIND_SEARCH);
2344 lock = stv0900_get_demod_lock(i_params, demod, demod_timeout);
2345 } else
2346 lock = FALSE;
2347 } else {
2348 fail_cpt = 0;
2349 agc2_overflow = 0;
2350
2351 switch (demod) {
2352 case STV0900_DEMOD_1:
2353 default:
2354 for (i = 0; i < 10; i++) {
2355 agc2_integr = (stv0900_read_reg(i_params, R0900_P1_AGC2I1) << 8)
2356 | stv0900_read_reg(i_params, R0900_P1_AGC2I0);
2357
2358 if (agc2_integr >= 0xff00)
2359 agc2_overflow++;
2360
2361 dstatus2 = stv0900_read_reg(i_params, R0900_P1_DSTATUS2);
2362
2363 if (((dstatus2 & 0x1) == 0x1) && ((dstatus2 >> 7) == 1))
2364 fail_cpt++;
2365 }
2366 break;
2367 case STV0900_DEMOD_2:
2368 for (i = 0; i < 10; i++) {
2369 agc2_integr = (stv0900_read_reg(i_params, R0900_P2_AGC2I1) << 8)
2370 | stv0900_read_reg(i_params, R0900_P2_AGC2I0);
2371
2372 if (agc2_integr >= 0xff00)
2373 agc2_overflow++;
2374
2375 dstatus2 = stv0900_read_reg(i_params, R0900_P2_DSTATUS2);
2376
2377 if (((dstatus2 & 0x1) == 0x1) && ((dstatus2 >> 7) == 1))
2378 fail_cpt++;
2379 }
2380 break;
2381 }
2382
2383 if ((fail_cpt > 7) || (agc2_overflow > 7))
2384 coarse_fail = TRUE;
2385
2386 lock = FALSE;
2387 }
2388 k_ref_tmg -= 30;
2389 } while ((k_ref_tmg >= k_ref_tmg_min) && (lock == FALSE) && (coarse_fail == FALSE));
2390 }
2391
2392 return lock;
2393 }
2394
2395 static void stv0900_set_viterbi_acq(struct stv0900_internal *i_params,
2396 enum fe_stv0900_demod_num demod)
2397 {
2398 s32 vth_reg;
2399
2400 dprintk(KERN_INFO "%s\n", __func__);
2401
2402 dmd_reg(vth_reg, R0900_P1_VTH12, R0900_P2_VTH12);
2403
2404 stv0900_write_reg(i_params, vth_reg++, 0x96);
2405 stv0900_write_reg(i_params, vth_reg++, 0x64);
2406 stv0900_write_reg(i_params, vth_reg++, 0x36);
2407 stv0900_write_reg(i_params, vth_reg++, 0x23);
2408 stv0900_write_reg(i_params, vth_reg++, 0x1E);
2409 stv0900_write_reg(i_params, vth_reg++, 0x19);
2410 }
2411
2412 static void stv0900_set_search_standard(struct stv0900_internal *i_params,
2413 enum fe_stv0900_demod_num demod)
2414 {
2415
2416 int sstndrd;
2417
2418 dprintk(KERN_INFO "%s\n", __func__);
2419
2420 sstndrd = i_params->dmd1_srch_standard;
2421 if (demod == 1)
2422 sstndrd = i_params->dmd2_srch_stndrd;
2423
2424 switch (sstndrd) {
2425 case STV0900_SEARCH_DVBS1:
2426 dprintk("Search Standard = DVBS1\n");
2427 break;
2428 case STV0900_SEARCH_DSS:
2429 dprintk("Search Standard = DSS\n");
2430 case STV0900_SEARCH_DVBS2:
2431 break;
2432 dprintk("Search Standard = DVBS2\n");
2433 case STV0900_AUTO_SEARCH:
2434 default:
2435 dprintk("Search Standard = AUTO\n");
2436 break;
2437 }
2438
2439 switch (demod) {
2440 case STV0900_DEMOD_1:
2441 default:
2442 switch (i_params->dmd1_srch_standard) {
2443 case STV0900_SEARCH_DVBS1:
2444 case STV0900_SEARCH_DSS:
2445 stv0900_write_bits(i_params, F0900_P1_DVBS1_ENABLE, 1);
2446 stv0900_write_bits(i_params, F0900_P1_DVBS2_ENABLE, 0);
2447
2448 stv0900_write_bits(i_params, F0900_STOP_CLKVIT1, 0);
2449 stv0900_write_reg(i_params, R0900_P1_ACLC, 0x1a);
2450 stv0900_write_reg(i_params, R0900_P1_BCLC, 0x09);
2451 stv0900_write_reg(i_params, R0900_P1_CAR2CFG, 0x22);
2452
2453 stv0900_set_viterbi_acq(i_params, demod);
2454 stv0900_set_viterbi_standard(i_params,
2455 i_params->dmd1_srch_standard,
2456 i_params->dmd1_fec, demod);
2457
2458 break;
2459 case STV0900_SEARCH_DVBS2:
2460 stv0900_write_bits(i_params, F0900_P1_DVBS1_ENABLE, 0);
2461 stv0900_write_bits(i_params, F0900_P1_DVBS2_ENABLE, 0);
2462 stv0900_write_bits(i_params, F0900_P1_DVBS1_ENABLE, 1);
2463 stv0900_write_bits(i_params, F0900_P1_DVBS2_ENABLE, 1);
2464 stv0900_write_bits(i_params, F0900_STOP_CLKVIT1, 1);
2465 stv0900_write_reg(i_params, R0900_P1_ACLC, 0x1a);
2466 stv0900_write_reg(i_params, R0900_P1_BCLC, 0x09);
2467 stv0900_write_reg(i_params, R0900_P1_CAR2CFG, 0x26);
2468 if (i_params->demod_mode != STV0900_SINGLE) {
2469 if (i_params->chip_id <= 0x11)
2470 stv0900_stop_all_s2_modcod(i_params, demod);
2471 else
2472 stv0900_activate_s2_modcode(i_params, demod);
2473
2474 } else
2475 stv0900_activate_s2_modcode_single(i_params, demod);
2476
2477 stv0900_set_viterbi_tracq(i_params, demod);
2478
2479 break;
2480 case STV0900_AUTO_SEARCH:
2481 default:
2482 stv0900_write_bits(i_params, F0900_P1_DVBS1_ENABLE, 0);
2483 stv0900_write_bits(i_params, F0900_P1_DVBS2_ENABLE, 0);
2484 stv0900_write_bits(i_params, F0900_P1_DVBS1_ENABLE, 1);
2485 stv0900_write_bits(i_params, F0900_P1_DVBS2_ENABLE, 1);
2486 stv0900_write_bits(i_params, F0900_STOP_CLKVIT1, 0);
2487 stv0900_write_reg(i_params, R0900_P1_ACLC, 0x1a);
2488 stv0900_write_reg(i_params, R0900_P1_BCLC, 0x09);
2489 stv0900_write_reg(i_params, R0900_P1_CAR2CFG, 0x26);
2490 if (i_params->demod_mode != STV0900_SINGLE) {
2491 if (i_params->chip_id <= 0x11)
2492 stv0900_stop_all_s2_modcod(i_params, demod);
2493 else
2494 stv0900_activate_s2_modcode(i_params, demod);
2495
2496 } else
2497 stv0900_activate_s2_modcode_single(i_params, demod);
2498
2499 if (i_params->dmd1_symbol_rate >= 2000000)
2500 stv0900_set_viterbi_acq(i_params, demod);
2501 else
2502 stv0900_set_viterbi_tracq(i_params, demod);
2503
2504 stv0900_set_viterbi_standard(i_params, i_params->dmd1_srch_standard, i_params->dmd1_fec, demod);
2505
2506 break;
2507 }
2508 break;
2509 case STV0900_DEMOD_2:
2510 switch (i_params->dmd2_srch_stndrd) {
2511 case STV0900_SEARCH_DVBS1:
2512 case STV0900_SEARCH_DSS:
2513 stv0900_write_bits(i_params, F0900_P2_DVBS1_ENABLE, 1);
2514 stv0900_write_bits(i_params, F0900_P2_DVBS2_ENABLE, 0);
2515 stv0900_write_bits(i_params, F0900_STOP_CLKVIT2, 0);
2516 stv0900_write_reg(i_params, R0900_P2_ACLC, 0x1a);
2517 stv0900_write_reg(i_params, R0900_P2_BCLC, 0x09);
2518 stv0900_write_reg(i_params, R0900_P2_CAR2CFG, 0x22);
2519 stv0900_set_viterbi_acq(i_params, demod);
2520 stv0900_set_viterbi_standard(i_params, i_params->dmd2_srch_stndrd, i_params->dmd2_fec, demod);
2521 break;
2522 case STV0900_SEARCH_DVBS2:
2523 stv0900_write_bits(i_params, F0900_P2_DVBS1_ENABLE, 0);
2524 stv0900_write_bits(i_params, F0900_P2_DVBS2_ENABLE, 0);
2525 stv0900_write_bits(i_params, F0900_P2_DVBS1_ENABLE, 1);
2526 stv0900_write_bits(i_params, F0900_P2_DVBS2_ENABLE, 1);
2527 stv0900_write_bits(i_params, F0900_STOP_CLKVIT2, 1);
2528 stv0900_write_reg(i_params, R0900_P2_ACLC, 0x1a);
2529 stv0900_write_reg(i_params, R0900_P2_BCLC, 0x09);
2530 stv0900_write_reg(i_params, R0900_P2_CAR2CFG, 0x26);
2531 if (i_params->demod_mode != STV0900_SINGLE)
2532 stv0900_activate_s2_modcode(i_params, demod);
2533 else
2534 stv0900_activate_s2_modcode_single(i_params, demod);
2535
2536 stv0900_set_viterbi_tracq(i_params, demod);
2537 break;
2538 case STV0900_AUTO_SEARCH:
2539 default:
2540 stv0900_write_bits(i_params, F0900_P2_DVBS1_ENABLE, 0);
2541 stv0900_write_bits(i_params, F0900_P2_DVBS2_ENABLE, 0);
2542 stv0900_write_bits(i_params, F0900_P2_DVBS1_ENABLE, 1);
2543 stv0900_write_bits(i_params, F0900_P2_DVBS2_ENABLE, 1);
2544 stv0900_write_bits(i_params, F0900_STOP_CLKVIT2, 0);
2545 stv0900_write_reg(i_params, R0900_P2_ACLC, 0x1a);
2546 stv0900_write_reg(i_params, R0900_P2_BCLC, 0x09);
2547 stv0900_write_reg(i_params, R0900_P2_CAR2CFG, 0x26);
2548 if (i_params->demod_mode != STV0900_SINGLE)
2549 stv0900_activate_s2_modcode(i_params, demod);
2550 else
2551 stv0900_activate_s2_modcode_single(i_params, demod);
2552
2553 if (i_params->dmd2_symbol_rate >= 2000000)
2554 stv0900_set_viterbi_acq(i_params, demod);
2555 else
2556 stv0900_set_viterbi_tracq(i_params, demod);
2557
2558 stv0900_set_viterbi_standard(i_params, i_params->dmd2_srch_stndrd, i_params->dmd2_fec, demod);
2559
2560 break;
2561 }
2562
2563 break;
2564 }
2565 }
2566
2567 enum fe_stv0900_signal_type stv0900_algo(struct dvb_frontend *fe)
2568 {
2569 struct stv0900_state *state = fe->demodulator_priv;
2570 struct stv0900_internal *i_params = state->internal;
2571 enum fe_stv0900_demod_num demod = state->demod;
2572
2573 s32 demod_timeout = 500, fec_timeout = 50, stream_merger_field;
2574
2575 int lock = FALSE, low_sr = FALSE;
2576
2577 enum fe_stv0900_signal_type signal_type = STV0900_NOCARRIER;
2578 enum fe_stv0900_search_algo algo;
2579 int no_signal = FALSE;
2580
2581 dprintk(KERN_INFO "%s\n", __func__);
2582
2583 switch (demod) {
2584 case STV0900_DEMOD_1:
2585 default:
2586 algo = i_params->dmd1_srch_algo;
2587
2588 stv0900_write_bits(i_params, F0900_P1_RST_HWARE, 1);
2589 stream_merger_field = F0900_P1_RST_HWARE;
2590
2591 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x5C);
2592
2593 if (i_params->chip_id >= 0x20)
2594 stv0900_write_reg(i_params, R0900_P1_CORRELABS, 0x9e);
2595 else
2596 stv0900_write_reg(i_params, R0900_P1_CORRELABS, 0x88);
2597
2598 stv0900_get_lock_timeout(&demod_timeout, &fec_timeout, i_params->dmd1_symbol_rate, i_params->dmd1_srch_algo);
2599
2600 if (i_params->dmd1_srch_algo == STV0900_BLIND_SEARCH) {
2601 i_params->tuner1_bw = 2 * 36000000;
2602
2603 stv0900_write_reg(i_params, R0900_P1_TMGCFG2, 0x00);
2604 stv0900_write_reg(i_params, R0900_P1_CORRELMANT, 0x70);
2605
2606 stv0900_set_symbol_rate(i_params, i_params->mclk, 1000000, demod);
2607 } else {
2608 stv0900_write_reg(i_params, R0900_P1_DMDT0M, 0x20);
2609 stv0900_write_reg(i_params, R0900_P1_TMGCFG, 0xd2);
2610
2611 if (i_params->dmd1_symbol_rate < 2000000)
2612 stv0900_write_reg(i_params, R0900_P1_CORRELMANT, 0x63);
2613 else
2614 stv0900_write_reg(i_params, R0900_P1_CORRELMANT, 0x70);
2615
2616 stv0900_write_reg(i_params, R0900_P1_AGC2REF, 0x38);
2617 if (i_params->chip_id >= 0x20) {
2618 stv0900_write_reg(i_params, R0900_P1_KREFTMG, 0x5a);
2619
2620 if (i_params->dmd1_srch_algo == STV0900_COLD_START)
2621 i_params->tuner1_bw = (15 * (stv0900_carrier_width(i_params->dmd1_symbol_rate, i_params->rolloff) + 10000000)) / 10;
2622 else if (i_params->dmd1_srch_algo == STV0900_WARM_START)
2623 i_params->tuner1_bw = stv0900_carrier_width(i_params->dmd1_symbol_rate, i_params->rolloff) + 10000000;
2624 } else {
2625 stv0900_write_reg(i_params, R0900_P1_KREFTMG, 0xc1);
2626 i_params->tuner1_bw = (15 * (stv0900_carrier_width(i_params->dmd1_symbol_rate, i_params->rolloff) + 10000000)) / 10;
2627 }
2628
2629 stv0900_write_reg(i_params, R0900_P1_TMGCFG2, 0x01);
2630
2631 stv0900_set_symbol_rate(i_params, i_params->mclk, i_params->dmd1_symbol_rate, demod);
2632 stv0900_set_max_symbol_rate(i_params, i_params->mclk, i_params->dmd1_symbol_rate, demod);
2633 stv0900_set_min_symbol_rate(i_params, i_params->mclk, i_params->dmd1_symbol_rate, demod);
2634 if (i_params->dmd1_symbol_rate >= 10000000)
2635 low_sr = FALSE;
2636 else
2637 low_sr = TRUE;
2638
2639 }
2640
2641 stv0900_set_tuner(fe, i_params->tuner1_freq, i_params->tuner1_bw);
2642
2643 stv0900_write_bits(i_params, F0900_P1_SPECINV_CONTROL, i_params->dmd1_srch_iq_inv);
2644 stv0900_write_bits(i_params, F0900_P1_MANUAL_ROLLOFF, 1);
2645
2646 stv0900_set_search_standard(i_params, demod);
2647
2648 if (i_params->dmd1_srch_algo != STV0900_BLIND_SEARCH)
2649 stv0900_start_search(i_params, demod);
2650 break;
2651 case STV0900_DEMOD_2:
2652 algo = i_params->dmd2_srch_algo;
2653
2654 stv0900_write_bits(i_params, F0900_P2_RST_HWARE, 1);
2655
2656 stream_merger_field = F0900_P2_RST_HWARE;
2657
2658 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x5C);
2659
2660 if (i_params->chip_id >= 0x20)
2661 stv0900_write_reg(i_params, R0900_P2_CORRELABS, 0x9e);
2662 else
2663 stv0900_write_reg(i_params, R0900_P2_CORRELABS, 0x88);
2664
2665 stv0900_get_lock_timeout(&demod_timeout, &fec_timeout, i_params->dmd2_symbol_rate, i_params->dmd2_srch_algo);
2666
2667 if (i_params->dmd2_srch_algo == STV0900_BLIND_SEARCH) {
2668 i_params->tuner2_bw = 2 * 36000000;
2669
2670 stv0900_write_reg(i_params, R0900_P2_TMGCFG2, 0x00);
2671 stv0900_write_reg(i_params, R0900_P2_CORRELMANT, 0x70);
2672
2673 stv0900_set_symbol_rate(i_params, i_params->mclk, 1000000, demod);
2674 } else {
2675 stv0900_write_reg(i_params, R0900_P2_DMDT0M, 0x20);
2676 stv0900_write_reg(i_params, R0900_P2_TMGCFG, 0xd2);
2677
2678 if (i_params->dmd2_symbol_rate < 2000000)
2679 stv0900_write_reg(i_params, R0900_P2_CORRELMANT, 0x63);
2680 else
2681 stv0900_write_reg(i_params, R0900_P2_CORRELMANT, 0x70);
2682
2683 if (i_params->dmd2_symbol_rate >= 10000000)
2684 stv0900_write_reg(i_params, R0900_P2_AGC2REF, 0x38);
2685 else
2686 stv0900_write_reg(i_params, R0900_P2_AGC2REF, 0x60);
2687
2688 if (i_params->chip_id >= 0x20) {
2689 stv0900_write_reg(i_params, R0900_P2_KREFTMG, 0x5a);
2690
2691 if (i_params->dmd2_srch_algo == STV0900_COLD_START)
2692 i_params->tuner2_bw = (15 * (stv0900_carrier_width(i_params->dmd2_symbol_rate,
2693 i_params->rolloff) + 10000000)) / 10;
2694 else if (i_params->dmd2_srch_algo == STV0900_WARM_START)
2695 i_params->tuner2_bw = stv0900_carrier_width(i_params->dmd2_symbol_rate,
2696 i_params->rolloff) + 10000000;
2697 } else {
2698 stv0900_write_reg(i_params, R0900_P2_KREFTMG, 0xc1);
2699 i_params->tuner2_bw = (15 * (stv0900_carrier_width(i_params->dmd2_symbol_rate,
2700 i_params->rolloff) + 10000000)) / 10;
2701 }
2702
2703 stv0900_write_reg(i_params, R0900_P2_TMGCFG2, 0x01);
2704
2705 stv0900_set_symbol_rate(i_params, i_params->mclk, i_params->dmd2_symbol_rate, demod);
2706 stv0900_set_max_symbol_rate(i_params, i_params->mclk, i_params->dmd2_symbol_rate, demod);
2707 stv0900_set_min_symbol_rate(i_params, i_params->mclk, i_params->dmd2_symbol_rate, demod);
2708 if (i_params->dmd2_symbol_rate >= 10000000)
2709 low_sr = FALSE;
2710 else
2711 low_sr = TRUE;
2712
2713 }
2714
2715 stv0900_set_tuner(fe, i_params->tuner2_freq, i_params->tuner2_bw);
2716
2717 stv0900_write_bits(i_params, F0900_P2_SPECINV_CONTROL, i_params->dmd2_srch_iq_inv);
2718 stv0900_write_bits(i_params, F0900_P2_MANUAL_ROLLOFF, 1);
2719
2720 stv0900_set_search_standard(i_params, demod);
2721
2722 if (i_params->dmd2_srch_algo != STV0900_BLIND_SEARCH)
2723 stv0900_start_search(i_params, demod);
2724 break;
2725 }
2726
2727 if (i_params->chip_id == 0x12) {
2728 stv0900_write_bits(i_params, stream_merger_field, 0);
2729 msleep(3);
2730 stv0900_write_bits(i_params, stream_merger_field, 1);
2731 stv0900_write_bits(i_params, stream_merger_field, 0);
2732 }
2733
2734 if (algo == STV0900_BLIND_SEARCH)
2735 lock = stv0900_blind_search_algo(fe);
2736 else if (algo == STV0900_COLD_START)
2737 lock = stv0900_get_demod_cold_lock(fe, demod_timeout);
2738 else if (algo == STV0900_WARM_START)
2739 lock = stv0900_get_demod_lock(i_params, demod, demod_timeout);
2740
2741 if ((lock == FALSE) && (algo == STV0900_COLD_START)) {
2742 if (low_sr == FALSE) {
2743 if (stv0900_check_timing_lock(i_params, demod) == TRUE)
2744 lock = stv0900_sw_algo(i_params, demod);
2745 }
2746 }
2747
2748 if (lock == TRUE)
2749 signal_type = stv0900_get_signal_params(fe);
2750
2751 if ((lock == TRUE) && (signal_type == STV0900_RANGEOK)) {
2752 stv0900_track_optimization(fe);
2753 if (i_params->chip_id <= 0x11) {
2754 if ((stv0900_get_standard(fe, STV0900_DEMOD_1) == STV0900_DVBS1_STANDARD) && (stv0900_get_standard(fe, STV0900_DEMOD_2) == STV0900_DVBS1_STANDARD)) {
2755 msleep(20);
2756 stv0900_write_bits(i_params, stream_merger_field, 0);
2757 } else {
2758 stv0900_write_bits(i_params, stream_merger_field, 0);
2759 msleep(3);
2760 stv0900_write_bits(i_params, stream_merger_field, 1);
2761 stv0900_write_bits(i_params, stream_merger_field, 0);
2762 }
2763 } else if (i_params->chip_id == 0x20) {
2764 stv0900_write_bits(i_params, stream_merger_field, 0);
2765 msleep(3);
2766 stv0900_write_bits(i_params, stream_merger_field, 1);
2767 stv0900_write_bits(i_params, stream_merger_field, 0);
2768 }
2769
2770 if (stv0900_wait_for_lock(i_params, demod, fec_timeout, fec_timeout) == TRUE) {
2771 lock = TRUE;
2772 switch (demod) {
2773 case STV0900_DEMOD_1:
2774 default:
2775 i_params->dmd1_rslts.locked = TRUE;
2776 if (i_params->dmd1_rslts.standard == STV0900_DVBS2_STANDARD) {
2777 stv0900_set_dvbs2_rolloff(i_params, demod);
2778 stv0900_write_reg(i_params, R0900_P1_PDELCTRL2, 0x40);
2779 stv0900_write_reg(i_params, R0900_P1_PDELCTRL2, 0);
2780 stv0900_write_reg(i_params, R0900_P1_ERRCTRL1, 0x67);
2781 } else {
2782 stv0900_write_reg(i_params, R0900_P1_ERRCTRL1, 0x75);
2783 }
2784
2785 stv0900_write_reg(i_params, R0900_P1_FBERCPT4, 0);
2786 stv0900_write_reg(i_params, R0900_P1_ERRCTRL2, 0xc1);
2787 break;
2788 case STV0900_DEMOD_2:
2789 i_params->dmd2_rslts.locked = TRUE;
2790
2791 if (i_params->dmd2_rslts.standard == STV0900_DVBS2_STANDARD) {
2792 stv0900_set_dvbs2_rolloff(i_params, demod);
2793 stv0900_write_reg(i_params, R0900_P2_PDELCTRL2, 0x60);
2794 stv0900_write_reg(i_params, R0900_P2_PDELCTRL2, 0x20);
2795 stv0900_write_reg(i_params, R0900_P2_ERRCTRL1, 0x67);
2796 } else {
2797 stv0900_write_reg(i_params, R0900_P2_ERRCTRL1, 0x75);
2798 }
2799
2800 stv0900_write_reg(i_params, R0900_P2_FBERCPT4, 0);
2801
2802 stv0900_write_reg(i_params, R0900_P2_ERRCTRL2, 0xc1);
2803 break;
2804 }
2805 } else {
2806 lock = FALSE;
2807 signal_type = STV0900_NODATA;
2808 no_signal = stv0900_check_signal_presence(i_params, demod);
2809
2810 switch (demod) {
2811 case STV0900_DEMOD_1:
2812 default:
2813 i_params->dmd1_rslts.locked = FALSE;
2814 break;
2815 case STV0900_DEMOD_2:
2816 i_params->dmd2_rslts.locked = FALSE;
2817 break;
2818 }
2819 }
2820 }
2821
2822 if ((signal_type == STV0900_NODATA) && (no_signal == FALSE)) {
2823 switch (demod) {
2824 case STV0900_DEMOD_1:
2825 default:
2826 if (i_params->chip_id <= 0x11) {
2827 if ((stv0900_get_bits(i_params, F0900_P1_HEADER_MODE) == STV0900_DVBS_FOUND) &&
2828 (i_params->dmd1_srch_iq_inv <= STV0900_IQ_AUTO_NORMAL_FIRST))
2829 signal_type = stv0900_dvbs1_acq_workaround(fe);
2830 } else
2831 i_params->dmd1_rslts.locked = FALSE;
2832
2833 break;
2834 case STV0900_DEMOD_2:
2835 if (i_params->chip_id <= 0x11) {
2836 if ((stv0900_get_bits(i_params, F0900_P2_HEADER_MODE) == STV0900_DVBS_FOUND) &&
2837 (i_params->dmd2_srch_iq_inv <= STV0900_IQ_AUTO_NORMAL_FIRST))
2838 signal_type = stv0900_dvbs1_acq_workaround(fe);
2839 } else
2840 i_params->dmd2_rslts.locked = FALSE;
2841 break;
2842 }
2843 }
2844
2845 return signal_type;
2846 }
2847
Linux with added FPC-III support