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Merge branch 'fix/pcm-hwptr' into for-linus
[linux/fpc-iii.git] / drivers / video / omap / lcdc.c
blobab39492566771032148f844d1c51ca3d61a73aa2
1 /*
2 * OMAP1 internal LCD controller
3 *
4 * Copyright (C) 2004 Nokia Corporation
5 * Author: Imre Deak <imre.deak@nokia.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21 #include <linux/module.h>
22 #include <linux/device.h>
23 #include <linux/interrupt.h>
24 #include <linux/spinlock.h>
25 #include <linux/err.h>
26 #include <linux/mm.h>
27 #include <linux/fb.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/vmalloc.h>
30 #include <linux/clk.h>
31
32 #include <mach/dma.h>
33 #include <mach/omapfb.h>
34
35 #include <asm/mach-types.h>
36
37 #include "lcdc.h"
38
39 #define MODULE_NAME "lcdc"
40
41 #define OMAP_LCDC_BASE 0xfffec000
42 #define OMAP_LCDC_SIZE 256
43 #define OMAP_LCDC_IRQ INT_LCD_CTRL
44
45 #define OMAP_LCDC_CONTROL (OMAP_LCDC_BASE + 0x00)
46 #define OMAP_LCDC_TIMING0 (OMAP_LCDC_BASE + 0x04)
47 #define OMAP_LCDC_TIMING1 (OMAP_LCDC_BASE + 0x08)
48 #define OMAP_LCDC_TIMING2 (OMAP_LCDC_BASE + 0x0c)
49 #define OMAP_LCDC_STATUS (OMAP_LCDC_BASE + 0x10)
50 #define OMAP_LCDC_SUBPANEL (OMAP_LCDC_BASE + 0x14)
51 #define OMAP_LCDC_LINE_INT (OMAP_LCDC_BASE + 0x18)
52 #define OMAP_LCDC_DISPLAY_STATUS (OMAP_LCDC_BASE + 0x1c)
53
54 #define OMAP_LCDC_STAT_DONE (1 << 0)
55 #define OMAP_LCDC_STAT_VSYNC (1 << 1)
56 #define OMAP_LCDC_STAT_SYNC_LOST (1 << 2)
57 #define OMAP_LCDC_STAT_ABC (1 << 3)
58 #define OMAP_LCDC_STAT_LINE_INT (1 << 4)
59 #define OMAP_LCDC_STAT_FUF (1 << 5)
60 #define OMAP_LCDC_STAT_LOADED_PALETTE (1 << 6)
61
62 #define OMAP_LCDC_CTRL_LCD_EN (1 << 0)
63 #define OMAP_LCDC_CTRL_LCD_TFT (1 << 7)
64 #define OMAP_LCDC_CTRL_LINE_IRQ_CLR_SEL (1 << 10)
65
66 #define OMAP_LCDC_IRQ_VSYNC (1 << 2)
67 #define OMAP_LCDC_IRQ_DONE (1 << 3)
68 #define OMAP_LCDC_IRQ_LOADED_PALETTE (1 << 4)
69 #define OMAP_LCDC_IRQ_LINE_NIRQ (1 << 5)
70 #define OMAP_LCDC_IRQ_LINE (1 << 6)
71 #define OMAP_LCDC_IRQ_MASK (((1 << 5) - 1) << 2)
72
73 #define MAX_PALETTE_SIZE PAGE_SIZE
74
75 enum lcdc_load_mode {
76 OMAP_LCDC_LOAD_PALETTE,
77 OMAP_LCDC_LOAD_FRAME,
78 OMAP_LCDC_LOAD_PALETTE_AND_FRAME
79 };
80
81 static struct omap_lcd_controller {
82 enum omapfb_update_mode update_mode;
83 int ext_mode;
84
85 unsigned long frame_offset;
86 int screen_width;
87 int xres;
88 int yres;
89
90 enum omapfb_color_format color_mode;
91 int bpp;
92 void *palette_virt;
93 dma_addr_t palette_phys;
94 int palette_code;
95 int palette_size;
96
97 unsigned int irq_mask;
98 struct completion last_frame_complete;
99 struct completion palette_load_complete;
100 struct clk *lcd_ck;
101 struct omapfb_device *fbdev;
102
103 void (*dma_callback)(void *data);
104 void *dma_callback_data;
105
106 int fbmem_allocated;
107 dma_addr_t vram_phys;
108 void *vram_virt;
109 unsigned long vram_size;
110 } lcdc;
111
112 static void inline enable_irqs(int mask)
113 {
114 lcdc.irq_mask |= mask;
115 }
116
117 static void inline disable_irqs(int mask)
118 {
119 lcdc.irq_mask &= ~mask;
120 }
121
122 static void set_load_mode(enum lcdc_load_mode mode)
123 {
124 u32 l;
125
126 l = omap_readl(OMAP_LCDC_CONTROL);
127 l &= ~(3 << 20);
128 switch (mode) {
129 case OMAP_LCDC_LOAD_PALETTE:
130 l |= 1 << 20;
131 break;
132 case OMAP_LCDC_LOAD_FRAME:
133 l |= 2 << 20;
134 break;
135 case OMAP_LCDC_LOAD_PALETTE_AND_FRAME:
136 break;
137 default:
138 BUG();
139 }
140 omap_writel(l, OMAP_LCDC_CONTROL);
141 }
142
143 static void enable_controller(void)
144 {
145 u32 l;
146
147 l = omap_readl(OMAP_LCDC_CONTROL);
148 l |= OMAP_LCDC_CTRL_LCD_EN;
149 l &= ~OMAP_LCDC_IRQ_MASK;
150 l |= lcdc.irq_mask | OMAP_LCDC_IRQ_DONE; /* enabled IRQs */
151 omap_writel(l, OMAP_LCDC_CONTROL);
152 }
153
154 static void disable_controller_async(void)
155 {
156 u32 l;
157 u32 mask;
158
159 l = omap_readl(OMAP_LCDC_CONTROL);
160 mask = OMAP_LCDC_CTRL_LCD_EN | OMAP_LCDC_IRQ_MASK;
161 /*
162 * Preserve the DONE mask, since we still want to get the
163 * final DONE irq. It will be disabled in the IRQ handler.
164 */
165 mask &= ~OMAP_LCDC_IRQ_DONE;
166 l &= ~mask;
167 omap_writel(l, OMAP_LCDC_CONTROL);
168 }
169
170 static void disable_controller(void)
171 {
172 init_completion(&lcdc.last_frame_complete);
173 disable_controller_async();
174 if (!wait_for_completion_timeout(&lcdc.last_frame_complete,
175 msecs_to_jiffies(500)))
176 dev_err(lcdc.fbdev->dev, "timeout waiting for FRAME DONE\n");
177 }
178
179 static void reset_controller(u32 status)
180 {
181 static unsigned long reset_count;
182 static unsigned long last_jiffies;
183
184 disable_controller_async();
185 reset_count++;
186 if (reset_count == 1 || time_after(jiffies, last_jiffies + HZ)) {
187 dev_err(lcdc.fbdev->dev,
188 "resetting (status %#010x,reset count %lu)\n",
189 status, reset_count);
190 last_jiffies = jiffies;
191 }
192 if (reset_count < 100) {
193 enable_controller();
194 } else {
195 reset_count = 0;
196 dev_err(lcdc.fbdev->dev,
197 "too many reset attempts, giving up.\n");
198 }
199 }
200
201 /*
202 * Configure the LCD DMA according to the current mode specified by parameters
203 * in lcdc.fbdev and fbdev->var.
204 */
205 static void setup_lcd_dma(void)
206 {
207 static const int dma_elem_type[] = {
208 0,
209 OMAP_DMA_DATA_TYPE_S8,
210 OMAP_DMA_DATA_TYPE_S16,
211 0,
212 OMAP_DMA_DATA_TYPE_S32,
213 };
214 struct omapfb_plane_struct *plane = lcdc.fbdev->fb_info[0]->par;
215 struct fb_var_screeninfo *var = &lcdc.fbdev->fb_info[0]->var;
216 unsigned long src;
217 int esize, xelem, yelem;
218
219 src = lcdc.vram_phys + lcdc.frame_offset;
220
221 switch (var->rotate) {
222 case 0:
223 if (plane->info.mirror || (src & 3) ||
224 lcdc.color_mode == OMAPFB_COLOR_YUV420 ||
225 (lcdc.xres & 1))
226 esize = 2;
227 else
228 esize = 4;
229 xelem = lcdc.xres * lcdc.bpp / 8 / esize;
230 yelem = lcdc.yres;
231 break;
232 case 90:
233 case 180:
234 case 270:
235 if (cpu_is_omap15xx()) {
236 BUG();
237 }
238 esize = 2;
239 xelem = lcdc.yres * lcdc.bpp / 16;
240 yelem = lcdc.xres;
241 break;
242 default:
243 BUG();
244 return;
245 }
246 #ifdef VERBOSE
247 dev_dbg(lcdc.fbdev->dev,
248 "setup_dma: src %#010lx esize %d xelem %d yelem %d\n",
249 src, esize, xelem, yelem);
250 #endif
251 omap_set_lcd_dma_b1(src, xelem, yelem, dma_elem_type[esize]);
252 if (!cpu_is_omap15xx()) {
253 int bpp = lcdc.bpp;
254
255 /*
256 * YUV support is only for external mode when we have the
257 * YUV window embedded in a 16bpp frame buffer.
258 */
259 if (lcdc.color_mode == OMAPFB_COLOR_YUV420)
260 bpp = 16;
261 /* Set virtual xres elem size */
262 omap_set_lcd_dma_b1_vxres(
263 lcdc.screen_width * bpp / 8 / esize);
264 /* Setup transformations */
265 omap_set_lcd_dma_b1_rotation(var->rotate);
266 omap_set_lcd_dma_b1_mirror(plane->info.mirror);
267 }
268 omap_setup_lcd_dma();
269 }
270
271 static irqreturn_t lcdc_irq_handler(int irq, void *dev_id)
272 {
273 u32 status;
274
275 status = omap_readl(OMAP_LCDC_STATUS);
276
277 if (status & (OMAP_LCDC_STAT_FUF | OMAP_LCDC_STAT_SYNC_LOST))
278 reset_controller(status);
279 else {
280 if (status & OMAP_LCDC_STAT_DONE) {
281 u32 l;
282
283 /*
284 * Disable IRQ_DONE. The status bit will be cleared
285 * only when the controller is reenabled and we don't
286 * want to get more interrupts.
287 */
288 l = omap_readl(OMAP_LCDC_CONTROL);
289 l &= ~OMAP_LCDC_IRQ_DONE;
290 omap_writel(l, OMAP_LCDC_CONTROL);
291 complete(&lcdc.last_frame_complete);
292 }
293 if (status & OMAP_LCDC_STAT_LOADED_PALETTE) {
294 disable_controller_async();
295 complete(&lcdc.palette_load_complete);
296 }
297 }
298
299 /*
300 * Clear these interrupt status bits.
301 * Sync_lost, FUF bits were cleared by disabling the LCD controller
302 * LOADED_PALETTE can be cleared this way only in palette only
303 * load mode. In other load modes it's cleared by disabling the
304 * controller.
305 */
306 status &= ~(OMAP_LCDC_STAT_VSYNC |
307 OMAP_LCDC_STAT_LOADED_PALETTE |
308 OMAP_LCDC_STAT_ABC |
309 OMAP_LCDC_STAT_LINE_INT);
310 omap_writel(status, OMAP_LCDC_STATUS);
311 return IRQ_HANDLED;
312 }
313
314 /*
315 * Change to a new video mode. We defer this to a later time to avoid any
316 * flicker and not to mess up the current LCD DMA context. For this we disable
317 * the LCD controller, which will generate a DONE irq after the last frame has
318 * been transferred. Then it'll be safe to reconfigure both the LCD controller
319 * as well as the LCD DMA.
320 */
321 static int omap_lcdc_setup_plane(int plane, int channel_out,
322 unsigned long offset, int screen_width,
323 int pos_x, int pos_y, int width, int height,
324 int color_mode)
325 {
326 struct fb_var_screeninfo *var = &lcdc.fbdev->fb_info[0]->var;
327 struct lcd_panel *panel = lcdc.fbdev->panel;
328 int rot_x, rot_y;
329
330 if (var->rotate == 0) {
331 rot_x = panel->x_res;
332 rot_y = panel->y_res;
333 } else {
334 rot_x = panel->y_res;
335 rot_y = panel->x_res;
336 }
337 if (plane != 0 || channel_out != 0 || pos_x != 0 || pos_y != 0 ||
338 width > rot_x || height > rot_y) {
339 #ifdef VERBOSE
340 dev_dbg(lcdc.fbdev->dev,
341 "invalid plane params plane %d pos_x %d pos_y %d "
342 "w %d h %d\n", plane, pos_x, pos_y, width, height);
343 #endif
344 return -EINVAL;
345 }
346
347 lcdc.frame_offset = offset;
348 lcdc.xres = width;
349 lcdc.yres = height;
350 lcdc.screen_width = screen_width;
351 lcdc.color_mode = color_mode;
352
353 switch (color_mode) {
354 case OMAPFB_COLOR_CLUT_8BPP:
355 lcdc.bpp = 8;
356 lcdc.palette_code = 0x3000;
357 lcdc.palette_size = 512;
358 break;
359 case OMAPFB_COLOR_RGB565:
360 lcdc.bpp = 16;
361 lcdc.palette_code = 0x4000;
362 lcdc.palette_size = 32;
363 break;
364 case OMAPFB_COLOR_RGB444:
365 lcdc.bpp = 16;
366 lcdc.palette_code = 0x4000;
367 lcdc.palette_size = 32;
368 break;
369 case OMAPFB_COLOR_YUV420:
370 if (lcdc.ext_mode) {
371 lcdc.bpp = 12;
372 break;
373 }
374 /* fallthrough */
375 case OMAPFB_COLOR_YUV422:
376 if (lcdc.ext_mode) {
377 lcdc.bpp = 16;
378 break;
379 }
380 /* fallthrough */
381 default:
382 /* FIXME: other BPPs.
383 * bpp1: code 0, size 256
384 * bpp2: code 0x1000 size 256
385 * bpp4: code 0x2000 size 256
386 * bpp12: code 0x4000 size 32
387 */
388 dev_dbg(lcdc.fbdev->dev, "invalid color mode %d\n", color_mode);
389 BUG();
390 return -1;
391 }
392
393 if (lcdc.ext_mode) {
394 setup_lcd_dma();
395 return 0;
396 }
397
398 if (lcdc.update_mode == OMAPFB_AUTO_UPDATE) {
399 disable_controller();
400 omap_stop_lcd_dma();
401 setup_lcd_dma();
402 enable_controller();
403 }
404
405 return 0;
406 }
407
408 static int omap_lcdc_enable_plane(int plane, int enable)
409 {
410 dev_dbg(lcdc.fbdev->dev,
411 "plane %d enable %d update_mode %d ext_mode %d\n",
412 plane, enable, lcdc.update_mode, lcdc.ext_mode);
413 if (plane != OMAPFB_PLANE_GFX)
414 return -EINVAL;
415
416 return 0;
417 }
418
419 /*
420 * Configure the LCD DMA for a palette load operation and do the palette
421 * downloading synchronously. We don't use the frame+palette load mode of
422 * the controller, since the palette can always be downloaded seperately.
423 */
424 static void load_palette(void)
425 {
426 u16 *palette;
427
428 palette = (u16 *)lcdc.palette_virt;
429
430 *(u16 *)palette &= 0x0fff;
431 *(u16 *)palette |= lcdc.palette_code;
432
433 omap_set_lcd_dma_b1(lcdc.palette_phys,
434 lcdc.palette_size / 4 + 1, 1, OMAP_DMA_DATA_TYPE_S32);
435
436 omap_set_lcd_dma_single_transfer(1);
437 omap_setup_lcd_dma();
438
439 init_completion(&lcdc.palette_load_complete);
440 enable_irqs(OMAP_LCDC_IRQ_LOADED_PALETTE);
441 set_load_mode(OMAP_LCDC_LOAD_PALETTE);
442 enable_controller();
443 if (!wait_for_completion_timeout(&lcdc.palette_load_complete,
444 msecs_to_jiffies(500)))
445 dev_err(lcdc.fbdev->dev, "timeout waiting for FRAME DONE\n");
446 /* The controller gets disabled in the irq handler */
447 disable_irqs(OMAP_LCDC_IRQ_LOADED_PALETTE);
448 omap_stop_lcd_dma();
449
450 omap_set_lcd_dma_single_transfer(lcdc.ext_mode);
451 }
452
453 /* Used only in internal controller mode */
454 static int omap_lcdc_setcolreg(u_int regno, u16 red, u16 green, u16 blue,
455 u16 transp, int update_hw_pal)
456 {
457 u16 *palette;
458
459 if (lcdc.color_mode != OMAPFB_COLOR_CLUT_8BPP || regno > 255)
460 return -EINVAL;
461
462 palette = (u16 *)lcdc.palette_virt;
463
464 palette[regno] &= ~0x0fff;
465 palette[regno] |= ((red >> 12) << 8) | ((green >> 12) << 4 ) |
466 (blue >> 12);
467
468 if (update_hw_pal) {
469 disable_controller();
470 omap_stop_lcd_dma();
471 load_palette();
472 setup_lcd_dma();
473 set_load_mode(OMAP_LCDC_LOAD_FRAME);
474 enable_controller();
475 }
476
477 return 0;
478 }
479
480 static void calc_ck_div(int is_tft, int pck, int *pck_div)
481 {
482 unsigned long lck;
483
484 pck = max(1, pck);
485 lck = clk_get_rate(lcdc.lcd_ck);
486 *pck_div = (lck + pck - 1) / pck;
487 if (is_tft)
488 *pck_div = max(2, *pck_div);
489 else
490 *pck_div = max(3, *pck_div);
491 if (*pck_div > 255) {
492 /* FIXME: try to adjust logic clock divider as well */
493 *pck_div = 255;
494 dev_warn(lcdc.fbdev->dev, "pixclock %d kHz too low.\n",
495 pck / 1000);
496 }
497 }
498
499 static void inline setup_regs(void)
500 {
501 u32 l;
502 struct lcd_panel *panel = lcdc.fbdev->panel;
503 int is_tft = panel->config & OMAP_LCDC_PANEL_TFT;
504 unsigned long lck;
505 int pcd;
506
507 l = omap_readl(OMAP_LCDC_CONTROL);
508 l &= ~OMAP_LCDC_CTRL_LCD_TFT;
509 l |= is_tft ? OMAP_LCDC_CTRL_LCD_TFT : 0;
510 #ifdef CONFIG_MACH_OMAP_PALMTE
511 /* FIXME:if (machine_is_omap_palmte()) { */
512 /* PalmTE uses alternate TFT setting in 8BPP mode */
513 l |= (is_tft && panel->bpp == 8) ? 0x810000 : 0;
514 /* } */
515 #endif
516 omap_writel(l, OMAP_LCDC_CONTROL);
517
518 l = omap_readl(OMAP_LCDC_TIMING2);
519 l &= ~(((1 << 6) - 1) << 20);
520 l |= (panel->config & OMAP_LCDC_SIGNAL_MASK) << 20;
521 omap_writel(l, OMAP_LCDC_TIMING2);
522
523 l = panel->x_res - 1;
524 l |= (panel->hsw - 1) << 10;
525 l |= (panel->hfp - 1) << 16;
526 l |= (panel->hbp - 1) << 24;
527 omap_writel(l, OMAP_LCDC_TIMING0);
528
529 l = panel->y_res - 1;
530 l |= (panel->vsw - 1) << 10;
531 l |= panel->vfp << 16;
532 l |= panel->vbp << 24;
533 omap_writel(l, OMAP_LCDC_TIMING1);
534
535 l = omap_readl(OMAP_LCDC_TIMING2);
536 l &= ~0xff;
537
538 lck = clk_get_rate(lcdc.lcd_ck);
539
540 if (!panel->pcd)
541 calc_ck_div(is_tft, panel->pixel_clock * 1000, &pcd);
542 else {
543 dev_warn(lcdc.fbdev->dev,
544 "Pixel clock divider value is obsolete.\n"
545 "Try to set pixel_clock to %lu and pcd to 0 "
546 "in drivers/video/omap/lcd_%s.c and submit a patch.\n",
547 lck / panel->pcd / 1000, panel->name);
548
549 pcd = panel->pcd;
550 }
551 l |= pcd & 0xff;
552 l |= panel->acb << 8;
553 omap_writel(l, OMAP_LCDC_TIMING2);
554
555 /* update panel info with the exact clock */
556 panel->pixel_clock = lck / pcd / 1000;
557 }
558
559 /*
560 * Configure the LCD controller, download the color palette and start a looped
561 * DMA transfer of the frame image data. Called only in internal
562 * controller mode.
563 */
564 static int omap_lcdc_set_update_mode(enum omapfb_update_mode mode)
565 {
566 int r = 0;
567
568 if (mode != lcdc.update_mode) {
569 switch (mode) {
570 case OMAPFB_AUTO_UPDATE:
571 setup_regs();
572 load_palette();
573
574 /* Setup and start LCD DMA */
575 setup_lcd_dma();
576
577 set_load_mode(OMAP_LCDC_LOAD_FRAME);
578 enable_irqs(OMAP_LCDC_IRQ_DONE);
579 /* This will start the actual DMA transfer */
580 enable_controller();
581 lcdc.update_mode = mode;
582 break;
583 case OMAPFB_UPDATE_DISABLED:
584 disable_controller();
585 omap_stop_lcd_dma();
586 lcdc.update_mode = mode;
587 break;
588 default:
589 r = -EINVAL;
590 }
591 }
592
593 return r;
594 }
595
596 static enum omapfb_update_mode omap_lcdc_get_update_mode(void)
597 {
598 return lcdc.update_mode;
599 }
600
601 /* PM code called only in internal controller mode */
602 static void omap_lcdc_suspend(void)
603 {
604 if (lcdc.update_mode == OMAPFB_AUTO_UPDATE) {
605 disable_controller();
606 omap_stop_lcd_dma();
607 }
608 }
609
610 static void omap_lcdc_resume(void)
611 {
612 if (lcdc.update_mode == OMAPFB_AUTO_UPDATE) {
613 setup_regs();
614 load_palette();
615 setup_lcd_dma();
616 set_load_mode(OMAP_LCDC_LOAD_FRAME);
617 enable_irqs(OMAP_LCDC_IRQ_DONE);
618 enable_controller();
619 }
620 }
621
622 static void omap_lcdc_get_caps(int plane, struct omapfb_caps *caps)
623 {
624 return;
625 }
626
627 int omap_lcdc_set_dma_callback(void (*callback)(void *data), void *data)
628 {
629 BUG_ON(callback == NULL);
630
631 if (lcdc.dma_callback)
632 return -EBUSY;
633 else {
634 lcdc.dma_callback = callback;
635 lcdc.dma_callback_data = data;
636 }
637 return 0;
638 }
639 EXPORT_SYMBOL(omap_lcdc_set_dma_callback);
640
641 void omap_lcdc_free_dma_callback(void)
642 {
643 lcdc.dma_callback = NULL;
644 }
645 EXPORT_SYMBOL(omap_lcdc_free_dma_callback);
646
647 static void lcdc_dma_handler(u16 status, void *data)
648 {
649 if (lcdc.dma_callback)
650 lcdc.dma_callback(lcdc.dma_callback_data);
651 }
652
653 static int mmap_kern(void)
654 {
655 struct vm_struct *kvma;
656 struct vm_area_struct vma;
657 pgprot_t pgprot;
658 unsigned long vaddr;
659
660 kvma = get_vm_area(lcdc.vram_size, VM_IOREMAP);
661 if (kvma == NULL) {
662 dev_err(lcdc.fbdev->dev, "can't get kernel vm area\n");
663 return -ENOMEM;
664 }
665 vma.vm_mm = &init_mm;
666
667 vaddr = (unsigned long)kvma->addr;
668 vma.vm_start = vaddr;
669 vma.vm_end = vaddr + lcdc.vram_size;
670
671 pgprot = pgprot_writecombine(pgprot_kernel);
672 if (io_remap_pfn_range(&vma, vaddr,
673 lcdc.vram_phys >> PAGE_SHIFT,
674 lcdc.vram_size, pgprot) < 0) {
675 dev_err(lcdc.fbdev->dev, "kernel mmap for FB memory failed\n");
676 return -EAGAIN;
677 }
678
679 lcdc.vram_virt = (void *)vaddr;
680
681 return 0;
682 }
683
684 static void unmap_kern(void)
685 {
686 vunmap(lcdc.vram_virt);
687 }
688
689 static int alloc_palette_ram(void)
690 {
691 lcdc.palette_virt = dma_alloc_writecombine(lcdc.fbdev->dev,
692 MAX_PALETTE_SIZE, &lcdc.palette_phys, GFP_KERNEL);
693 if (lcdc.palette_virt == NULL) {
694 dev_err(lcdc.fbdev->dev, "failed to alloc palette memory\n");
695 return -ENOMEM;
696 }
697 memset(lcdc.palette_virt, 0, MAX_PALETTE_SIZE);
698
699 return 0;
700 }
701
702 static void free_palette_ram(void)
703 {
704 dma_free_writecombine(lcdc.fbdev->dev, MAX_PALETTE_SIZE,
705 lcdc.palette_virt, lcdc.palette_phys);
706 }
707
708 static int alloc_fbmem(struct omapfb_mem_region *region)
709 {
710 int bpp;
711 int frame_size;
712 struct lcd_panel *panel = lcdc.fbdev->panel;
713
714 bpp = panel->bpp;
715 if (bpp == 12)
716 bpp = 16;
717 frame_size = PAGE_ALIGN(panel->x_res * bpp / 8 * panel->y_res);
718 if (region->size > frame_size)
719 frame_size = region->size;
720 lcdc.vram_size = frame_size;
721 lcdc.vram_virt = dma_alloc_writecombine(lcdc.fbdev->dev,
722 lcdc.vram_size, &lcdc.vram_phys, GFP_KERNEL);
723 if (lcdc.vram_virt == NULL) {
724 dev_err(lcdc.fbdev->dev, "unable to allocate FB DMA memory\n");
725 return -ENOMEM;
726 }
727 region->size = frame_size;
728 region->paddr = lcdc.vram_phys;
729 region->vaddr = lcdc.vram_virt;
730 region->alloc = 1;
731
732 memset(lcdc.vram_virt, 0, lcdc.vram_size);
733
734 return 0;
735 }
736
737 static void free_fbmem(void)
738 {
739 dma_free_writecombine(lcdc.fbdev->dev, lcdc.vram_size,
740 lcdc.vram_virt, lcdc.vram_phys);
741 }
742
743 static int setup_fbmem(struct omapfb_mem_desc *req_md)
744 {
745 int r;
746
747 if (!req_md->region_cnt) {
748 dev_err(lcdc.fbdev->dev, "no memory regions defined\n");
749 return -EINVAL;
750 }
751
752 if (req_md->region_cnt > 1) {
753 dev_err(lcdc.fbdev->dev, "only one plane is supported\n");
754 req_md->region_cnt = 1;
755 }
756
757 if (req_md->region[0].paddr == 0) {
758 lcdc.fbmem_allocated = 1;
759 if ((r = alloc_fbmem(&req_md->region[0])) < 0)
760 return r;
761 return 0;
762 }
763
764 lcdc.vram_phys = req_md->region[0].paddr;
765 lcdc.vram_size = req_md->region[0].size;
766
767 if ((r = mmap_kern()) < 0)
768 return r;
769
770 dev_dbg(lcdc.fbdev->dev, "vram at %08x size %08lx mapped to 0x%p\n",
771 lcdc.vram_phys, lcdc.vram_size, lcdc.vram_virt);
772
773 return 0;
774 }
775
776 static void cleanup_fbmem(void)
777 {
778 if (lcdc.fbmem_allocated)
779 free_fbmem();
780 else
781 unmap_kern();
782 }
783
784 static int omap_lcdc_init(struct omapfb_device *fbdev, int ext_mode,
785 struct omapfb_mem_desc *req_vram)
786 {
787 int r;
788 u32 l;
789 int rate;
790 struct clk *tc_ck;
791
792 lcdc.irq_mask = 0;
793
794 lcdc.fbdev = fbdev;
795 lcdc.ext_mode = ext_mode;
796
797 l = 0;
798 omap_writel(l, OMAP_LCDC_CONTROL);
799
800 /* FIXME:
801 * According to errata some platforms have a clock rate limitiation
802 */
803 lcdc.lcd_ck = clk_get(fbdev->dev, "lcd_ck");
804 if (IS_ERR(lcdc.lcd_ck)) {
805 dev_err(fbdev->dev, "unable to access LCD clock\n");
806 r = PTR_ERR(lcdc.lcd_ck);
807 goto fail0;
808 }
809
810 tc_ck = clk_get(fbdev->dev, "tc_ck");
811 if (IS_ERR(tc_ck)) {
812 dev_err(fbdev->dev, "unable to access TC clock\n");
813 r = PTR_ERR(tc_ck);
814 goto fail1;
815 }
816
817 rate = clk_get_rate(tc_ck);
818 clk_put(tc_ck);
819
820 if (machine_is_ams_delta())
821 rate /= 4;
822 if (machine_is_omap_h3())
823 rate /= 3;
824 r = clk_set_rate(lcdc.lcd_ck, rate);
825 if (r) {
826 dev_err(fbdev->dev, "failed to adjust LCD rate\n");
827 goto fail1;
828 }
829 clk_enable(lcdc.lcd_ck);
830
831 r = request_irq(OMAP_LCDC_IRQ, lcdc_irq_handler, 0, MODULE_NAME, fbdev);
832 if (r) {
833 dev_err(fbdev->dev, "unable to get IRQ\n");
834 goto fail2;
835 }
836
837 r = omap_request_lcd_dma(lcdc_dma_handler, NULL);
838 if (r) {
839 dev_err(fbdev->dev, "unable to get LCD DMA\n");
840 goto fail3;
841 }
842
843 omap_set_lcd_dma_single_transfer(ext_mode);
844 omap_set_lcd_dma_ext_controller(ext_mode);
845
846 if (!ext_mode)
847 if ((r = alloc_palette_ram()) < 0)
848 goto fail4;
849
850 if ((r = setup_fbmem(req_vram)) < 0)
851 goto fail5;
852
853 pr_info("omapfb: LCDC initialized\n");
854
855 return 0;
856 fail5:
857 if (!ext_mode)
858 free_palette_ram();
859 fail4:
860 omap_free_lcd_dma();
861 fail3:
862 free_irq(OMAP_LCDC_IRQ, lcdc.fbdev);
863 fail2:
864 clk_disable(lcdc.lcd_ck);
865 fail1:
866 clk_put(lcdc.lcd_ck);
867 fail0:
868 return r;
869 }
870
871 static void omap_lcdc_cleanup(void)
872 {
873 if (!lcdc.ext_mode)
874 free_palette_ram();
875 cleanup_fbmem();
876 omap_free_lcd_dma();
877 free_irq(OMAP_LCDC_IRQ, lcdc.fbdev);
878 clk_disable(lcdc.lcd_ck);
879 clk_put(lcdc.lcd_ck);
880 }
881
882 const struct lcd_ctrl omap1_int_ctrl = {
883 .name = "internal",
884 .init = omap_lcdc_init,
885 .cleanup = omap_lcdc_cleanup,
886 .get_caps = omap_lcdc_get_caps,
887 .set_update_mode = omap_lcdc_set_update_mode,
888 .get_update_mode = omap_lcdc_get_update_mode,
889 .update_window = NULL,
890 .suspend = omap_lcdc_suspend,
891 .resume = omap_lcdc_resume,
892 .setup_plane = omap_lcdc_setup_plane,
893 .enable_plane = omap_lcdc_enable_plane,
894 .setcolreg = omap_lcdc_setcolreg,
895 };
Linux with added FPC-III support