?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Merge tag 'ceph-for-4.13-rc8' of git://github.com/ceph/ceph-client
[linux/fpc-iii.git] / drivers / pinctrl / nomadik / pinctrl-nomadik.c
blobd318ca0554894930fc205c75040dc7b826167515
1 /*
2 * Generic GPIO driver for logic cells found in the Nomadik SoC
3 *
4 * Copyright (C) 2008,2009 STMicroelectronics
5 * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it>
6 * Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com>
7 * Copyright (C) 2011-2013 Linus Walleij <linus.walleij@linaro.org>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13 #include <linux/kernel.h>
14 #include <linux/init.h>
15 #include <linux/device.h>
16 #include <linux/platform_device.h>
17 #include <linux/io.h>
18 #include <linux/clk.h>
19 #include <linux/err.h>
20 #include <linux/gpio.h>
21 #include <linux/spinlock.h>
22 #include <linux/interrupt.h>
23 #include <linux/slab.h>
24 #include <linux/of_device.h>
25 #include <linux/of_address.h>
26 #include <linux/bitops.h>
27 #include <linux/pinctrl/machine.h>
28 #include <linux/pinctrl/pinctrl.h>
29 #include <linux/pinctrl/pinmux.h>
30 #include <linux/pinctrl/pinconf.h>
31 /* Since we request GPIOs from ourself */
32 #include <linux/pinctrl/consumer.h>
33 #include "pinctrl-nomadik.h"
34 #include "../core.h"
35 #include "../pinctrl-utils.h"
36
37 /*
38 * The GPIO module in the Nomadik family of Systems-on-Chip is an
39 * AMBA device, managing 32 pins and alternate functions. The logic block
40 * is currently used in the Nomadik and ux500.
41 *
42 * Symbols in this file are called "nmk_gpio" for "nomadik gpio"
43 */
44
45 /*
46 * pin configurations are represented by 32-bit integers:
47 *
48 * bit 0.. 8 - Pin Number (512 Pins Maximum)
49 * bit 9..10 - Alternate Function Selection
50 * bit 11..12 - Pull up/down state
51 * bit 13 - Sleep mode behaviour
52 * bit 14 - Direction
53 * bit 15 - Value (if output)
54 * bit 16..18 - SLPM pull up/down state
55 * bit 19..20 - SLPM direction
56 * bit 21..22 - SLPM Value (if output)
57 * bit 23..25 - PDIS value (if input)
58 * bit 26 - Gpio mode
59 * bit 27 - Sleep mode
60 *
61 * to facilitate the definition, the following macros are provided
62 *
63 * PIN_CFG_DEFAULT - default config (0):
64 * pull up/down = disabled
65 * sleep mode = input/wakeup
66 * direction = input
67 * value = low
68 * SLPM direction = same as normal
69 * SLPM pull = same as normal
70 * SLPM value = same as normal
71 *
72 * PIN_CFG - default config with alternate function
73 */
74
75 typedef unsigned long pin_cfg_t;
76
77 #define PIN_NUM_MASK 0x1ff
78 #define PIN_NUM(x) ((x) & PIN_NUM_MASK)
79
80 #define PIN_ALT_SHIFT 9
81 #define PIN_ALT_MASK (0x3 << PIN_ALT_SHIFT)
82 #define PIN_ALT(x) (((x) & PIN_ALT_MASK) >> PIN_ALT_SHIFT)
83 #define PIN_GPIO (NMK_GPIO_ALT_GPIO << PIN_ALT_SHIFT)
84 #define PIN_ALT_A (NMK_GPIO_ALT_A << PIN_ALT_SHIFT)
85 #define PIN_ALT_B (NMK_GPIO_ALT_B << PIN_ALT_SHIFT)
86 #define PIN_ALT_C (NMK_GPIO_ALT_C << PIN_ALT_SHIFT)
87
88 #define PIN_PULL_SHIFT 11
89 #define PIN_PULL_MASK (0x3 << PIN_PULL_SHIFT)
90 #define PIN_PULL(x) (((x) & PIN_PULL_MASK) >> PIN_PULL_SHIFT)
91 #define PIN_PULL_NONE (NMK_GPIO_PULL_NONE << PIN_PULL_SHIFT)
92 #define PIN_PULL_UP (NMK_GPIO_PULL_UP << PIN_PULL_SHIFT)
93 #define PIN_PULL_DOWN (NMK_GPIO_PULL_DOWN << PIN_PULL_SHIFT)
94
95 #define PIN_SLPM_SHIFT 13
96 #define PIN_SLPM_MASK (0x1 << PIN_SLPM_SHIFT)
97 #define PIN_SLPM(x) (((x) & PIN_SLPM_MASK) >> PIN_SLPM_SHIFT)
98 #define PIN_SLPM_MAKE_INPUT (NMK_GPIO_SLPM_INPUT << PIN_SLPM_SHIFT)
99 #define PIN_SLPM_NOCHANGE (NMK_GPIO_SLPM_NOCHANGE << PIN_SLPM_SHIFT)
100 /* These two replace the above in DB8500v2+ */
101 #define PIN_SLPM_WAKEUP_ENABLE (NMK_GPIO_SLPM_WAKEUP_ENABLE << PIN_SLPM_SHIFT)
102 #define PIN_SLPM_WAKEUP_DISABLE (NMK_GPIO_SLPM_WAKEUP_DISABLE << PIN_SLPM_SHIFT)
103 #define PIN_SLPM_USE_MUX_SETTINGS_IN_SLEEP PIN_SLPM_WAKEUP_DISABLE
104
105 #define PIN_SLPM_GPIO PIN_SLPM_WAKEUP_ENABLE /* In SLPM, pin is a gpio */
106 #define PIN_SLPM_ALTFUNC PIN_SLPM_WAKEUP_DISABLE /* In SLPM, pin is altfunc */
107
108 #define PIN_DIR_SHIFT 14
109 #define PIN_DIR_MASK (0x1 << PIN_DIR_SHIFT)
110 #define PIN_DIR(x) (((x) & PIN_DIR_MASK) >> PIN_DIR_SHIFT)
111 #define PIN_DIR_INPUT (0 << PIN_DIR_SHIFT)
112 #define PIN_DIR_OUTPUT (1 << PIN_DIR_SHIFT)
113
114 #define PIN_VAL_SHIFT 15
115 #define PIN_VAL_MASK (0x1 << PIN_VAL_SHIFT)
116 #define PIN_VAL(x) (((x) & PIN_VAL_MASK) >> PIN_VAL_SHIFT)
117 #define PIN_VAL_LOW (0 << PIN_VAL_SHIFT)
118 #define PIN_VAL_HIGH (1 << PIN_VAL_SHIFT)
119
120 #define PIN_SLPM_PULL_SHIFT 16
121 #define PIN_SLPM_PULL_MASK (0x7 << PIN_SLPM_PULL_SHIFT)
122 #define PIN_SLPM_PULL(x) \
123 (((x) & PIN_SLPM_PULL_MASK) >> PIN_SLPM_PULL_SHIFT)
124 #define PIN_SLPM_PULL_NONE \
125 ((1 + NMK_GPIO_PULL_NONE) << PIN_SLPM_PULL_SHIFT)
126 #define PIN_SLPM_PULL_UP \
127 ((1 + NMK_GPIO_PULL_UP) << PIN_SLPM_PULL_SHIFT)
128 #define PIN_SLPM_PULL_DOWN \
129 ((1 + NMK_GPIO_PULL_DOWN) << PIN_SLPM_PULL_SHIFT)
130
131 #define PIN_SLPM_DIR_SHIFT 19
132 #define PIN_SLPM_DIR_MASK (0x3 << PIN_SLPM_DIR_SHIFT)
133 #define PIN_SLPM_DIR(x) \
134 (((x) & PIN_SLPM_DIR_MASK) >> PIN_SLPM_DIR_SHIFT)
135 #define PIN_SLPM_DIR_INPUT ((1 + 0) << PIN_SLPM_DIR_SHIFT)
136 #define PIN_SLPM_DIR_OUTPUT ((1 + 1) << PIN_SLPM_DIR_SHIFT)
137
138 #define PIN_SLPM_VAL_SHIFT 21
139 #define PIN_SLPM_VAL_MASK (0x3 << PIN_SLPM_VAL_SHIFT)
140 #define PIN_SLPM_VAL(x) \
141 (((x) & PIN_SLPM_VAL_MASK) >> PIN_SLPM_VAL_SHIFT)
142 #define PIN_SLPM_VAL_LOW ((1 + 0) << PIN_SLPM_VAL_SHIFT)
143 #define PIN_SLPM_VAL_HIGH ((1 + 1) << PIN_SLPM_VAL_SHIFT)
144
145 #define PIN_SLPM_PDIS_SHIFT 23
146 #define PIN_SLPM_PDIS_MASK (0x3 << PIN_SLPM_PDIS_SHIFT)
147 #define PIN_SLPM_PDIS(x) \
148 (((x) & PIN_SLPM_PDIS_MASK) >> PIN_SLPM_PDIS_SHIFT)
149 #define PIN_SLPM_PDIS_NO_CHANGE (0 << PIN_SLPM_PDIS_SHIFT)
150 #define PIN_SLPM_PDIS_DISABLED (1 << PIN_SLPM_PDIS_SHIFT)
151 #define PIN_SLPM_PDIS_ENABLED (2 << PIN_SLPM_PDIS_SHIFT)
152
153 #define PIN_LOWEMI_SHIFT 25
154 #define PIN_LOWEMI_MASK (0x1 << PIN_LOWEMI_SHIFT)
155 #define PIN_LOWEMI(x) (((x) & PIN_LOWEMI_MASK) >> PIN_LOWEMI_SHIFT)
156 #define PIN_LOWEMI_DISABLED (0 << PIN_LOWEMI_SHIFT)
157 #define PIN_LOWEMI_ENABLED (1 << PIN_LOWEMI_SHIFT)
158
159 #define PIN_GPIOMODE_SHIFT 26
160 #define PIN_GPIOMODE_MASK (0x1 << PIN_GPIOMODE_SHIFT)
161 #define PIN_GPIOMODE(x) (((x) & PIN_GPIOMODE_MASK) >> PIN_GPIOMODE_SHIFT)
162 #define PIN_GPIOMODE_DISABLED (0 << PIN_GPIOMODE_SHIFT)
163 #define PIN_GPIOMODE_ENABLED (1 << PIN_GPIOMODE_SHIFT)
164
165 #define PIN_SLEEPMODE_SHIFT 27
166 #define PIN_SLEEPMODE_MASK (0x1 << PIN_SLEEPMODE_SHIFT)
167 #define PIN_SLEEPMODE(x) (((x) & PIN_SLEEPMODE_MASK) >> PIN_SLEEPMODE_SHIFT)
168 #define PIN_SLEEPMODE_DISABLED (0 << PIN_SLEEPMODE_SHIFT)
169 #define PIN_SLEEPMODE_ENABLED (1 << PIN_SLEEPMODE_SHIFT)
170
171
172 /* Shortcuts. Use these instead of separate DIR, PULL, and VAL. */
173 #define PIN_INPUT_PULLDOWN (PIN_DIR_INPUT | PIN_PULL_DOWN)
174 #define PIN_INPUT_PULLUP (PIN_DIR_INPUT | PIN_PULL_UP)
175 #define PIN_INPUT_NOPULL (PIN_DIR_INPUT | PIN_PULL_NONE)
176 #define PIN_OUTPUT_LOW (PIN_DIR_OUTPUT | PIN_VAL_LOW)
177 #define PIN_OUTPUT_HIGH (PIN_DIR_OUTPUT | PIN_VAL_HIGH)
178
179 #define PIN_SLPM_INPUT_PULLDOWN (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_DOWN)
180 #define PIN_SLPM_INPUT_PULLUP (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_UP)
181 #define PIN_SLPM_INPUT_NOPULL (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_NONE)
182 #define PIN_SLPM_OUTPUT_LOW (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_LOW)
183 #define PIN_SLPM_OUTPUT_HIGH (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_HIGH)
184
185 #define PIN_CFG_DEFAULT (0)
186
187 #define PIN_CFG(num, alt) \
188 (PIN_CFG_DEFAULT |\
189 (PIN_NUM(num) | PIN_##alt))
190
191 #define PIN_CFG_INPUT(num, alt, pull) \
192 (PIN_CFG_DEFAULT |\
193 (PIN_NUM(num) | PIN_##alt | PIN_INPUT_##pull))
194
195 #define PIN_CFG_OUTPUT(num, alt, val) \
196 (PIN_CFG_DEFAULT |\
197 (PIN_NUM(num) | PIN_##alt | PIN_OUTPUT_##val))
198
199 /*
200 * "nmk_gpio" and "NMK_GPIO" stand for "Nomadik GPIO", leaving
201 * the "gpio" namespace for generic and cross-machine functions
202 */
203
204 #define GPIO_BLOCK_SHIFT 5
205 #define NMK_GPIO_PER_CHIP (1 << GPIO_BLOCK_SHIFT)
206 #define NMK_MAX_BANKS DIV_ROUND_UP(ARCH_NR_GPIOS, NMK_GPIO_PER_CHIP)
207
208 /* Register in the logic block */
209 #define NMK_GPIO_DAT 0x00
210 #define NMK_GPIO_DATS 0x04
211 #define NMK_GPIO_DATC 0x08
212 #define NMK_GPIO_PDIS 0x0c
213 #define NMK_GPIO_DIR 0x10
214 #define NMK_GPIO_DIRS 0x14
215 #define NMK_GPIO_DIRC 0x18
216 #define NMK_GPIO_SLPC 0x1c
217 #define NMK_GPIO_AFSLA 0x20
218 #define NMK_GPIO_AFSLB 0x24
219 #define NMK_GPIO_LOWEMI 0x28
220
221 #define NMK_GPIO_RIMSC 0x40
222 #define NMK_GPIO_FIMSC 0x44
223 #define NMK_GPIO_IS 0x48
224 #define NMK_GPIO_IC 0x4c
225 #define NMK_GPIO_RWIMSC 0x50
226 #define NMK_GPIO_FWIMSC 0x54
227 #define NMK_GPIO_WKS 0x58
228 /* These appear in DB8540 and later ASICs */
229 #define NMK_GPIO_EDGELEVEL 0x5C
230 #define NMK_GPIO_LEVEL 0x60
231
232
233 /* Pull up/down values */
234 enum nmk_gpio_pull {
235 NMK_GPIO_PULL_NONE,
236 NMK_GPIO_PULL_UP,
237 NMK_GPIO_PULL_DOWN,
238 };
239
240 /* Sleep mode */
241 enum nmk_gpio_slpm {
242 NMK_GPIO_SLPM_INPUT,
243 NMK_GPIO_SLPM_WAKEUP_ENABLE = NMK_GPIO_SLPM_INPUT,
244 NMK_GPIO_SLPM_NOCHANGE,
245 NMK_GPIO_SLPM_WAKEUP_DISABLE = NMK_GPIO_SLPM_NOCHANGE,
246 };
247
248 struct nmk_gpio_chip {
249 struct gpio_chip chip;
250 struct irq_chip irqchip;
251 void __iomem *addr;
252 struct clk *clk;
253 unsigned int bank;
254 unsigned int parent_irq;
255 int latent_parent_irq;
256 u32 (*get_latent_status)(unsigned int bank);
257 void (*set_ioforce)(bool enable);
258 spinlock_t lock;
259 bool sleepmode;
260 /* Keep track of configured edges */
261 u32 edge_rising;
262 u32 edge_falling;
263 u32 real_wake;
264 u32 rwimsc;
265 u32 fwimsc;
266 u32 rimsc;
267 u32 fimsc;
268 u32 pull_up;
269 u32 lowemi;
270 };
271
272 /**
273 * struct nmk_pinctrl - state container for the Nomadik pin controller
274 * @dev: containing device pointer
275 * @pctl: corresponding pin controller device
276 * @soc: SoC data for this specific chip
277 * @prcm_base: PRCM register range virtual base
278 */
279 struct nmk_pinctrl {
280 struct device *dev;
281 struct pinctrl_dev *pctl;
282 const struct nmk_pinctrl_soc_data *soc;
283 void __iomem *prcm_base;
284 };
285
286 static struct nmk_gpio_chip *nmk_gpio_chips[NMK_MAX_BANKS];
287
288 static DEFINE_SPINLOCK(nmk_gpio_slpm_lock);
289
290 #define NUM_BANKS ARRAY_SIZE(nmk_gpio_chips)
291
292 static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip,
293 unsigned offset, int gpio_mode)
294 {
295 u32 afunc, bfunc;
296
297 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~BIT(offset);
298 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~BIT(offset);
299 if (gpio_mode & NMK_GPIO_ALT_A)
300 afunc |= BIT(offset);
301 if (gpio_mode & NMK_GPIO_ALT_B)
302 bfunc |= BIT(offset);
303 writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA);
304 writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB);
305 }
306
307 static void __nmk_gpio_set_slpm(struct nmk_gpio_chip *nmk_chip,
308 unsigned offset, enum nmk_gpio_slpm mode)
309 {
310 u32 slpm;
311
312 slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC);
313 if (mode == NMK_GPIO_SLPM_NOCHANGE)
314 slpm |= BIT(offset);
315 else
316 slpm &= ~BIT(offset);
317 writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC);
318 }
319
320 static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip,
321 unsigned offset, enum nmk_gpio_pull pull)
322 {
323 u32 pdis;
324
325 pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS);
326 if (pull == NMK_GPIO_PULL_NONE) {
327 pdis |= BIT(offset);
328 nmk_chip->pull_up &= ~BIT(offset);
329 } else {
330 pdis &= ~BIT(offset);
331 }
332
333 writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS);
334
335 if (pull == NMK_GPIO_PULL_UP) {
336 nmk_chip->pull_up |= BIT(offset);
337 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATS);
338 } else if (pull == NMK_GPIO_PULL_DOWN) {
339 nmk_chip->pull_up &= ~BIT(offset);
340 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATC);
341 }
342 }
343
344 static void __nmk_gpio_set_lowemi(struct nmk_gpio_chip *nmk_chip,
345 unsigned offset, bool lowemi)
346 {
347 bool enabled = nmk_chip->lowemi & BIT(offset);
348
349 if (lowemi == enabled)
350 return;
351
352 if (lowemi)
353 nmk_chip->lowemi |= BIT(offset);
354 else
355 nmk_chip->lowemi &= ~BIT(offset);
356
357 writel_relaxed(nmk_chip->lowemi,
358 nmk_chip->addr + NMK_GPIO_LOWEMI);
359 }
360
361 static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip,
362 unsigned offset)
363 {
364 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DIRC);
365 }
366
367 static void __nmk_gpio_set_output(struct nmk_gpio_chip *nmk_chip,
368 unsigned offset, int val)
369 {
370 if (val)
371 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATS);
372 else
373 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATC);
374 }
375
376 static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip,
377 unsigned offset, int val)
378 {
379 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DIRS);
380 __nmk_gpio_set_output(nmk_chip, offset, val);
381 }
382
383 static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip,
384 unsigned offset, int gpio_mode,
385 bool glitch)
386 {
387 u32 rwimsc = nmk_chip->rwimsc;
388 u32 fwimsc = nmk_chip->fwimsc;
389
390 if (glitch && nmk_chip->set_ioforce) {
391 u32 bit = BIT(offset);
392
393 /* Prevent spurious wakeups */
394 writel(rwimsc & ~bit, nmk_chip->addr + NMK_GPIO_RWIMSC);
395 writel(fwimsc & ~bit, nmk_chip->addr + NMK_GPIO_FWIMSC);
396
397 nmk_chip->set_ioforce(true);
398 }
399
400 __nmk_gpio_set_mode(nmk_chip, offset, gpio_mode);
401
402 if (glitch && nmk_chip->set_ioforce) {
403 nmk_chip->set_ioforce(false);
404
405 writel(rwimsc, nmk_chip->addr + NMK_GPIO_RWIMSC);
406 writel(fwimsc, nmk_chip->addr + NMK_GPIO_FWIMSC);
407 }
408 }
409
410 static void
411 nmk_gpio_disable_lazy_irq(struct nmk_gpio_chip *nmk_chip, unsigned offset)
412 {
413 u32 falling = nmk_chip->fimsc & BIT(offset);
414 u32 rising = nmk_chip->rimsc & BIT(offset);
415 int gpio = nmk_chip->chip.base + offset;
416 int irq = irq_find_mapping(nmk_chip->chip.irqdomain, offset);
417 struct irq_data *d = irq_get_irq_data(irq);
418
419 if (!rising && !falling)
420 return;
421
422 if (!d || !irqd_irq_disabled(d))
423 return;
424
425 if (rising) {
426 nmk_chip->rimsc &= ~BIT(offset);
427 writel_relaxed(nmk_chip->rimsc,
428 nmk_chip->addr + NMK_GPIO_RIMSC);
429 }
430
431 if (falling) {
432 nmk_chip->fimsc &= ~BIT(offset);
433 writel_relaxed(nmk_chip->fimsc,
434 nmk_chip->addr + NMK_GPIO_FIMSC);
435 }
436
437 dev_dbg(nmk_chip->chip.parent, "%d: clearing interrupt mask\n", gpio);
438 }
439
440 static void nmk_write_masked(void __iomem *reg, u32 mask, u32 value)
441 {
442 u32 val;
443
444 val = readl(reg);
445 val = ((val & ~mask) | (value & mask));
446 writel(val, reg);
447 }
448
449 static void nmk_prcm_altcx_set_mode(struct nmk_pinctrl *npct,
450 unsigned offset, unsigned alt_num)
451 {
452 int i;
453 u16 reg;
454 u8 bit;
455 u8 alt_index;
456 const struct prcm_gpiocr_altcx_pin_desc *pin_desc;
457 const u16 *gpiocr_regs;
458
459 if (!npct->prcm_base)
460 return;
461
462 if (alt_num > PRCM_IDX_GPIOCR_ALTC_MAX) {
463 dev_err(npct->dev, "PRCM GPIOCR: alternate-C%i is invalid\n",
464 alt_num);
465 return;
466 }
467
468 for (i = 0 ; i < npct->soc->npins_altcx ; i++) {
469 if (npct->soc->altcx_pins[i].pin == offset)
470 break;
471 }
472 if (i == npct->soc->npins_altcx) {
473 dev_dbg(npct->dev, "PRCM GPIOCR: pin %i is not found\n",
474 offset);
475 return;
476 }
477
478 pin_desc = npct->soc->altcx_pins + i;
479 gpiocr_regs = npct->soc->prcm_gpiocr_registers;
480
481 /*
482 * If alt_num is NULL, just clear current ALTCx selection
483 * to make sure we come back to a pure ALTC selection
484 */
485 if (!alt_num) {
486 for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) {
487 if (pin_desc->altcx[i].used == true) {
488 reg = gpiocr_regs[pin_desc->altcx[i].reg_index];
489 bit = pin_desc->altcx[i].control_bit;
490 if (readl(npct->prcm_base + reg) & BIT(bit)) {
491 nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0);
492 dev_dbg(npct->dev,
493 "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n",
494 offset, i+1);
495 }
496 }
497 }
498 return;
499 }
500
501 alt_index = alt_num - 1;
502 if (pin_desc->altcx[alt_index].used == false) {
503 dev_warn(npct->dev,
504 "PRCM GPIOCR: pin %i: alternate-C%i does not exist\n",
505 offset, alt_num);
506 return;
507 }
508
509 /*
510 * Check if any other ALTCx functions are activated on this pin
511 * and disable it first.
512 */
513 for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) {
514 if (i == alt_index)
515 continue;
516 if (pin_desc->altcx[i].used == true) {
517 reg = gpiocr_regs[pin_desc->altcx[i].reg_index];
518 bit = pin_desc->altcx[i].control_bit;
519 if (readl(npct->prcm_base + reg) & BIT(bit)) {
520 nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0);
521 dev_dbg(npct->dev,
522 "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n",
523 offset, i+1);
524 }
525 }
526 }
527
528 reg = gpiocr_regs[pin_desc->altcx[alt_index].reg_index];
529 bit = pin_desc->altcx[alt_index].control_bit;
530 dev_dbg(npct->dev, "PRCM GPIOCR: pin %i: alternate-C%i has been selected\n",
531 offset, alt_index+1);
532 nmk_write_masked(npct->prcm_base + reg, BIT(bit), BIT(bit));
533 }
534
535 /*
536 * Safe sequence used to switch IOs between GPIO and Alternate-C mode:
537 * - Save SLPM registers
538 * - Set SLPM=0 for the IOs you want to switch and others to 1
539 * - Configure the GPIO registers for the IOs that are being switched
540 * - Set IOFORCE=1
541 * - Modify the AFLSA/B registers for the IOs that are being switched
542 * - Set IOFORCE=0
543 * - Restore SLPM registers
544 * - Any spurious wake up event during switch sequence to be ignored and
545 * cleared
546 */
547 static void nmk_gpio_glitch_slpm_init(unsigned int *slpm)
548 {
549 int i;
550
551 for (i = 0; i < NUM_BANKS; i++) {
552 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
553 unsigned int temp = slpm[i];
554
555 if (!chip)
556 break;
557
558 clk_enable(chip->clk);
559
560 slpm[i] = readl(chip->addr + NMK_GPIO_SLPC);
561 writel(temp, chip->addr + NMK_GPIO_SLPC);
562 }
563 }
564
565 static void nmk_gpio_glitch_slpm_restore(unsigned int *slpm)
566 {
567 int i;
568
569 for (i = 0; i < NUM_BANKS; i++) {
570 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
571
572 if (!chip)
573 break;
574
575 writel(slpm[i], chip->addr + NMK_GPIO_SLPC);
576
577 clk_disable(chip->clk);
578 }
579 }
580
581 static int __maybe_unused nmk_prcm_gpiocr_get_mode(struct pinctrl_dev *pctldev, int gpio)
582 {
583 int i;
584 u16 reg;
585 u8 bit;
586 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
587 const struct prcm_gpiocr_altcx_pin_desc *pin_desc;
588 const u16 *gpiocr_regs;
589
590 if (!npct->prcm_base)
591 return NMK_GPIO_ALT_C;
592
593 for (i = 0; i < npct->soc->npins_altcx; i++) {
594 if (npct->soc->altcx_pins[i].pin == gpio)
595 break;
596 }
597 if (i == npct->soc->npins_altcx)
598 return NMK_GPIO_ALT_C;
599
600 pin_desc = npct->soc->altcx_pins + i;
601 gpiocr_regs = npct->soc->prcm_gpiocr_registers;
602 for (i = 0; i < PRCM_IDX_GPIOCR_ALTC_MAX; i++) {
603 if (pin_desc->altcx[i].used == true) {
604 reg = gpiocr_regs[pin_desc->altcx[i].reg_index];
605 bit = pin_desc->altcx[i].control_bit;
606 if (readl(npct->prcm_base + reg) & BIT(bit))
607 return NMK_GPIO_ALT_C+i+1;
608 }
609 }
610 return NMK_GPIO_ALT_C;
611 }
612
613 /* IRQ functions */
614
615 static void nmk_gpio_irq_ack(struct irq_data *d)
616 {
617 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
618 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
619
620 clk_enable(nmk_chip->clk);
621 writel(BIT(d->hwirq), nmk_chip->addr + NMK_GPIO_IC);
622 clk_disable(nmk_chip->clk);
623 }
624
625 enum nmk_gpio_irq_type {
626 NORMAL,
627 WAKE,
628 };
629
630 static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip,
631 int offset, enum nmk_gpio_irq_type which,
632 bool enable)
633 {
634 u32 *rimscval;
635 u32 *fimscval;
636 u32 rimscreg;
637 u32 fimscreg;
638
639 if (which == NORMAL) {
640 rimscreg = NMK_GPIO_RIMSC;
641 fimscreg = NMK_GPIO_FIMSC;
642 rimscval = &nmk_chip->rimsc;
643 fimscval = &nmk_chip->fimsc;
644 } else {
645 rimscreg = NMK_GPIO_RWIMSC;
646 fimscreg = NMK_GPIO_FWIMSC;
647 rimscval = &nmk_chip->rwimsc;
648 fimscval = &nmk_chip->fwimsc;
649 }
650
651 /* we must individually set/clear the two edges */
652 if (nmk_chip->edge_rising & BIT(offset)) {
653 if (enable)
654 *rimscval |= BIT(offset);
655 else
656 *rimscval &= ~BIT(offset);
657 writel(*rimscval, nmk_chip->addr + rimscreg);
658 }
659 if (nmk_chip->edge_falling & BIT(offset)) {
660 if (enable)
661 *fimscval |= BIT(offset);
662 else
663 *fimscval &= ~BIT(offset);
664 writel(*fimscval, nmk_chip->addr + fimscreg);
665 }
666 }
667
668 static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip,
669 int offset, bool on)
670 {
671 /*
672 * Ensure WAKEUP_ENABLE is on. No need to disable it if wakeup is
673 * disabled, since setting SLPM to 1 increases power consumption, and
674 * wakeup is anyhow controlled by the RIMSC and FIMSC registers.
675 */
676 if (nmk_chip->sleepmode && on) {
677 __nmk_gpio_set_slpm(nmk_chip, offset,
678 NMK_GPIO_SLPM_WAKEUP_ENABLE);
679 }
680
681 __nmk_gpio_irq_modify(nmk_chip, offset, WAKE, on);
682 }
683
684 static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable)
685 {
686 struct nmk_gpio_chip *nmk_chip;
687 unsigned long flags;
688
689 nmk_chip = irq_data_get_irq_chip_data(d);
690 if (!nmk_chip)
691 return -EINVAL;
692
693 clk_enable(nmk_chip->clk);
694 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
695 spin_lock(&nmk_chip->lock);
696
697 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, enable);
698
699 if (!(nmk_chip->real_wake & BIT(d->hwirq)))
700 __nmk_gpio_set_wake(nmk_chip, d->hwirq, enable);
701
702 spin_unlock(&nmk_chip->lock);
703 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
704 clk_disable(nmk_chip->clk);
705
706 return 0;
707 }
708
709 static void nmk_gpio_irq_mask(struct irq_data *d)
710 {
711 nmk_gpio_irq_maskunmask(d, false);
712 }
713
714 static void nmk_gpio_irq_unmask(struct irq_data *d)
715 {
716 nmk_gpio_irq_maskunmask(d, true);
717 }
718
719 static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
720 {
721 struct nmk_gpio_chip *nmk_chip;
722 unsigned long flags;
723
724 nmk_chip = irq_data_get_irq_chip_data(d);
725 if (!nmk_chip)
726 return -EINVAL;
727
728 clk_enable(nmk_chip->clk);
729 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
730 spin_lock(&nmk_chip->lock);
731
732 if (irqd_irq_disabled(d))
733 __nmk_gpio_set_wake(nmk_chip, d->hwirq, on);
734
735 if (on)
736 nmk_chip->real_wake |= BIT(d->hwirq);
737 else
738 nmk_chip->real_wake &= ~BIT(d->hwirq);
739
740 spin_unlock(&nmk_chip->lock);
741 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
742 clk_disable(nmk_chip->clk);
743
744 return 0;
745 }
746
747 static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type)
748 {
749 bool enabled = !irqd_irq_disabled(d);
750 bool wake = irqd_is_wakeup_set(d);
751 struct nmk_gpio_chip *nmk_chip;
752 unsigned long flags;
753
754 nmk_chip = irq_data_get_irq_chip_data(d);
755 if (!nmk_chip)
756 return -EINVAL;
757 if (type & IRQ_TYPE_LEVEL_HIGH)
758 return -EINVAL;
759 if (type & IRQ_TYPE_LEVEL_LOW)
760 return -EINVAL;
761
762 clk_enable(nmk_chip->clk);
763 spin_lock_irqsave(&nmk_chip->lock, flags);
764
765 if (enabled)
766 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, false);
767
768 if (enabled || wake)
769 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, false);
770
771 nmk_chip->edge_rising &= ~BIT(d->hwirq);
772 if (type & IRQ_TYPE_EDGE_RISING)
773 nmk_chip->edge_rising |= BIT(d->hwirq);
774
775 nmk_chip->edge_falling &= ~BIT(d->hwirq);
776 if (type & IRQ_TYPE_EDGE_FALLING)
777 nmk_chip->edge_falling |= BIT(d->hwirq);
778
779 if (enabled)
780 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, true);
781
782 if (enabled || wake)
783 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, true);
784
785 spin_unlock_irqrestore(&nmk_chip->lock, flags);
786 clk_disable(nmk_chip->clk);
787
788 return 0;
789 }
790
791 static unsigned int nmk_gpio_irq_startup(struct irq_data *d)
792 {
793 struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d);
794
795 clk_enable(nmk_chip->clk);
796 nmk_gpio_irq_unmask(d);
797 return 0;
798 }
799
800 static void nmk_gpio_irq_shutdown(struct irq_data *d)
801 {
802 struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d);
803
804 nmk_gpio_irq_mask(d);
805 clk_disable(nmk_chip->clk);
806 }
807
808 static void __nmk_gpio_irq_handler(struct irq_desc *desc, u32 status)
809 {
810 struct irq_chip *host_chip = irq_desc_get_chip(desc);
811 struct gpio_chip *chip = irq_desc_get_handler_data(desc);
812
813 chained_irq_enter(host_chip, desc);
814
815 while (status) {
816 int bit = __ffs(status);
817
818 generic_handle_irq(irq_find_mapping(chip->irqdomain, bit));
819 status &= ~BIT(bit);
820 }
821
822 chained_irq_exit(host_chip, desc);
823 }
824
825 static void nmk_gpio_irq_handler(struct irq_desc *desc)
826 {
827 struct gpio_chip *chip = irq_desc_get_handler_data(desc);
828 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
829 u32 status;
830
831 clk_enable(nmk_chip->clk);
832 status = readl(nmk_chip->addr + NMK_GPIO_IS);
833 clk_disable(nmk_chip->clk);
834
835 __nmk_gpio_irq_handler(desc, status);
836 }
837
838 static void nmk_gpio_latent_irq_handler(struct irq_desc *desc)
839 {
840 struct gpio_chip *chip = irq_desc_get_handler_data(desc);
841 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
842 u32 status = nmk_chip->get_latent_status(nmk_chip->bank);
843
844 __nmk_gpio_irq_handler(desc, status);
845 }
846
847 /* I/O Functions */
848
849 static int nmk_gpio_get_dir(struct gpio_chip *chip, unsigned offset)
850 {
851 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
852 int dir;
853
854 clk_enable(nmk_chip->clk);
855
856 dir = !(readl(nmk_chip->addr + NMK_GPIO_DIR) & BIT(offset));
857
858 clk_disable(nmk_chip->clk);
859
860 return dir;
861 }
862
863 static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset)
864 {
865 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
866
867 clk_enable(nmk_chip->clk);
868
869 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DIRC);
870
871 clk_disable(nmk_chip->clk);
872
873 return 0;
874 }
875
876 static int nmk_gpio_get_input(struct gpio_chip *chip, unsigned offset)
877 {
878 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
879 int value;
880
881 clk_enable(nmk_chip->clk);
882
883 value = !!(readl(nmk_chip->addr + NMK_GPIO_DAT) & BIT(offset));
884
885 clk_disable(nmk_chip->clk);
886
887 return value;
888 }
889
890 static void nmk_gpio_set_output(struct gpio_chip *chip, unsigned offset,
891 int val)
892 {
893 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
894
895 clk_enable(nmk_chip->clk);
896
897 __nmk_gpio_set_output(nmk_chip, offset, val);
898
899 clk_disable(nmk_chip->clk);
900 }
901
902 static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset,
903 int val)
904 {
905 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
906
907 clk_enable(nmk_chip->clk);
908
909 __nmk_gpio_make_output(nmk_chip, offset, val);
910
911 clk_disable(nmk_chip->clk);
912
913 return 0;
914 }
915
916 #ifdef CONFIG_DEBUG_FS
917 static int nmk_gpio_get_mode(struct nmk_gpio_chip *nmk_chip, int offset)
918 {
919 u32 afunc, bfunc;
920
921 clk_enable(nmk_chip->clk);
922
923 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & BIT(offset);
924 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & BIT(offset);
925
926 clk_disable(nmk_chip->clk);
927
928 return (afunc ? NMK_GPIO_ALT_A : 0) | (bfunc ? NMK_GPIO_ALT_B : 0);
929 }
930
931 #include <linux/seq_file.h>
932
933 static void nmk_gpio_dbg_show_one(struct seq_file *s,
934 struct pinctrl_dev *pctldev, struct gpio_chip *chip,
935 unsigned offset, unsigned gpio)
936 {
937 const char *label = gpiochip_is_requested(chip, offset);
938 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
939 int mode;
940 bool is_out;
941 bool data_out;
942 bool pull;
943 const char *modes[] = {
944 [NMK_GPIO_ALT_GPIO] = "gpio",
945 [NMK_GPIO_ALT_A] = "altA",
946 [NMK_GPIO_ALT_B] = "altB",
947 [NMK_GPIO_ALT_C] = "altC",
948 [NMK_GPIO_ALT_C+1] = "altC1",
949 [NMK_GPIO_ALT_C+2] = "altC2",
950 [NMK_GPIO_ALT_C+3] = "altC3",
951 [NMK_GPIO_ALT_C+4] = "altC4",
952 };
953 const char *pulls[] = {
954 "none ",
955 "pull down",
956 "pull up ",
957 };
958
959 clk_enable(nmk_chip->clk);
960 is_out = !!(readl(nmk_chip->addr + NMK_GPIO_DIR) & BIT(offset));
961 pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & BIT(offset));
962 data_out = !!(readl(nmk_chip->addr + NMK_GPIO_DAT) & BIT(offset));
963 mode = nmk_gpio_get_mode(nmk_chip, offset);
964 if ((mode == NMK_GPIO_ALT_C) && pctldev)
965 mode = nmk_prcm_gpiocr_get_mode(pctldev, gpio);
966
967 if (is_out) {
968 seq_printf(s, " gpio-%-3d (%-20.20s) out %s %s",
969 gpio,
970 label ?: "(none)",
971 data_out ? "hi" : "lo",
972 (mode < 0) ? "unknown" : modes[mode]);
973 } else {
974 int irq = gpio_to_irq(gpio);
975 struct irq_desc *desc = irq_to_desc(irq);
976 int pullidx = 0;
977 int val;
978
979 if (pull)
980 pullidx = data_out ? 2 : 1;
981
982 seq_printf(s, " gpio-%-3d (%-20.20s) in %s %s",
983 gpio,
984 label ?: "(none)",
985 pulls[pullidx],
986 (mode < 0) ? "unknown" : modes[mode]);
987
988 val = nmk_gpio_get_input(chip, offset);
989 seq_printf(s, " VAL %d", val);
990
991 /*
992 * This races with request_irq(), set_irq_type(),
993 * and set_irq_wake() ... but those are "rare".
994 */
995 if (irq > 0 && desc && desc->action) {
996 char *trigger;
997
998 if (nmk_chip->edge_rising & BIT(offset))
999 trigger = "edge-rising";
1000 else if (nmk_chip->edge_falling & BIT(offset))
1001 trigger = "edge-falling";
1002 else
1003 trigger = "edge-undefined";
1004
1005 seq_printf(s, " irq-%d %s%s",
1006 irq, trigger,
1007 irqd_is_wakeup_set(&desc->irq_data)
1008 ? " wakeup" : "");
1009 }
1010 }
1011 clk_disable(nmk_chip->clk);
1012 }
1013
1014 static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
1015 {
1016 unsigned i;
1017 unsigned gpio = chip->base;
1018
1019 for (i = 0; i < chip->ngpio; i++, gpio++) {
1020 nmk_gpio_dbg_show_one(s, NULL, chip, i, gpio);
1021 seq_printf(s, "\n");
1022 }
1023 }
1024
1025 #else
1026 static inline void nmk_gpio_dbg_show_one(struct seq_file *s,
1027 struct pinctrl_dev *pctldev,
1028 struct gpio_chip *chip,
1029 unsigned offset, unsigned gpio)
1030 {
1031 }
1032 #define nmk_gpio_dbg_show NULL
1033 #endif
1034
1035 /*
1036 * We will allocate memory for the state container using devm* allocators
1037 * binding to the first device reaching this point, it doesn't matter if
1038 * it is the pin controller or GPIO driver. However we need to use the right
1039 * platform device when looking up resources so pay attention to pdev.
1040 */
1041 static struct nmk_gpio_chip *nmk_gpio_populate_chip(struct device_node *np,
1042 struct platform_device *pdev)
1043 {
1044 struct nmk_gpio_chip *nmk_chip;
1045 struct platform_device *gpio_pdev;
1046 struct gpio_chip *chip;
1047 struct resource *res;
1048 struct clk *clk;
1049 void __iomem *base;
1050 u32 id;
1051
1052 gpio_pdev = of_find_device_by_node(np);
1053 if (!gpio_pdev) {
1054 pr_err("populate \"%s\": device not found\n", np->name);
1055 return ERR_PTR(-ENODEV);
1056 }
1057 if (of_property_read_u32(np, "gpio-bank", &id)) {
1058 dev_err(&pdev->dev, "populate: gpio-bank property not found\n");
1059 return ERR_PTR(-EINVAL);
1060 }
1061
1062 /* Already populated? */
1063 nmk_chip = nmk_gpio_chips[id];
1064 if (nmk_chip)
1065 return nmk_chip;
1066
1067 nmk_chip = devm_kzalloc(&pdev->dev, sizeof(*nmk_chip), GFP_KERNEL);
1068 if (!nmk_chip)
1069 return ERR_PTR(-ENOMEM);
1070
1071 nmk_chip->bank = id;
1072 chip = &nmk_chip->chip;
1073 chip->base = id * NMK_GPIO_PER_CHIP;
1074 chip->ngpio = NMK_GPIO_PER_CHIP;
1075 chip->label = dev_name(&gpio_pdev->dev);
1076 chip->parent = &gpio_pdev->dev;
1077
1078 res = platform_get_resource(gpio_pdev, IORESOURCE_MEM, 0);
1079 base = devm_ioremap_resource(&pdev->dev, res);
1080 if (IS_ERR(base))
1081 return base;
1082 nmk_chip->addr = base;
1083
1084 clk = clk_get(&gpio_pdev->dev, NULL);
1085 if (IS_ERR(clk))
1086 return (void *) clk;
1087 clk_prepare(clk);
1088 nmk_chip->clk = clk;
1089
1090 BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips));
1091 nmk_gpio_chips[id] = nmk_chip;
1092 return nmk_chip;
1093 }
1094
1095 static int nmk_gpio_probe(struct platform_device *dev)
1096 {
1097 struct device_node *np = dev->dev.of_node;
1098 struct nmk_gpio_chip *nmk_chip;
1099 struct gpio_chip *chip;
1100 struct irq_chip *irqchip;
1101 int latent_irq;
1102 bool supports_sleepmode;
1103 int irq;
1104 int ret;
1105
1106 nmk_chip = nmk_gpio_populate_chip(np, dev);
1107 if (IS_ERR(nmk_chip)) {
1108 dev_err(&dev->dev, "could not populate nmk chip struct\n");
1109 return PTR_ERR(nmk_chip);
1110 }
1111
1112 supports_sleepmode =
1113 of_property_read_bool(np, "st,supports-sleepmode");
1114
1115 /* Correct platform device ID */
1116 dev->id = nmk_chip->bank;
1117
1118 irq = platform_get_irq(dev, 0);
1119 if (irq < 0)
1120 return irq;
1121
1122 /* It's OK for this IRQ not to be present */
1123 latent_irq = platform_get_irq(dev, 1);
1124
1125 /*
1126 * The virt address in nmk_chip->addr is in the nomadik register space,
1127 * so we can simply convert the resource address, without remapping
1128 */
1129 nmk_chip->parent_irq = irq;
1130 nmk_chip->latent_parent_irq = latent_irq;
1131 nmk_chip->sleepmode = supports_sleepmode;
1132 spin_lock_init(&nmk_chip->lock);
1133
1134 chip = &nmk_chip->chip;
1135 chip->request = gpiochip_generic_request;
1136 chip->free = gpiochip_generic_free;
1137 chip->get_direction = nmk_gpio_get_dir;
1138 chip->direction_input = nmk_gpio_make_input;
1139 chip->get = nmk_gpio_get_input;
1140 chip->direction_output = nmk_gpio_make_output;
1141 chip->set = nmk_gpio_set_output;
1142 chip->dbg_show = nmk_gpio_dbg_show;
1143 chip->can_sleep = false;
1144 chip->owner = THIS_MODULE;
1145
1146 irqchip = &nmk_chip->irqchip;
1147 irqchip->irq_ack = nmk_gpio_irq_ack;
1148 irqchip->irq_mask = nmk_gpio_irq_mask;
1149 irqchip->irq_unmask = nmk_gpio_irq_unmask;
1150 irqchip->irq_set_type = nmk_gpio_irq_set_type;
1151 irqchip->irq_set_wake = nmk_gpio_irq_set_wake;
1152 irqchip->irq_startup = nmk_gpio_irq_startup;
1153 irqchip->irq_shutdown = nmk_gpio_irq_shutdown;
1154 irqchip->flags = IRQCHIP_MASK_ON_SUSPEND;
1155 irqchip->name = kasprintf(GFP_KERNEL, "nmk%u-%u-%u",
1156 dev->id,
1157 chip->base,
1158 chip->base + chip->ngpio - 1);
1159
1160 clk_enable(nmk_chip->clk);
1161 nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI);
1162 clk_disable(nmk_chip->clk);
1163 chip->of_node = np;
1164
1165 ret = gpiochip_add_data(chip, nmk_chip);
1166 if (ret)
1167 return ret;
1168
1169 platform_set_drvdata(dev, nmk_chip);
1170
1171 /*
1172 * Let the generic code handle this edge IRQ, the the chained
1173 * handler will perform the actual work of handling the parent
1174 * interrupt.
1175 */
1176 ret = gpiochip_irqchip_add(chip,
1177 irqchip,
1178 0,
1179 handle_edge_irq,
1180 IRQ_TYPE_NONE);
1181 if (ret) {
1182 dev_err(&dev->dev, "could not add irqchip\n");
1183 gpiochip_remove(&nmk_chip->chip);
1184 return -ENODEV;
1185 }
1186 /* Then register the chain on the parent IRQ */
1187 gpiochip_set_chained_irqchip(chip,
1188 irqchip,
1189 nmk_chip->parent_irq,
1190 nmk_gpio_irq_handler);
1191 if (nmk_chip->latent_parent_irq > 0)
1192 gpiochip_set_chained_irqchip(chip,
1193 irqchip,
1194 nmk_chip->latent_parent_irq,
1195 nmk_gpio_latent_irq_handler);
1196
1197 dev_info(&dev->dev, "at address %p\n", nmk_chip->addr);
1198
1199 return 0;
1200 }
1201
1202 static int nmk_get_groups_cnt(struct pinctrl_dev *pctldev)
1203 {
1204 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1205
1206 return npct->soc->ngroups;
1207 }
1208
1209 static const char *nmk_get_group_name(struct pinctrl_dev *pctldev,
1210 unsigned selector)
1211 {
1212 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1213
1214 return npct->soc->groups[selector].name;
1215 }
1216
1217 static int nmk_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
1218 const unsigned **pins,
1219 unsigned *num_pins)
1220 {
1221 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1222
1223 *pins = npct->soc->groups[selector].pins;
1224 *num_pins = npct->soc->groups[selector].npins;
1225 return 0;
1226 }
1227
1228 static struct nmk_gpio_chip *find_nmk_gpio_from_pin(unsigned pin)
1229 {
1230 int i;
1231 struct nmk_gpio_chip *nmk_gpio;
1232
1233 for(i = 0; i < NMK_MAX_BANKS; i++) {
1234 nmk_gpio = nmk_gpio_chips[i];
1235 if (!nmk_gpio)
1236 continue;
1237 if (pin >= nmk_gpio->chip.base &&
1238 pin < nmk_gpio->chip.base + nmk_gpio->chip.ngpio)
1239 return nmk_gpio;
1240 }
1241 return NULL;
1242 }
1243
1244 static struct gpio_chip *find_gc_from_pin(unsigned pin)
1245 {
1246 struct nmk_gpio_chip *nmk_gpio = find_nmk_gpio_from_pin(pin);
1247
1248 if (nmk_gpio)
1249 return &nmk_gpio->chip;
1250 return NULL;
1251 }
1252
1253 static void nmk_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
1254 unsigned offset)
1255 {
1256 struct gpio_chip *chip = find_gc_from_pin(offset);
1257
1258 if (!chip) {
1259 seq_printf(s, "invalid pin offset");
1260 return;
1261 }
1262 nmk_gpio_dbg_show_one(s, pctldev, chip, offset - chip->base, offset);
1263 }
1264
1265 static int nmk_dt_add_map_mux(struct pinctrl_map **map, unsigned *reserved_maps,
1266 unsigned *num_maps, const char *group,
1267 const char *function)
1268 {
1269 if (*num_maps == *reserved_maps)
1270 return -ENOSPC;
1271
1272 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
1273 (*map)[*num_maps].data.mux.group = group;
1274 (*map)[*num_maps].data.mux.function = function;
1275 (*num_maps)++;
1276
1277 return 0;
1278 }
1279
1280 static int nmk_dt_add_map_configs(struct pinctrl_map **map,
1281 unsigned *reserved_maps,
1282 unsigned *num_maps, const char *group,
1283 unsigned long *configs, unsigned num_configs)
1284 {
1285 unsigned long *dup_configs;
1286
1287 if (*num_maps == *reserved_maps)
1288 return -ENOSPC;
1289
1290 dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs),
1291 GFP_KERNEL);
1292 if (!dup_configs)
1293 return -ENOMEM;
1294
1295 (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_PIN;
1296
1297 (*map)[*num_maps].data.configs.group_or_pin = group;
1298 (*map)[*num_maps].data.configs.configs = dup_configs;
1299 (*map)[*num_maps].data.configs.num_configs = num_configs;
1300 (*num_maps)++;
1301
1302 return 0;
1303 }
1304
1305 #define NMK_CONFIG_PIN(x, y) { .property = x, .config = y, }
1306 #define NMK_CONFIG_PIN_ARRAY(x, y) { .property = x, .choice = y, \
1307 .size = ARRAY_SIZE(y), }
1308
1309 static const unsigned long nmk_pin_input_modes[] = {
1310 PIN_INPUT_NOPULL,
1311 PIN_INPUT_PULLUP,
1312 PIN_INPUT_PULLDOWN,
1313 };
1314
1315 static const unsigned long nmk_pin_output_modes[] = {
1316 PIN_OUTPUT_LOW,
1317 PIN_OUTPUT_HIGH,
1318 PIN_DIR_OUTPUT,
1319 };
1320
1321 static const unsigned long nmk_pin_sleep_modes[] = {
1322 PIN_SLEEPMODE_DISABLED,
1323 PIN_SLEEPMODE_ENABLED,
1324 };
1325
1326 static const unsigned long nmk_pin_sleep_input_modes[] = {
1327 PIN_SLPM_INPUT_NOPULL,
1328 PIN_SLPM_INPUT_PULLUP,
1329 PIN_SLPM_INPUT_PULLDOWN,
1330 PIN_SLPM_DIR_INPUT,
1331 };
1332
1333 static const unsigned long nmk_pin_sleep_output_modes[] = {
1334 PIN_SLPM_OUTPUT_LOW,
1335 PIN_SLPM_OUTPUT_HIGH,
1336 PIN_SLPM_DIR_OUTPUT,
1337 };
1338
1339 static const unsigned long nmk_pin_sleep_wakeup_modes[] = {
1340 PIN_SLPM_WAKEUP_DISABLE,
1341 PIN_SLPM_WAKEUP_ENABLE,
1342 };
1343
1344 static const unsigned long nmk_pin_gpio_modes[] = {
1345 PIN_GPIOMODE_DISABLED,
1346 PIN_GPIOMODE_ENABLED,
1347 };
1348
1349 static const unsigned long nmk_pin_sleep_pdis_modes[] = {
1350 PIN_SLPM_PDIS_DISABLED,
1351 PIN_SLPM_PDIS_ENABLED,
1352 };
1353
1354 struct nmk_cfg_param {
1355 const char *property;
1356 unsigned long config;
1357 const unsigned long *choice;
1358 int size;
1359 };
1360
1361 static const struct nmk_cfg_param nmk_cfg_params[] = {
1362 NMK_CONFIG_PIN_ARRAY("ste,input", nmk_pin_input_modes),
1363 NMK_CONFIG_PIN_ARRAY("ste,output", nmk_pin_output_modes),
1364 NMK_CONFIG_PIN_ARRAY("ste,sleep", nmk_pin_sleep_modes),
1365 NMK_CONFIG_PIN_ARRAY("ste,sleep-input", nmk_pin_sleep_input_modes),
1366 NMK_CONFIG_PIN_ARRAY("ste,sleep-output", nmk_pin_sleep_output_modes),
1367 NMK_CONFIG_PIN_ARRAY("ste,sleep-wakeup", nmk_pin_sleep_wakeup_modes),
1368 NMK_CONFIG_PIN_ARRAY("ste,gpio", nmk_pin_gpio_modes),
1369 NMK_CONFIG_PIN_ARRAY("ste,sleep-pull-disable", nmk_pin_sleep_pdis_modes),
1370 };
1371
1372 static int nmk_dt_pin_config(int index, int val, unsigned long *config)
1373 {
1374 int ret = 0;
1375
1376 if (nmk_cfg_params[index].choice == NULL)
1377 *config = nmk_cfg_params[index].config;
1378 else {
1379 /* test if out of range */
1380 if (val < nmk_cfg_params[index].size) {
1381 *config = nmk_cfg_params[index].config |
1382 nmk_cfg_params[index].choice[val];
1383 }
1384 }
1385 return ret;
1386 }
1387
1388 static const char *nmk_find_pin_name(struct pinctrl_dev *pctldev, const char *pin_name)
1389 {
1390 int i, pin_number;
1391 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1392
1393 if (sscanf((char *)pin_name, "GPIO%d", &pin_number) == 1)
1394 for (i = 0; i < npct->soc->npins; i++)
1395 if (npct->soc->pins[i].number == pin_number)
1396 return npct->soc->pins[i].name;
1397 return NULL;
1398 }
1399
1400 static bool nmk_pinctrl_dt_get_config(struct device_node *np,
1401 unsigned long *configs)
1402 {
1403 bool has_config = 0;
1404 unsigned long cfg = 0;
1405 int i, val, ret;
1406
1407 for (i = 0; i < ARRAY_SIZE(nmk_cfg_params); i++) {
1408 ret = of_property_read_u32(np,
1409 nmk_cfg_params[i].property, &val);
1410 if (ret != -EINVAL) {
1411 if (nmk_dt_pin_config(i, val, &cfg) == 0) {
1412 *configs |= cfg;
1413 has_config = 1;
1414 }
1415 }
1416 }
1417
1418 return has_config;
1419 }
1420
1421 static int nmk_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
1422 struct device_node *np,
1423 struct pinctrl_map **map,
1424 unsigned *reserved_maps,
1425 unsigned *num_maps)
1426 {
1427 int ret;
1428 const char *function = NULL;
1429 unsigned long configs = 0;
1430 bool has_config = 0;
1431 struct property *prop;
1432 struct device_node *np_config;
1433
1434 ret = of_property_read_string(np, "function", &function);
1435 if (ret >= 0) {
1436 const char *group;
1437
1438 ret = of_property_count_strings(np, "groups");
1439 if (ret < 0)
1440 goto exit;
1441
1442 ret = pinctrl_utils_reserve_map(pctldev, map,
1443 reserved_maps,
1444 num_maps, ret);
1445 if (ret < 0)
1446 goto exit;
1447
1448 of_property_for_each_string(np, "groups", prop, group) {
1449 ret = nmk_dt_add_map_mux(map, reserved_maps, num_maps,
1450 group, function);
1451 if (ret < 0)
1452 goto exit;
1453 }
1454 }
1455
1456 has_config = nmk_pinctrl_dt_get_config(np, &configs);
1457 np_config = of_parse_phandle(np, "ste,config", 0);
1458 if (np_config)
1459 has_config |= nmk_pinctrl_dt_get_config(np_config, &configs);
1460 if (has_config) {
1461 const char *gpio_name;
1462 const char *pin;
1463
1464 ret = of_property_count_strings(np, "pins");
1465 if (ret < 0)
1466 goto exit;
1467 ret = pinctrl_utils_reserve_map(pctldev, map,
1468 reserved_maps,
1469 num_maps, ret);
1470 if (ret < 0)
1471 goto exit;
1472
1473 of_property_for_each_string(np, "pins", prop, pin) {
1474 gpio_name = nmk_find_pin_name(pctldev, pin);
1475
1476 ret = nmk_dt_add_map_configs(map, reserved_maps,
1477 num_maps,
1478 gpio_name, &configs, 1);
1479 if (ret < 0)
1480 goto exit;
1481 }
1482 }
1483
1484 exit:
1485 return ret;
1486 }
1487
1488 static int nmk_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
1489 struct device_node *np_config,
1490 struct pinctrl_map **map, unsigned *num_maps)
1491 {
1492 unsigned reserved_maps;
1493 struct device_node *np;
1494 int ret;
1495
1496 reserved_maps = 0;
1497 *map = NULL;
1498 *num_maps = 0;
1499
1500 for_each_child_of_node(np_config, np) {
1501 ret = nmk_pinctrl_dt_subnode_to_map(pctldev, np, map,
1502 &reserved_maps, num_maps);
1503 if (ret < 0) {
1504 pinctrl_utils_free_map(pctldev, *map, *num_maps);
1505 return ret;
1506 }
1507 }
1508
1509 return 0;
1510 }
1511
1512 static const struct pinctrl_ops nmk_pinctrl_ops = {
1513 .get_groups_count = nmk_get_groups_cnt,
1514 .get_group_name = nmk_get_group_name,
1515 .get_group_pins = nmk_get_group_pins,
1516 .pin_dbg_show = nmk_pin_dbg_show,
1517 .dt_node_to_map = nmk_pinctrl_dt_node_to_map,
1518 .dt_free_map = pinctrl_utils_free_map,
1519 };
1520
1521 static int nmk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
1522 {
1523 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1524
1525 return npct->soc->nfunctions;
1526 }
1527
1528 static const char *nmk_pmx_get_func_name(struct pinctrl_dev *pctldev,
1529 unsigned function)
1530 {
1531 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1532
1533 return npct->soc->functions[function].name;
1534 }
1535
1536 static int nmk_pmx_get_func_groups(struct pinctrl_dev *pctldev,
1537 unsigned function,
1538 const char * const **groups,
1539 unsigned * const num_groups)
1540 {
1541 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1542
1543 *groups = npct->soc->functions[function].groups;
1544 *num_groups = npct->soc->functions[function].ngroups;
1545
1546 return 0;
1547 }
1548
1549 static int nmk_pmx_set(struct pinctrl_dev *pctldev, unsigned function,
1550 unsigned group)
1551 {
1552 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1553 const struct nmk_pingroup *g;
1554 static unsigned int slpm[NUM_BANKS];
1555 unsigned long flags = 0;
1556 bool glitch;
1557 int ret = -EINVAL;
1558 int i;
1559
1560 g = &npct->soc->groups[group];
1561
1562 if (g->altsetting < 0)
1563 return -EINVAL;
1564
1565 dev_dbg(npct->dev, "enable group %s, %u pins\n", g->name, g->npins);
1566
1567 /*
1568 * If we're setting altfunc C by setting both AFSLA and AFSLB to 1,
1569 * we may pass through an undesired state. In this case we take
1570 * some extra care.
1571 *
1572 * Safe sequence used to switch IOs between GPIO and Alternate-C mode:
1573 * - Save SLPM registers (since we have a shadow register in the
1574 * nmk_chip we're using that as backup)
1575 * - Set SLPM=0 for the IOs you want to switch and others to 1
1576 * - Configure the GPIO registers for the IOs that are being switched
1577 * - Set IOFORCE=1
1578 * - Modify the AFLSA/B registers for the IOs that are being switched
1579 * - Set IOFORCE=0
1580 * - Restore SLPM registers
1581 * - Any spurious wake up event during switch sequence to be ignored
1582 * and cleared
1583 *
1584 * We REALLY need to save ALL slpm registers, because the external
1585 * IOFORCE will switch *all* ports to their sleepmode setting to as
1586 * to avoid glitches. (Not just one port!)
1587 */
1588 glitch = ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C);
1589
1590 if (glitch) {
1591 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
1592
1593 /* Initially don't put any pins to sleep when switching */
1594 memset(slpm, 0xff, sizeof(slpm));
1595
1596 /*
1597 * Then mask the pins that need to be sleeping now when we're
1598 * switching to the ALT C function.
1599 */
1600 for (i = 0; i < g->npins; i++)
1601 slpm[g->pins[i] / NMK_GPIO_PER_CHIP] &= ~BIT(g->pins[i]);
1602 nmk_gpio_glitch_slpm_init(slpm);
1603 }
1604
1605 for (i = 0; i < g->npins; i++) {
1606 struct nmk_gpio_chip *nmk_chip;
1607 unsigned bit;
1608
1609 nmk_chip = find_nmk_gpio_from_pin(g->pins[i]);
1610 if (!nmk_chip) {
1611 dev_err(npct->dev,
1612 "invalid pin offset %d in group %s at index %d\n",
1613 g->pins[i], g->name, i);
1614 goto out_glitch;
1615 }
1616 dev_dbg(npct->dev, "setting pin %d to altsetting %d\n", g->pins[i], g->altsetting);
1617
1618 clk_enable(nmk_chip->clk);
1619 bit = g->pins[i] % NMK_GPIO_PER_CHIP;
1620 /*
1621 * If the pin is switching to altfunc, and there was an
1622 * interrupt installed on it which has been lazy disabled,
1623 * actually mask the interrupt to prevent spurious interrupts
1624 * that would occur while the pin is under control of the
1625 * peripheral. Only SKE does this.
1626 */
1627 nmk_gpio_disable_lazy_irq(nmk_chip, bit);
1628
1629 __nmk_gpio_set_mode_safe(nmk_chip, bit,
1630 (g->altsetting & NMK_GPIO_ALT_C), glitch);
1631 clk_disable(nmk_chip->clk);
1632
1633 /*
1634 * Call PRCM GPIOCR config function in case ALTC
1635 * has been selected:
1636 * - If selection is a ALTCx, some bits in PRCM GPIOCR registers
1637 * must be set.
1638 * - If selection is pure ALTC and previous selection was ALTCx,
1639 * then some bits in PRCM GPIOCR registers must be cleared.
1640 */
1641 if ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C)
1642 nmk_prcm_altcx_set_mode(npct, g->pins[i],
1643 g->altsetting >> NMK_GPIO_ALT_CX_SHIFT);
1644 }
1645
1646 /* When all pins are successfully reconfigured we get here */
1647 ret = 0;
1648
1649 out_glitch:
1650 if (glitch) {
1651 nmk_gpio_glitch_slpm_restore(slpm);
1652 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
1653 }
1654
1655 return ret;
1656 }
1657
1658 static int nmk_gpio_request_enable(struct pinctrl_dev *pctldev,
1659 struct pinctrl_gpio_range *range,
1660 unsigned offset)
1661 {
1662 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1663 struct nmk_gpio_chip *nmk_chip;
1664 struct gpio_chip *chip;
1665 unsigned bit;
1666
1667 if (!range) {
1668 dev_err(npct->dev, "invalid range\n");
1669 return -EINVAL;
1670 }
1671 if (!range->gc) {
1672 dev_err(npct->dev, "missing GPIO chip in range\n");
1673 return -EINVAL;
1674 }
1675 chip = range->gc;
1676 nmk_chip = gpiochip_get_data(chip);
1677
1678 dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset);
1679
1680 clk_enable(nmk_chip->clk);
1681 bit = offset % NMK_GPIO_PER_CHIP;
1682 /* There is no glitch when converting any pin to GPIO */
1683 __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);
1684 clk_disable(nmk_chip->clk);
1685
1686 return 0;
1687 }
1688
1689 static void nmk_gpio_disable_free(struct pinctrl_dev *pctldev,
1690 struct pinctrl_gpio_range *range,
1691 unsigned offset)
1692 {
1693 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1694
1695 dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset);
1696 /* Set the pin to some default state, GPIO is usually default */
1697 }
1698
1699 static const struct pinmux_ops nmk_pinmux_ops = {
1700 .get_functions_count = nmk_pmx_get_funcs_cnt,
1701 .get_function_name = nmk_pmx_get_func_name,
1702 .get_function_groups = nmk_pmx_get_func_groups,
1703 .set_mux = nmk_pmx_set,
1704 .gpio_request_enable = nmk_gpio_request_enable,
1705 .gpio_disable_free = nmk_gpio_disable_free,
1706 .strict = true,
1707 };
1708
1709 static int nmk_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin,
1710 unsigned long *config)
1711 {
1712 /* Not implemented */
1713 return -EINVAL;
1714 }
1715
1716 static int nmk_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin,
1717 unsigned long *configs, unsigned num_configs)
1718 {
1719 static const char *pullnames[] = {
1720 [NMK_GPIO_PULL_NONE] = "none",
1721 [NMK_GPIO_PULL_UP] = "up",
1722 [NMK_GPIO_PULL_DOWN] = "down",
1723 [3] /* illegal */ = "??"
1724 };
1725 static const char *slpmnames[] = {
1726 [NMK_GPIO_SLPM_INPUT] = "input/wakeup",
1727 [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup",
1728 };
1729 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1730 struct nmk_gpio_chip *nmk_chip;
1731 unsigned bit;
1732 pin_cfg_t cfg;
1733 int pull, slpm, output, val, i;
1734 bool lowemi, gpiomode, sleep;
1735
1736 nmk_chip = find_nmk_gpio_from_pin(pin);
1737 if (!nmk_chip) {
1738 dev_err(npct->dev,
1739 "invalid pin offset %d\n", pin);
1740 return -EINVAL;
1741 }
1742
1743 for (i = 0; i < num_configs; i++) {
1744 /*
1745 * The pin config contains pin number and altfunction fields,
1746 * here we just ignore that part. It's being handled by the
1747 * framework and pinmux callback respectively.
1748 */
1749 cfg = (pin_cfg_t) configs[i];
1750 pull = PIN_PULL(cfg);
1751 slpm = PIN_SLPM(cfg);
1752 output = PIN_DIR(cfg);
1753 val = PIN_VAL(cfg);
1754 lowemi = PIN_LOWEMI(cfg);
1755 gpiomode = PIN_GPIOMODE(cfg);
1756 sleep = PIN_SLEEPMODE(cfg);
1757
1758 if (sleep) {
1759 int slpm_pull = PIN_SLPM_PULL(cfg);
1760 int slpm_output = PIN_SLPM_DIR(cfg);
1761 int slpm_val = PIN_SLPM_VAL(cfg);
1762
1763 /* All pins go into GPIO mode at sleep */
1764 gpiomode = true;
1765
1766 /*
1767 * The SLPM_* values are normal values + 1 to allow zero
1768 * to mean "same as normal".
1769 */
1770 if (slpm_pull)
1771 pull = slpm_pull - 1;
1772 if (slpm_output)
1773 output = slpm_output - 1;
1774 if (slpm_val)
1775 val = slpm_val - 1;
1776
1777 dev_dbg(nmk_chip->chip.parent,
1778 "pin %d: sleep pull %s, dir %s, val %s\n",
1779 pin,
1780 slpm_pull ? pullnames[pull] : "same",
1781 slpm_output ? (output ? "output" : "input")
1782 : "same",
1783 slpm_val ? (val ? "high" : "low") : "same");
1784 }
1785
1786 dev_dbg(nmk_chip->chip.parent,
1787 "pin %d [%#lx]: pull %s, slpm %s (%s%s), lowemi %s\n",
1788 pin, cfg, pullnames[pull], slpmnames[slpm],
1789 output ? "output " : "input",
1790 output ? (val ? "high" : "low") : "",
1791 lowemi ? "on" : "off");
1792
1793 clk_enable(nmk_chip->clk);
1794 bit = pin % NMK_GPIO_PER_CHIP;
1795 if (gpiomode)
1796 /* No glitch when going to GPIO mode */
1797 __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);
1798 if (output)
1799 __nmk_gpio_make_output(nmk_chip, bit, val);
1800 else {
1801 __nmk_gpio_make_input(nmk_chip, bit);
1802 __nmk_gpio_set_pull(nmk_chip, bit, pull);
1803 }
1804 /* TODO: isn't this only applicable on output pins? */
1805 __nmk_gpio_set_lowemi(nmk_chip, bit, lowemi);
1806
1807 __nmk_gpio_set_slpm(nmk_chip, bit, slpm);
1808 clk_disable(nmk_chip->clk);
1809 } /* for each config */
1810
1811 return 0;
1812 }
1813
1814 static const struct pinconf_ops nmk_pinconf_ops = {
1815 .pin_config_get = nmk_pin_config_get,
1816 .pin_config_set = nmk_pin_config_set,
1817 };
1818
1819 static struct pinctrl_desc nmk_pinctrl_desc = {
1820 .name = "pinctrl-nomadik",
1821 .pctlops = &nmk_pinctrl_ops,
1822 .pmxops = &nmk_pinmux_ops,
1823 .confops = &nmk_pinconf_ops,
1824 .owner = THIS_MODULE,
1825 };
1826
1827 static const struct of_device_id nmk_pinctrl_match[] = {
1828 {
1829 .compatible = "stericsson,stn8815-pinctrl",
1830 .data = (void *)PINCTRL_NMK_STN8815,
1831 },
1832 {
1833 .compatible = "stericsson,db8500-pinctrl",
1834 .data = (void *)PINCTRL_NMK_DB8500,
1835 },
1836 {
1837 .compatible = "stericsson,db8540-pinctrl",
1838 .data = (void *)PINCTRL_NMK_DB8540,
1839 },
1840 {},
1841 };
1842
1843 #ifdef CONFIG_PM_SLEEP
1844 static int nmk_pinctrl_suspend(struct device *dev)
1845 {
1846 struct nmk_pinctrl *npct;
1847
1848 npct = dev_get_drvdata(dev);
1849 if (!npct)
1850 return -EINVAL;
1851
1852 return pinctrl_force_sleep(npct->pctl);
1853 }
1854
1855 static int nmk_pinctrl_resume(struct device *dev)
1856 {
1857 struct nmk_pinctrl *npct;
1858
1859 npct = dev_get_drvdata(dev);
1860 if (!npct)
1861 return -EINVAL;
1862
1863 return pinctrl_force_default(npct->pctl);
1864 }
1865 #endif
1866
1867 static int nmk_pinctrl_probe(struct platform_device *pdev)
1868 {
1869 const struct of_device_id *match;
1870 struct device_node *np = pdev->dev.of_node;
1871 struct device_node *prcm_np;
1872 struct nmk_pinctrl *npct;
1873 unsigned int version = 0;
1874 int i;
1875
1876 npct = devm_kzalloc(&pdev->dev, sizeof(*npct), GFP_KERNEL);
1877 if (!npct)
1878 return -ENOMEM;
1879
1880 match = of_match_device(nmk_pinctrl_match, &pdev->dev);
1881 if (!match)
1882 return -ENODEV;
1883 version = (unsigned int) match->data;
1884
1885 /* Poke in other ASIC variants here */
1886 if (version == PINCTRL_NMK_STN8815)
1887 nmk_pinctrl_stn8815_init(&npct->soc);
1888 if (version == PINCTRL_NMK_DB8500)
1889 nmk_pinctrl_db8500_init(&npct->soc);
1890 if (version == PINCTRL_NMK_DB8540)
1891 nmk_pinctrl_db8540_init(&npct->soc);
1892
1893 /*
1894 * Since we depend on the GPIO chips to provide clock and register base
1895 * for the pin control operations, make sure that we have these
1896 * populated before we continue. Follow the phandles to instantiate
1897 * them. The GPIO portion of the actual hardware may be probed before
1898 * or after this point: it shouldn't matter as the APIs are orthogonal.
1899 */
1900 for (i = 0; i < NMK_MAX_BANKS; i++) {
1901 struct device_node *gpio_np;
1902 struct nmk_gpio_chip *nmk_chip;
1903
1904 gpio_np = of_parse_phandle(np, "nomadik-gpio-chips", i);
1905 if (gpio_np) {
1906 dev_info(&pdev->dev,
1907 "populate NMK GPIO %d \"%s\"\n",
1908 i, gpio_np->name);
1909 nmk_chip = nmk_gpio_populate_chip(gpio_np, pdev);
1910 if (IS_ERR(nmk_chip))
1911 dev_err(&pdev->dev,
1912 "could not populate nmk chip struct "
1913 "- continue anyway\n");
1914 of_node_put(gpio_np);
1915 }
1916 }
1917
1918 prcm_np = of_parse_phandle(np, "prcm", 0);
1919 if (prcm_np)
1920 npct->prcm_base = of_iomap(prcm_np, 0);
1921 if (!npct->prcm_base) {
1922 if (version == PINCTRL_NMK_STN8815) {
1923 dev_info(&pdev->dev,
1924 "No PRCM base, "
1925 "assuming no ALT-Cx control is available\n");
1926 } else {
1927 dev_err(&pdev->dev, "missing PRCM base address\n");
1928 return -EINVAL;
1929 }
1930 }
1931
1932 nmk_pinctrl_desc.pins = npct->soc->pins;
1933 nmk_pinctrl_desc.npins = npct->soc->npins;
1934 npct->dev = &pdev->dev;
1935
1936 npct->pctl = devm_pinctrl_register(&pdev->dev, &nmk_pinctrl_desc, npct);
1937 if (IS_ERR(npct->pctl)) {
1938 dev_err(&pdev->dev, "could not register Nomadik pinctrl driver\n");
1939 return PTR_ERR(npct->pctl);
1940 }
1941
1942 platform_set_drvdata(pdev, npct);
1943 dev_info(&pdev->dev, "initialized Nomadik pin control driver\n");
1944
1945 return 0;
1946 }
1947
1948 static const struct of_device_id nmk_gpio_match[] = {
1949 { .compatible = "st,nomadik-gpio", },
1950 {}
1951 };
1952
1953 static struct platform_driver nmk_gpio_driver = {
1954 .driver = {
1955 .name = "gpio",
1956 .of_match_table = nmk_gpio_match,
1957 },
1958 .probe = nmk_gpio_probe,
1959 };
1960
1961 static SIMPLE_DEV_PM_OPS(nmk_pinctrl_pm_ops,
1962 nmk_pinctrl_suspend,
1963 nmk_pinctrl_resume);
1964
1965 static struct platform_driver nmk_pinctrl_driver = {
1966 .driver = {
1967 .name = "pinctrl-nomadik",
1968 .of_match_table = nmk_pinctrl_match,
1969 .pm = &nmk_pinctrl_pm_ops,
1970 },
1971 .probe = nmk_pinctrl_probe,
1972 };
1973
1974 static int __init nmk_gpio_init(void)
1975 {
1976 return platform_driver_register(&nmk_gpio_driver);
1977 }
1978 subsys_initcall(nmk_gpio_init);
1979
1980 static int __init nmk_pinctrl_init(void)
1981 {
1982 return platform_driver_register(&nmk_pinctrl_driver);
1983 }
1984 core_initcall(nmk_pinctrl_init);
Linux with added FPC-III support