drivers/pinctrl/samsung/pinctrl-exynos.c

   1 /*
   2  * Exynos specific support for Samsung pinctrl/gpiolib driver with eint support.
   3  *
   4  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  * Copyright (c) 2012 Linaro Ltd
   7  *              http://www.linaro.org
   8  *
   9  * Author: Thomas Abraham <thomas.ab@samsung.com>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * This file contains the Samsung Exynos specific information required by the
  17  * the Samsung pinctrl/gpiolib driver. It also includes the implementation of
  18  * external gpio and wakeup interrupt support.
  19  */
  20
  21 #include <linux/device.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/irqdomain.h>
  24 #include <linux/irq.h>
  25 #include <linux/irqchip/chained_irq.h>
  26 #include <linux/of.h>
  27 #include <linux/of_irq.h>
  28 #include <linux/slab.h>
  29 #include <linux/spinlock.h>
  30 #include <linux/regmap.h>
  31 #include <linux/err.h>
  32 #include <linux/soc/samsung/exynos-pmu.h>
  33
  34 #include "pinctrl-samsung.h"
  35 #include "pinctrl-exynos.h"
  36
  37 struct exynos_irq_chip {
  38         struct irq_chip chip;
  39
  40         u32 eint_con;
  41         u32 eint_mask;
  42         u32 eint_pend;
  43 };
  44
  45 static inline struct exynos_irq_chip *to_exynos_irq_chip(struct irq_chip *chip)
  46 {
  47         return container_of(chip, struct exynos_irq_chip, chip);
  48 }
  49
  50 static void exynos_irq_mask(struct irq_data *irqd)
  51 {
  52         struct irq_chip *chip = irq_data_get_irq_chip(irqd);
  53         struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
  54         struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
  55         unsigned long reg_mask = our_chip->eint_mask + bank->eint_offset;
  56         unsigned long mask;
  57         unsigned long flags;
  58
  59         spin_lock_irqsave(&bank->slock, flags);
  60
  61         mask = readl(bank->eint_base + reg_mask);
  62         mask |= 1 << irqd->hwirq;
  63         writel(mask, bank->eint_base + reg_mask);
  64
  65         spin_unlock_irqrestore(&bank->slock, flags);
  66 }
  67
  68 static void exynos_irq_ack(struct irq_data *irqd)
  69 {
  70         struct irq_chip *chip = irq_data_get_irq_chip(irqd);
  71         struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
  72         struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
  73         unsigned long reg_pend = our_chip->eint_pend + bank->eint_offset;
  74
  75         writel(1 << irqd->hwirq, bank->eint_base + reg_pend);
  76 }
  77
  78 static void exynos_irq_unmask(struct irq_data *irqd)
  79 {
  80         struct irq_chip *chip = irq_data_get_irq_chip(irqd);
  81         struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
  82         struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
  83         unsigned long reg_mask = our_chip->eint_mask + bank->eint_offset;
  84         unsigned long mask;
  85         unsigned long flags;
  86
  87         /*
  88          * Ack level interrupts right before unmask
  89          *
  90          * If we don't do this we'll get a double-interrupt.  Level triggered
  91          * interrupts must not fire an interrupt if the level is not
  92          * _currently_ active, even if it was active while the interrupt was
  93          * masked.
  94          */
  95         if (irqd_get_trigger_type(irqd) & IRQ_TYPE_LEVEL_MASK)
  96                 exynos_irq_ack(irqd);
  97
  98         spin_lock_irqsave(&bank->slock, flags);
  99
 100         mask = readl(bank->eint_base + reg_mask);
 101         mask &= ~(1 << irqd->hwirq);
 102         writel(mask, bank->eint_base + reg_mask);
 103
 104         spin_unlock_irqrestore(&bank->slock, flags);
 105 }
 106
 107 static int exynos_irq_set_type(struct irq_data *irqd, unsigned int type)
 108 {
 109         struct irq_chip *chip = irq_data_get_irq_chip(irqd);
 110         struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
 111         struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
 112         unsigned int shift = EXYNOS_EINT_CON_LEN * irqd->hwirq;
 113         unsigned int con, trig_type;
 114         unsigned long reg_con = our_chip->eint_con + bank->eint_offset;
 115
 116         switch (type) {
 117         case IRQ_TYPE_EDGE_RISING:
 118                 trig_type = EXYNOS_EINT_EDGE_RISING;
 119                 break;
 120         case IRQ_TYPE_EDGE_FALLING:
 121                 trig_type = EXYNOS_EINT_EDGE_FALLING;
 122                 break;
 123         case IRQ_TYPE_EDGE_BOTH:
 124                 trig_type = EXYNOS_EINT_EDGE_BOTH;
 125                 break;
 126         case IRQ_TYPE_LEVEL_HIGH:
 127                 trig_type = EXYNOS_EINT_LEVEL_HIGH;
 128                 break;
 129         case IRQ_TYPE_LEVEL_LOW:
 130                 trig_type = EXYNOS_EINT_LEVEL_LOW;
 131                 break;
 132         default:
 133                 pr_err("unsupported external interrupt type\n");
 134                 return -EINVAL;
 135         }
 136
 137         if (type & IRQ_TYPE_EDGE_BOTH)
 138                 irq_set_handler_locked(irqd, handle_edge_irq);
 139         else
 140                 irq_set_handler_locked(irqd, handle_level_irq);
 141
 142         con = readl(bank->eint_base + reg_con);
 143         con &= ~(EXYNOS_EINT_CON_MASK << shift);
 144         con |= trig_type << shift;
 145         writel(con, bank->eint_base + reg_con);
 146
 147         return 0;
 148 }
 149
 150 static int exynos_irq_request_resources(struct irq_data *irqd)
 151 {
 152         struct irq_chip *chip = irq_data_get_irq_chip(irqd);
 153         struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
 154         struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
 155         const struct samsung_pin_bank_type *bank_type = bank->type;
 156         unsigned int shift = EXYNOS_EINT_CON_LEN * irqd->hwirq;
 157         unsigned long reg_con = our_chip->eint_con + bank->eint_offset;
 158         unsigned long flags;
 159         unsigned int mask;
 160         unsigned int con;
 161         int ret;
 162
 163         ret = gpiochip_lock_as_irq(&bank->gpio_chip, irqd->hwirq);
 164         if (ret) {
 165                 dev_err(bank->gpio_chip.parent,
 166                         "unable to lock pin %s-%lu IRQ\n",
 167                         bank->name, irqd->hwirq);
 168                 return ret;
 169         }
 170
 171         reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC];
 172         shift = irqd->hwirq * bank_type->fld_width[PINCFG_TYPE_FUNC];
 173         mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1;
 174
 175         spin_lock_irqsave(&bank->slock, flags);
 176
 177         con = readl(bank->eint_base + reg_con);
 178         con &= ~(mask << shift);
 179         con |= EXYNOS_EINT_FUNC << shift;
 180         writel(con, bank->eint_base + reg_con);
 181
 182         spin_unlock_irqrestore(&bank->slock, flags);
 183
 184         return 0;
 185 }
 186
 187 static void exynos_irq_release_resources(struct irq_data *irqd)
 188 {
 189         struct irq_chip *chip = irq_data_get_irq_chip(irqd);
 190         struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
 191         struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
 192         const struct samsung_pin_bank_type *bank_type = bank->type;
 193         unsigned int shift = EXYNOS_EINT_CON_LEN * irqd->hwirq;
 194         unsigned long reg_con = our_chip->eint_con + bank->eint_offset;
 195         unsigned long flags;
 196         unsigned int mask;
 197         unsigned int con;
 198
 199         reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC];
 200         shift = irqd->hwirq * bank_type->fld_width[PINCFG_TYPE_FUNC];
 201         mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1;
 202
 203         spin_lock_irqsave(&bank->slock, flags);
 204
 205         con = readl(bank->eint_base + reg_con);
 206         con &= ~(mask << shift);
 207         con |= FUNC_INPUT << shift;
 208         writel(con, bank->eint_base + reg_con);
 209
 210         spin_unlock_irqrestore(&bank->slock, flags);
 211
 212         gpiochip_unlock_as_irq(&bank->gpio_chip, irqd->hwirq);
 213 }
 214
 215 /*
 216  * irq_chip for gpio interrupts.
 217  */
 218 static struct exynos_irq_chip exynos_gpio_irq_chip = {
 219         .chip = {
 220                 .name = "exynos_gpio_irq_chip",
 221                 .irq_unmask = exynos_irq_unmask,
 222                 .irq_mask = exynos_irq_mask,
 223                 .irq_ack = exynos_irq_ack,
 224                 .irq_set_type = exynos_irq_set_type,
 225                 .irq_request_resources = exynos_irq_request_resources,
 226                 .irq_release_resources = exynos_irq_release_resources,
 227         },
 228         .eint_con = EXYNOS_GPIO_ECON_OFFSET,
 229         .eint_mask = EXYNOS_GPIO_EMASK_OFFSET,
 230         .eint_pend = EXYNOS_GPIO_EPEND_OFFSET,
 231 };
 232
 233 static int exynos_eint_irq_map(struct irq_domain *h, unsigned int virq,
 234                                         irq_hw_number_t hw)
 235 {
 236         struct samsung_pin_bank *b = h->host_data;
 237
 238         irq_set_chip_data(virq, b);
 239         irq_set_chip_and_handler(virq, &b->irq_chip->chip,
 240                                         handle_level_irq);
 241         return 0;
 242 }
 243
 244 /*
 245  * irq domain callbacks for external gpio and wakeup interrupt controllers.
 246  */
 247 static const struct irq_domain_ops exynos_eint_irqd_ops = {
 248         .map    = exynos_eint_irq_map,
 249         .xlate  = irq_domain_xlate_twocell,
 250 };
 251
 252 static irqreturn_t exynos_eint_gpio_irq(int irq, void *data)
 253 {
 254         struct samsung_pinctrl_drv_data *d = data;
 255         struct samsung_pin_bank *bank = d->pin_banks;
 256         unsigned int svc, group, pin, virq;
 257
 258         svc = readl(bank->eint_base + EXYNOS_SVC_OFFSET);
 259         group = EXYNOS_SVC_GROUP(svc);
 260         pin = svc & EXYNOS_SVC_NUM_MASK;
 261
 262         if (!group)
 263                 return IRQ_HANDLED;
 264         bank += (group - 1);
 265
 266         virq = irq_linear_revmap(bank->irq_domain, pin);
 267         if (!virq)
 268                 return IRQ_NONE;
 269         generic_handle_irq(virq);
 270         return IRQ_HANDLED;
 271 }
 272
 273 struct exynos_eint_gpio_save {
 274         u32 eint_con;
 275         u32 eint_fltcon0;
 276         u32 eint_fltcon1;
 277 };
 278
 279 /*
 280  * exynos_eint_gpio_init() - setup handling of external gpio interrupts.
 281  * @d: driver data of samsung pinctrl driver.
 282  */
 283 int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d)
 284 {
 285         struct samsung_pin_bank *bank;
 286         struct device *dev = d->dev;
 287         int ret;
 288         int i;
 289
 290         if (!d->irq) {
 291                 dev_err(dev, "irq number not available\n");
 292                 return -EINVAL;
 293         }
 294
 295         ret = devm_request_irq(dev, d->irq, exynos_eint_gpio_irq,
 296                                         0, dev_name(dev), d);
 297         if (ret) {
 298                 dev_err(dev, "irq request failed\n");
 299                 return -ENXIO;
 300         }
 301
 302         bank = d->pin_banks;
 303         for (i = 0; i < d->nr_banks; ++i, ++bank) {
 304                 if (bank->eint_type != EINT_TYPE_GPIO)
 305                         continue;
 306                 bank->irq_domain = irq_domain_add_linear(bank->of_node,
 307                                 bank->nr_pins, &exynos_eint_irqd_ops, bank);
 308                 if (!bank->irq_domain) {
 309                         dev_err(dev, "gpio irq domain add failed\n");
 310                         ret = -ENXIO;
 311                         goto err_domains;
 312                 }
 313
 314                 bank->soc_priv = devm_kzalloc(d->dev,
 315                         sizeof(struct exynos_eint_gpio_save), GFP_KERNEL);
 316                 if (!bank->soc_priv) {
 317                         irq_domain_remove(bank->irq_domain);
 318                         ret = -ENOMEM;
 319                         goto err_domains;
 320                 }
 321
 322                 bank->irq_chip = &exynos_gpio_irq_chip;
 323         }
 324
 325         return 0;
 326
 327 err_domains:
 328         for (--i, --bank; i >= 0; --i, --bank) {
 329                 if (bank->eint_type != EINT_TYPE_GPIO)
 330                         continue;
 331                 irq_domain_remove(bank->irq_domain);
 332         }
 333
 334         return ret;
 335 }
 336
 337 static u32 exynos_eint_wake_mask = 0xffffffff;
 338
 339 u32 exynos_get_eint_wake_mask(void)
 340 {
 341         return exynos_eint_wake_mask;
 342 }
 343
 344 static int exynos_wkup_irq_set_wake(struct irq_data *irqd, unsigned int on)
 345 {
 346         struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
 347         unsigned long bit = 1UL << (2 * bank->eint_offset + irqd->hwirq);
 348
 349         pr_info("wake %s for irq %d\n", on ? "enabled" : "disabled", irqd->irq);
 350
 351         if (!on)
 352                 exynos_eint_wake_mask |= bit;
 353         else
 354                 exynos_eint_wake_mask &= ~bit;
 355
 356         return 0;
 357 }
 358
 359 /*
 360  * irq_chip for wakeup interrupts
 361  */
 362 static const struct exynos_irq_chip exynos4210_wkup_irq_chip __initconst = {
 363         .chip = {
 364                 .name = "exynos4210_wkup_irq_chip",
 365                 .irq_unmask = exynos_irq_unmask,
 366                 .irq_mask = exynos_irq_mask,
 367                 .irq_ack = exynos_irq_ack,
 368                 .irq_set_type = exynos_irq_set_type,
 369                 .irq_set_wake = exynos_wkup_irq_set_wake,
 370                 .irq_request_resources = exynos_irq_request_resources,
 371                 .irq_release_resources = exynos_irq_release_resources,
 372         },
 373         .eint_con = EXYNOS_WKUP_ECON_OFFSET,
 374         .eint_mask = EXYNOS_WKUP_EMASK_OFFSET,
 375         .eint_pend = EXYNOS_WKUP_EPEND_OFFSET,
 376 };
 377
 378 static const struct exynos_irq_chip exynos7_wkup_irq_chip __initconst = {
 379         .chip = {
 380                 .name = "exynos7_wkup_irq_chip",
 381                 .irq_unmask = exynos_irq_unmask,
 382                 .irq_mask = exynos_irq_mask,
 383                 .irq_ack = exynos_irq_ack,
 384                 .irq_set_type = exynos_irq_set_type,
 385                 .irq_set_wake = exynos_wkup_irq_set_wake,
 386                 .irq_request_resources = exynos_irq_request_resources,
 387                 .irq_release_resources = exynos_irq_release_resources,
 388         },
 389         .eint_con = EXYNOS7_WKUP_ECON_OFFSET,
 390         .eint_mask = EXYNOS7_WKUP_EMASK_OFFSET,
 391         .eint_pend = EXYNOS7_WKUP_EPEND_OFFSET,
 392 };
 393
 394 /* list of external wakeup controllers supported */
 395 static const struct of_device_id exynos_wkup_irq_ids[] = {
 396         { .compatible = "samsung,exynos4210-wakeup-eint",
 397                         .data = &exynos4210_wkup_irq_chip },
 398         { .compatible = "samsung,exynos7-wakeup-eint",
 399                         .data = &exynos7_wkup_irq_chip },
 400         { }
 401 };
 402
 403 /* interrupt handler for wakeup interrupts 0..15 */
 404 static void exynos_irq_eint0_15(struct irq_desc *desc)
 405 {
 406         struct exynos_weint_data *eintd = irq_desc_get_handler_data(desc);
 407         struct samsung_pin_bank *bank = eintd->bank;
 408         struct irq_chip *chip = irq_desc_get_chip(desc);
 409         int eint_irq;
 410
 411         chained_irq_enter(chip, desc);
 412
 413         eint_irq = irq_linear_revmap(bank->irq_domain, eintd->irq);
 414         generic_handle_irq(eint_irq);
 415
 416         chained_irq_exit(chip, desc);
 417 }
 418
 419 static inline void exynos_irq_demux_eint(unsigned long pend,
 420                                                 struct irq_domain *domain)
 421 {
 422         unsigned int irq;
 423
 424         while (pend) {
 425                 irq = fls(pend) - 1;
 426                 generic_handle_irq(irq_find_mapping(domain, irq));
 427                 pend &= ~(1 << irq);
 428         }
 429 }
 430
 431 /* interrupt handler for wakeup interrupt 16 */
 432 static void exynos_irq_demux_eint16_31(struct irq_desc *desc)
 433 {
 434         struct irq_chip *chip = irq_desc_get_chip(desc);
 435         struct exynos_muxed_weint_data *eintd = irq_desc_get_handler_data(desc);
 436         unsigned long pend;
 437         unsigned long mask;
 438         int i;
 439
 440         chained_irq_enter(chip, desc);
 441
 442         for (i = 0; i < eintd->nr_banks; ++i) {
 443                 struct samsung_pin_bank *b = eintd->banks[i];
 444                 pend = readl(b->eint_base + b->irq_chip->eint_pend
 445                                 + b->eint_offset);
 446                 mask = readl(b->eint_base + b->irq_chip->eint_mask
 447                                 + b->eint_offset);
 448                 exynos_irq_demux_eint(pend & ~mask, b->irq_domain);
 449         }
 450
 451         chained_irq_exit(chip, desc);
 452 }
 453
 454 /*
 455  * exynos_eint_wkup_init() - setup handling of external wakeup interrupts.
 456  * @d: driver data of samsung pinctrl driver.
 457  */
 458 int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d)
 459 {
 460         struct device *dev = d->dev;
 461         struct device_node *wkup_np = NULL;
 462         struct device_node *np;
 463         struct samsung_pin_bank *bank;
 464         struct exynos_weint_data *weint_data;
 465         struct exynos_muxed_weint_data *muxed_data;
 466         struct exynos_irq_chip *irq_chip;
 467         unsigned int muxed_banks = 0;
 468         unsigned int i;
 469         int idx, irq;
 470
 471         for_each_child_of_node(dev->of_node, np) {
 472                 const struct of_device_id *match;
 473
 474                 match = of_match_node(exynos_wkup_irq_ids, np);
 475                 if (match) {
 476                         irq_chip = kmemdup(match->data,
 477                                 sizeof(*irq_chip), GFP_KERNEL);
 478                         if (!irq_chip)
 479                                 return -ENOMEM;
 480                         wkup_np = np;
 481                         break;
 482                 }
 483         }
 484         if (!wkup_np)
 485                 return -ENODEV;
 486
 487         bank = d->pin_banks;
 488         for (i = 0; i < d->nr_banks; ++i, ++bank) {
 489                 if (bank->eint_type != EINT_TYPE_WKUP)
 490                         continue;
 491
 492                 bank->irq_domain = irq_domain_add_linear(bank->of_node,
 493                                 bank->nr_pins, &exynos_eint_irqd_ops, bank);
 494                 if (!bank->irq_domain) {
 495                         dev_err(dev, "wkup irq domain add failed\n");
 496                         return -ENXIO;
 497                 }
 498
 499                 bank->irq_chip = irq_chip;
 500
 501                 if (!of_find_property(bank->of_node, "interrupts", NULL)) {
 502                         bank->eint_type = EINT_TYPE_WKUP_MUX;
 503                         ++muxed_banks;
 504                         continue;
 505                 }
 506
 507                 weint_data = devm_kzalloc(dev, bank->nr_pins
 508                                         * sizeof(*weint_data), GFP_KERNEL);
 509                 if (!weint_data)
 510                         return -ENOMEM;
 511
 512                 for (idx = 0; idx < bank->nr_pins; ++idx) {
 513                         irq = irq_of_parse_and_map(bank->of_node, idx);
 514                         if (!irq) {
 515                                 dev_err(dev, "irq number for eint-%s-%d not found\n",
 516                                                         bank->name, idx);
 517                                 continue;
 518                         }
 519                         weint_data[idx].irq = idx;
 520                         weint_data[idx].bank = bank;
 521                         irq_set_chained_handler_and_data(irq,
 522                                                          exynos_irq_eint0_15,
 523                                                          &weint_data[idx]);
 524                 }
 525         }
 526
 527         if (!muxed_banks)
 528                 return 0;
 529
 530         irq = irq_of_parse_and_map(wkup_np, 0);
 531         if (!irq) {
 532                 dev_err(dev, "irq number for muxed EINTs not found\n");
 533                 return 0;
 534         }
 535
 536         muxed_data = devm_kzalloc(dev, sizeof(*muxed_data)
 537                 + muxed_banks*sizeof(struct samsung_pin_bank *), GFP_KERNEL);
 538         if (!muxed_data)
 539                 return -ENOMEM;
 540
 541         irq_set_chained_handler_and_data(irq, exynos_irq_demux_eint16_31,
 542                                          muxed_data);
 543
 544         bank = d->pin_banks;
 545         idx = 0;
 546         for (i = 0; i < d->nr_banks; ++i, ++bank) {
 547                 if (bank->eint_type != EINT_TYPE_WKUP_MUX)
 548                         continue;
 549
 550                 muxed_data->banks[idx++] = bank;
 551         }
 552         muxed_data->nr_banks = muxed_banks;
 553
 554         return 0;
 555 }
 556
 557 static void exynos_pinctrl_suspend_bank(
 558                                 struct samsung_pinctrl_drv_data *drvdata,
 559                                 struct samsung_pin_bank *bank)
 560 {
 561         struct exynos_eint_gpio_save *save = bank->soc_priv;
 562         void __iomem *regs = bank->eint_base;
 563
 564         save->eint_con = readl(regs + EXYNOS_GPIO_ECON_OFFSET
 565                                                 + bank->eint_offset);
 566         save->eint_fltcon0 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
 567                                                 + 2 * bank->eint_offset);
 568         save->eint_fltcon1 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
 569                                                 + 2 * bank->eint_offset + 4);
 570
 571         pr_debug("%s: save     con %#010x\n", bank->name, save->eint_con);
 572         pr_debug("%s: save fltcon0 %#010x\n", bank->name, save->eint_fltcon0);
 573         pr_debug("%s: save fltcon1 %#010x\n", bank->name, save->eint_fltcon1);
 574 }
 575
 576 void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata)
 577 {
 578         struct samsung_pin_bank *bank = drvdata->pin_banks;
 579         int i;
 580
 581         for (i = 0; i < drvdata->nr_banks; ++i, ++bank)
 582                 if (bank->eint_type == EINT_TYPE_GPIO)
 583                         exynos_pinctrl_suspend_bank(drvdata, bank);
 584 }
 585
 586 static void exynos_pinctrl_resume_bank(
 587                                 struct samsung_pinctrl_drv_data *drvdata,
 588                                 struct samsung_pin_bank *bank)
 589 {
 590         struct exynos_eint_gpio_save *save = bank->soc_priv;
 591         void __iomem *regs = bank->eint_base;
 592
 593         pr_debug("%s:     con %#010x => %#010x\n", bank->name,
 594                         readl(regs + EXYNOS_GPIO_ECON_OFFSET
 595                         + bank->eint_offset), save->eint_con);
 596         pr_debug("%s: fltcon0 %#010x => %#010x\n", bank->name,
 597                         readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
 598                         + 2 * bank->eint_offset), save->eint_fltcon0);
 599         pr_debug("%s: fltcon1 %#010x => %#010x\n", bank->name,
 600                         readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
 601                         + 2 * bank->eint_offset + 4), save->eint_fltcon1);
 602
 603         writel(save->eint_con, regs + EXYNOS_GPIO_ECON_OFFSET
 604                                                 + bank->eint_offset);
 605         writel(save->eint_fltcon0, regs + EXYNOS_GPIO_EFLTCON_OFFSET
 606                                                 + 2 * bank->eint_offset);
 607         writel(save->eint_fltcon1, regs + EXYNOS_GPIO_EFLTCON_OFFSET
 608                                                 + 2 * bank->eint_offset + 4);
 609 }
 610
 611 void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata)
 612 {
 613         struct samsung_pin_bank *bank = drvdata->pin_banks;
 614         int i;
 615
 616         for (i = 0; i < drvdata->nr_banks; ++i, ++bank)
 617                 if (bank->eint_type == EINT_TYPE_GPIO)
 618                         exynos_pinctrl_resume_bank(drvdata, bank);
 619 }
 620
 621 static void exynos_retention_enable(struct samsung_pinctrl_drv_data *drvdata)
 622 {
 623         if (drvdata->retention_ctrl->refcnt)
 624                 atomic_inc(drvdata->retention_ctrl->refcnt);
 625 }
 626
 627 static void exynos_retention_disable(struct samsung_pinctrl_drv_data *drvdata)
 628 {
 629         struct samsung_retention_ctrl *ctrl = drvdata->retention_ctrl;
 630         struct regmap *pmu_regs = ctrl->priv;
 631         int i;
 632
 633         if (ctrl->refcnt && !atomic_dec_and_test(ctrl->refcnt))
 634                 return;
 635
 636         for (i = 0; i < ctrl->nr_regs; i++)
 637                 regmap_write(pmu_regs, ctrl->regs[i], ctrl->value);
 638 }
 639
 640 struct samsung_retention_ctrl *
 641 exynos_retention_init(struct samsung_pinctrl_drv_data *drvdata,
 642                       const struct samsung_retention_data *data)
 643 {
 644         struct samsung_retention_ctrl *ctrl;
 645         struct regmap *pmu_regs;
 646         int i;
 647
 648         ctrl = devm_kzalloc(drvdata->dev, sizeof(*ctrl), GFP_KERNEL);
 649         if (!ctrl)
 650                 return ERR_PTR(-ENOMEM);
 651
 652         pmu_regs = exynos_get_pmu_regmap();
 653         if (IS_ERR(pmu_regs))
 654                 return ERR_CAST(pmu_regs);
 655
 656         ctrl->priv = pmu_regs;
 657         ctrl->regs = data->regs;
 658         ctrl->nr_regs = data->nr_regs;
 659         ctrl->value = data->value;
 660         ctrl->refcnt = data->refcnt;
 661         ctrl->enable = exynos_retention_enable;
 662         ctrl->disable = exynos_retention_disable;
 663
 664         /* Ensure that retention is disabled on driver init */
 665         for (i = 0; i < ctrl->nr_regs; i++)
 666                 regmap_write(pmu_regs, ctrl->regs[i], ctrl->value);
 667
 668         return ctrl;
 669 }