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Merge tag 'ceph-for-4.13-rc8' of git://github.com/ceph/ceph-client
[linux/fpc-iii.git] / drivers / pinctrl / samsung / pinctrl-s3c64xx.c
blob4a88d7446e87b664de0e52a8a27a6a403990d105
1 /*
2 * S3C64xx specific support for pinctrl-samsung driver.
3 *
4 * Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com>
5 *
6 * Based on pinctrl-exynos.c, please see the file for original copyrights.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This file contains the Samsung S3C64xx specific information required by the
14 * the Samsung pinctrl/gpiolib driver. It also includes the implementation of
15 * external gpio and wakeup interrupt support.
16 */
17
18 #include <linux/init.h>
19 #include <linux/device.h>
20 #include <linux/interrupt.h>
21 #include <linux/irqdomain.h>
22 #include <linux/irq.h>
23 #include <linux/of_irq.h>
24 #include <linux/io.h>
25 #include <linux/irqchip/chained_irq.h>
26 #include <linux/slab.h>
27 #include <linux/err.h>
28
29 #include "pinctrl-samsung.h"
30
31 #define NUM_EINT0 28
32 #define NUM_EINT0_IRQ 4
33 #define EINT_MAX_PER_REG 16
34 #define EINT_MAX_PER_GROUP 16
35
36 /* External GPIO and wakeup interrupt related definitions */
37 #define SVC_GROUP_SHIFT 4
38 #define SVC_GROUP_MASK 0xf
39 #define SVC_NUM_MASK 0xf
40 #define SVC_GROUP(x) ((x >> SVC_GROUP_SHIFT) & \
41 SVC_GROUP_MASK)
42
43 #define EINT12CON_REG 0x200
44 #define EINT12MASK_REG 0x240
45 #define EINT12PEND_REG 0x260
46
47 #define EINT_OFFS(i) ((i) % (2 * EINT_MAX_PER_GROUP))
48 #define EINT_GROUP(i) ((i) / EINT_MAX_PER_GROUP)
49 #define EINT_REG(g) (4 * ((g) / 2))
50
51 #define EINTCON_REG(i) (EINT12CON_REG + EINT_REG(EINT_GROUP(i)))
52 #define EINTMASK_REG(i) (EINT12MASK_REG + EINT_REG(EINT_GROUP(i)))
53 #define EINTPEND_REG(i) (EINT12PEND_REG + EINT_REG(EINT_GROUP(i)))
54
55 #define SERVICE_REG 0x284
56 #define SERVICEPEND_REG 0x288
57
58 #define EINT0CON0_REG 0x900
59 #define EINT0MASK_REG 0x920
60 #define EINT0PEND_REG 0x924
61
62 /* S3C64xx specific external interrupt trigger types */
63 #define EINT_LEVEL_LOW 0
64 #define EINT_LEVEL_HIGH 1
65 #define EINT_EDGE_FALLING 2
66 #define EINT_EDGE_RISING 4
67 #define EINT_EDGE_BOTH 6
68 #define EINT_CON_MASK 0xF
69 #define EINT_CON_LEN 4
70
71 static const struct samsung_pin_bank_type bank_type_4bit_off = {
72 .fld_width = { 4, 1, 2, 0, 2, 2, },
73 .reg_offset = { 0x00, 0x04, 0x08, 0, 0x0c, 0x10, },
74 };
75
76 static const struct samsung_pin_bank_type bank_type_4bit_alive = {
77 .fld_width = { 4, 1, 2, },
78 .reg_offset = { 0x00, 0x04, 0x08, },
79 };
80
81 static const struct samsung_pin_bank_type bank_type_4bit2_off = {
82 .fld_width = { 4, 1, 2, 0, 2, 2, },
83 .reg_offset = { 0x00, 0x08, 0x0c, 0, 0x10, 0x14, },
84 };
85
86 static const struct samsung_pin_bank_type bank_type_4bit2_alive = {
87 .fld_width = { 4, 1, 2, },
88 .reg_offset = { 0x00, 0x08, 0x0c, },
89 };
90
91 static const struct samsung_pin_bank_type bank_type_2bit_off = {
92 .fld_width = { 2, 1, 2, 0, 2, 2, },
93 .reg_offset = { 0x00, 0x04, 0x08, 0, 0x0c, 0x10, },
94 };
95
96 static const struct samsung_pin_bank_type bank_type_2bit_alive = {
97 .fld_width = { 2, 1, 2, },
98 .reg_offset = { 0x00, 0x04, 0x08, },
99 };
100
101 #define PIN_BANK_4BIT(pins, reg, id) \
102 { \
103 .type = &bank_type_4bit_off, \
104 .pctl_offset = reg, \
105 .nr_pins = pins, \
106 .eint_type = EINT_TYPE_NONE, \
107 .name = id \
108 }
109
110 #define PIN_BANK_4BIT_EINTG(pins, reg, id, eoffs) \
111 { \
112 .type = &bank_type_4bit_off, \
113 .pctl_offset = reg, \
114 .nr_pins = pins, \
115 .eint_type = EINT_TYPE_GPIO, \
116 .eint_func = 7, \
117 .eint_mask = (1 << (pins)) - 1, \
118 .eint_offset = eoffs, \
119 .name = id \
120 }
121
122 #define PIN_BANK_4BIT_EINTW(pins, reg, id, eoffs, emask) \
123 { \
124 .type = &bank_type_4bit_alive,\
125 .pctl_offset = reg, \
126 .nr_pins = pins, \
127 .eint_type = EINT_TYPE_WKUP, \
128 .eint_func = 3, \
129 .eint_mask = emask, \
130 .eint_offset = eoffs, \
131 .name = id \
132 }
133
134 #define PIN_BANK_4BIT2_EINTG(pins, reg, id, eoffs) \
135 { \
136 .type = &bank_type_4bit2_off, \
137 .pctl_offset = reg, \
138 .nr_pins = pins, \
139 .eint_type = EINT_TYPE_GPIO, \
140 .eint_func = 7, \
141 .eint_mask = (1 << (pins)) - 1, \
142 .eint_offset = eoffs, \
143 .name = id \
144 }
145
146 #define PIN_BANK_4BIT2_EINTW(pins, reg, id, eoffs, emask) \
147 { \
148 .type = &bank_type_4bit2_alive,\
149 .pctl_offset = reg, \
150 .nr_pins = pins, \
151 .eint_type = EINT_TYPE_WKUP, \
152 .eint_func = 3, \
153 .eint_mask = emask, \
154 .eint_offset = eoffs, \
155 .name = id \
156 }
157
158 #define PIN_BANK_4BIT2_ALIVE(pins, reg, id) \
159 { \
160 .type = &bank_type_4bit2_alive,\
161 .pctl_offset = reg, \
162 .nr_pins = pins, \
163 .eint_type = EINT_TYPE_NONE, \
164 .name = id \
165 }
166
167 #define PIN_BANK_2BIT(pins, reg, id) \
168 { \
169 .type = &bank_type_2bit_off, \
170 .pctl_offset = reg, \
171 .nr_pins = pins, \
172 .eint_type = EINT_TYPE_NONE, \
173 .name = id \
174 }
175
176 #define PIN_BANK_2BIT_EINTG(pins, reg, id, eoffs, emask) \
177 { \
178 .type = &bank_type_2bit_off, \
179 .pctl_offset = reg, \
180 .nr_pins = pins, \
181 .eint_type = EINT_TYPE_GPIO, \
182 .eint_func = 3, \
183 .eint_mask = emask, \
184 .eint_offset = eoffs, \
185 .name = id \
186 }
187
188 #define PIN_BANK_2BIT_EINTW(pins, reg, id, eoffs) \
189 { \
190 .type = &bank_type_2bit_alive,\
191 .pctl_offset = reg, \
192 .nr_pins = pins, \
193 .eint_type = EINT_TYPE_WKUP, \
194 .eint_func = 2, \
195 .eint_mask = (1 << (pins)) - 1, \
196 .eint_offset = eoffs, \
197 .name = id \
198 }
199
200 /**
201 * struct s3c64xx_eint0_data: EINT0 common data
202 * @drvdata: pin controller driver data
203 * @domains: IRQ domains of particular EINT0 interrupts
204 * @pins: pin offsets inside of banks of particular EINT0 interrupts
205 */
206 struct s3c64xx_eint0_data {
207 struct samsung_pinctrl_drv_data *drvdata;
208 struct irq_domain *domains[NUM_EINT0];
209 u8 pins[NUM_EINT0];
210 };
211
212 /**
213 * struct s3c64xx_eint0_domain_data: EINT0 per-domain data
214 * @bank: pin bank related to the domain
215 * @eints: EINT0 interrupts related to the domain
216 */
217 struct s3c64xx_eint0_domain_data {
218 struct samsung_pin_bank *bank;
219 u8 eints[];
220 };
221
222 /**
223 * struct s3c64xx_eint_gpio_data: GPIO EINT data
224 * @drvdata: pin controller driver data
225 * @domains: array of domains related to EINT interrupt groups
226 */
227 struct s3c64xx_eint_gpio_data {
228 struct samsung_pinctrl_drv_data *drvdata;
229 struct irq_domain *domains[];
230 };
231
232 /*
233 * Common functions for S3C64xx EINT configuration
234 */
235
236 static int s3c64xx_irq_get_trigger(unsigned int type)
237 {
238 int trigger;
239
240 switch (type) {
241 case IRQ_TYPE_EDGE_RISING:
242 trigger = EINT_EDGE_RISING;
243 break;
244 case IRQ_TYPE_EDGE_FALLING:
245 trigger = EINT_EDGE_FALLING;
246 break;
247 case IRQ_TYPE_EDGE_BOTH:
248 trigger = EINT_EDGE_BOTH;
249 break;
250 case IRQ_TYPE_LEVEL_HIGH:
251 trigger = EINT_LEVEL_HIGH;
252 break;
253 case IRQ_TYPE_LEVEL_LOW:
254 trigger = EINT_LEVEL_LOW;
255 break;
256 default:
257 return -EINVAL;
258 }
259
260 return trigger;
261 }
262
263 static void s3c64xx_irq_set_handler(struct irq_data *d, unsigned int type)
264 {
265 /* Edge- and level-triggered interrupts need different handlers */
266 if (type & IRQ_TYPE_EDGE_BOTH)
267 irq_set_handler_locked(d, handle_edge_irq);
268 else
269 irq_set_handler_locked(d, handle_level_irq);
270 }
271
272 static void s3c64xx_irq_set_function(struct samsung_pinctrl_drv_data *d,
273 struct samsung_pin_bank *bank, int pin)
274 {
275 const struct samsung_pin_bank_type *bank_type = bank->type;
276 unsigned long flags;
277 void __iomem *reg;
278 u8 shift;
279 u32 mask;
280 u32 val;
281
282 /* Make sure that pin is configured as interrupt */
283 reg = bank->pctl_base + bank->pctl_offset;
284 shift = pin;
285 if (bank_type->fld_width[PINCFG_TYPE_FUNC] * shift >= 32) {
286 /* 4-bit bank type with 2 con regs */
287 reg += 4;
288 shift -= 8;
289 }
290
291 shift = shift * bank_type->fld_width[PINCFG_TYPE_FUNC];
292 mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1;
293
294 spin_lock_irqsave(&bank->slock, flags);
295
296 val = readl(reg);
297 val &= ~(mask << shift);
298 val |= bank->eint_func << shift;
299 writel(val, reg);
300
301 spin_unlock_irqrestore(&bank->slock, flags);
302 }
303
304 /*
305 * Functions for EINT GPIO configuration (EINT groups 1-9)
306 */
307
308 static inline void s3c64xx_gpio_irq_set_mask(struct irq_data *irqd, bool mask)
309 {
310 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
311 unsigned char index = EINT_OFFS(bank->eint_offset) + irqd->hwirq;
312 void __iomem *reg = bank->eint_base + EINTMASK_REG(bank->eint_offset);
313 u32 val;
314
315 val = readl(reg);
316 if (mask)
317 val |= 1 << index;
318 else
319 val &= ~(1 << index);
320 writel(val, reg);
321 }
322
323 static void s3c64xx_gpio_irq_unmask(struct irq_data *irqd)
324 {
325 s3c64xx_gpio_irq_set_mask(irqd, false);
326 }
327
328 static void s3c64xx_gpio_irq_mask(struct irq_data *irqd)
329 {
330 s3c64xx_gpio_irq_set_mask(irqd, true);
331 }
332
333 static void s3c64xx_gpio_irq_ack(struct irq_data *irqd)
334 {
335 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
336 unsigned char index = EINT_OFFS(bank->eint_offset) + irqd->hwirq;
337 void __iomem *reg = bank->eint_base + EINTPEND_REG(bank->eint_offset);
338
339 writel(1 << index, reg);
340 }
341
342 static int s3c64xx_gpio_irq_set_type(struct irq_data *irqd, unsigned int type)
343 {
344 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
345 struct samsung_pinctrl_drv_data *d = bank->drvdata;
346 void __iomem *reg;
347 int trigger;
348 u8 shift;
349 u32 val;
350
351 trigger = s3c64xx_irq_get_trigger(type);
352 if (trigger < 0) {
353 pr_err("unsupported external interrupt type\n");
354 return -EINVAL;
355 }
356
357 s3c64xx_irq_set_handler(irqd, type);
358
359 /* Set up interrupt trigger */
360 reg = bank->eint_base + EINTCON_REG(bank->eint_offset);
361 shift = EINT_OFFS(bank->eint_offset) + irqd->hwirq;
362 shift = 4 * (shift / 4); /* 4 EINTs per trigger selector */
363
364 val = readl(reg);
365 val &= ~(EINT_CON_MASK << shift);
366 val |= trigger << shift;
367 writel(val, reg);
368
369 s3c64xx_irq_set_function(d, bank, irqd->hwirq);
370
371 return 0;
372 }
373
374 /*
375 * irq_chip for gpio interrupts.
376 */
377 static struct irq_chip s3c64xx_gpio_irq_chip = {
378 .name = "GPIO",
379 .irq_unmask = s3c64xx_gpio_irq_unmask,
380 .irq_mask = s3c64xx_gpio_irq_mask,
381 .irq_ack = s3c64xx_gpio_irq_ack,
382 .irq_set_type = s3c64xx_gpio_irq_set_type,
383 };
384
385 static int s3c64xx_gpio_irq_map(struct irq_domain *h, unsigned int virq,
386 irq_hw_number_t hw)
387 {
388 struct samsung_pin_bank *bank = h->host_data;
389
390 if (!(bank->eint_mask & (1 << hw)))
391 return -EINVAL;
392
393 irq_set_chip_and_handler(virq,
394 &s3c64xx_gpio_irq_chip, handle_level_irq);
395 irq_set_chip_data(virq, bank);
396
397 return 0;
398 }
399
400 /*
401 * irq domain callbacks for external gpio interrupt controller.
402 */
403 static const struct irq_domain_ops s3c64xx_gpio_irqd_ops = {
404 .map = s3c64xx_gpio_irq_map,
405 .xlate = irq_domain_xlate_twocell,
406 };
407
408 static void s3c64xx_eint_gpio_irq(struct irq_desc *desc)
409 {
410 struct irq_chip *chip = irq_desc_get_chip(desc);
411 struct s3c64xx_eint_gpio_data *data = irq_desc_get_handler_data(desc);
412 struct irq_data *irqd = irq_desc_get_irq_data(desc);
413 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
414
415 chained_irq_enter(chip, desc);
416
417 do {
418 unsigned int svc;
419 unsigned int group;
420 unsigned int pin;
421 unsigned int virq;
422
423 svc = readl(bank->eint_base + SERVICE_REG);
424 group = SVC_GROUP(svc);
425 pin = svc & SVC_NUM_MASK;
426
427 if (!group)
428 break;
429
430 /* Group 1 is used for two pin banks */
431 if (group == 1) {
432 if (pin < 8)
433 group = 0;
434 else
435 pin -= 8;
436 }
437
438 virq = irq_linear_revmap(data->domains[group], pin);
439 /*
440 * Something must be really wrong if an unmapped EINT
441 * was unmasked...
442 */
443 BUG_ON(!virq);
444
445 generic_handle_irq(virq);
446 } while (1);
447
448 chained_irq_exit(chip, desc);
449 }
450
451 /**
452 * s3c64xx_eint_gpio_init() - setup handling of external gpio interrupts.
453 * @d: driver data of samsung pinctrl driver.
454 */
455 static int s3c64xx_eint_gpio_init(struct samsung_pinctrl_drv_data *d)
456 {
457 struct s3c64xx_eint_gpio_data *data;
458 struct samsung_pin_bank *bank;
459 struct device *dev = d->dev;
460 unsigned int nr_domains;
461 unsigned int i;
462
463 if (!d->irq) {
464 dev_err(dev, "irq number not available\n");
465 return -EINVAL;
466 }
467
468 nr_domains = 0;
469 bank = d->pin_banks;
470 for (i = 0; i < d->nr_banks; ++i, ++bank) {
471 unsigned int nr_eints;
472 unsigned int mask;
473
474 if (bank->eint_type != EINT_TYPE_GPIO)
475 continue;
476
477 mask = bank->eint_mask;
478 nr_eints = fls(mask);
479
480 bank->irq_domain = irq_domain_add_linear(bank->of_node,
481 nr_eints, &s3c64xx_gpio_irqd_ops, bank);
482 if (!bank->irq_domain) {
483 dev_err(dev, "gpio irq domain add failed\n");
484 return -ENXIO;
485 }
486
487 ++nr_domains;
488 }
489
490 data = devm_kzalloc(dev, sizeof(*data)
491 + nr_domains * sizeof(*data->domains), GFP_KERNEL);
492 if (!data)
493 return -ENOMEM;
494 data->drvdata = d;
495
496 bank = d->pin_banks;
497 nr_domains = 0;
498 for (i = 0; i < d->nr_banks; ++i, ++bank) {
499 if (bank->eint_type != EINT_TYPE_GPIO)
500 continue;
501
502 data->domains[nr_domains++] = bank->irq_domain;
503 }
504
505 irq_set_chained_handler_and_data(d->irq, s3c64xx_eint_gpio_irq, data);
506
507 return 0;
508 }
509
510 /*
511 * Functions for configuration of EINT0 wake-up interrupts
512 */
513
514 static inline void s3c64xx_eint0_irq_set_mask(struct irq_data *irqd, bool mask)
515 {
516 struct s3c64xx_eint0_domain_data *ddata =
517 irq_data_get_irq_chip_data(irqd);
518 struct samsung_pin_bank *bank = ddata->bank;
519 u32 val;
520
521 val = readl(bank->eint_base + EINT0MASK_REG);
522 if (mask)
523 val |= 1 << ddata->eints[irqd->hwirq];
524 else
525 val &= ~(1 << ddata->eints[irqd->hwirq]);
526 writel(val, bank->eint_base + EINT0MASK_REG);
527 }
528
529 static void s3c64xx_eint0_irq_unmask(struct irq_data *irqd)
530 {
531 s3c64xx_eint0_irq_set_mask(irqd, false);
532 }
533
534 static void s3c64xx_eint0_irq_mask(struct irq_data *irqd)
535 {
536 s3c64xx_eint0_irq_set_mask(irqd, true);
537 }
538
539 static void s3c64xx_eint0_irq_ack(struct irq_data *irqd)
540 {
541 struct s3c64xx_eint0_domain_data *ddata =
542 irq_data_get_irq_chip_data(irqd);
543 struct samsung_pin_bank *bank = ddata->bank;
544
545 writel(1 << ddata->eints[irqd->hwirq],
546 bank->eint_base + EINT0PEND_REG);
547 }
548
549 static int s3c64xx_eint0_irq_set_type(struct irq_data *irqd, unsigned int type)
550 {
551 struct s3c64xx_eint0_domain_data *ddata =
552 irq_data_get_irq_chip_data(irqd);
553 struct samsung_pin_bank *bank = ddata->bank;
554 struct samsung_pinctrl_drv_data *d = ddata->bank->drvdata;
555 void __iomem *reg;
556 int trigger;
557 u8 shift;
558 u32 val;
559
560 trigger = s3c64xx_irq_get_trigger(type);
561 if (trigger < 0) {
562 pr_err("unsupported external interrupt type\n");
563 return -EINVAL;
564 }
565
566 s3c64xx_irq_set_handler(irqd, type);
567
568 /* Set up interrupt trigger */
569 reg = bank->eint_base + EINT0CON0_REG;
570 shift = ddata->eints[irqd->hwirq];
571 if (shift >= EINT_MAX_PER_REG) {
572 reg += 4;
573 shift -= EINT_MAX_PER_REG;
574 }
575 shift = EINT_CON_LEN * (shift / 2);
576
577 val = readl(reg);
578 val &= ~(EINT_CON_MASK << shift);
579 val |= trigger << shift;
580 writel(val, reg);
581
582 s3c64xx_irq_set_function(d, bank, irqd->hwirq);
583
584 return 0;
585 }
586
587 /*
588 * irq_chip for wakeup interrupts
589 */
590 static struct irq_chip s3c64xx_eint0_irq_chip = {
591 .name = "EINT0",
592 .irq_unmask = s3c64xx_eint0_irq_unmask,
593 .irq_mask = s3c64xx_eint0_irq_mask,
594 .irq_ack = s3c64xx_eint0_irq_ack,
595 .irq_set_type = s3c64xx_eint0_irq_set_type,
596 };
597
598 static inline void s3c64xx_irq_demux_eint(struct irq_desc *desc, u32 range)
599 {
600 struct irq_chip *chip = irq_desc_get_chip(desc);
601 struct irq_data *irqd = irq_desc_get_irq_data(desc);
602 struct s3c64xx_eint0_domain_data *ddata =
603 irq_data_get_irq_chip_data(irqd);
604 struct samsung_pin_bank *bank = ddata->bank;
605
606 struct s3c64xx_eint0_data *data = irq_desc_get_handler_data(desc);
607
608 unsigned int pend, mask;
609
610 chained_irq_enter(chip, desc);
611
612 pend = readl(bank->eint_base + EINT0PEND_REG);
613 mask = readl(bank->eint_base + EINT0MASK_REG);
614
615 pend = pend & range & ~mask;
616 pend &= range;
617
618 while (pend) {
619 unsigned int virq, irq;
620
621 irq = fls(pend) - 1;
622 pend &= ~(1 << irq);
623 virq = irq_linear_revmap(data->domains[irq], data->pins[irq]);
624 /*
625 * Something must be really wrong if an unmapped EINT
626 * was unmasked...
627 */
628 BUG_ON(!virq);
629
630 generic_handle_irq(virq);
631 }
632
633 chained_irq_exit(chip, desc);
634 }
635
636 static void s3c64xx_demux_eint0_3(struct irq_desc *desc)
637 {
638 s3c64xx_irq_demux_eint(desc, 0xf);
639 }
640
641 static void s3c64xx_demux_eint4_11(struct irq_desc *desc)
642 {
643 s3c64xx_irq_demux_eint(desc, 0xff0);
644 }
645
646 static void s3c64xx_demux_eint12_19(struct irq_desc *desc)
647 {
648 s3c64xx_irq_demux_eint(desc, 0xff000);
649 }
650
651 static void s3c64xx_demux_eint20_27(struct irq_desc *desc)
652 {
653 s3c64xx_irq_demux_eint(desc, 0xff00000);
654 }
655
656 static irq_flow_handler_t s3c64xx_eint0_handlers[NUM_EINT0_IRQ] = {
657 s3c64xx_demux_eint0_3,
658 s3c64xx_demux_eint4_11,
659 s3c64xx_demux_eint12_19,
660 s3c64xx_demux_eint20_27,
661 };
662
663 static int s3c64xx_eint0_irq_map(struct irq_domain *h, unsigned int virq,
664 irq_hw_number_t hw)
665 {
666 struct s3c64xx_eint0_domain_data *ddata = h->host_data;
667 struct samsung_pin_bank *bank = ddata->bank;
668
669 if (!(bank->eint_mask & (1 << hw)))
670 return -EINVAL;
671
672 irq_set_chip_and_handler(virq,
673 &s3c64xx_eint0_irq_chip, handle_level_irq);
674 irq_set_chip_data(virq, ddata);
675
676 return 0;
677 }
678
679 /*
680 * irq domain callbacks for external wakeup interrupt controller.
681 */
682 static const struct irq_domain_ops s3c64xx_eint0_irqd_ops = {
683 .map = s3c64xx_eint0_irq_map,
684 .xlate = irq_domain_xlate_twocell,
685 };
686
687 /* list of external wakeup controllers supported */
688 static const struct of_device_id s3c64xx_eint0_irq_ids[] = {
689 { .compatible = "samsung,s3c64xx-wakeup-eint", },
690 { }
691 };
692
693 /**
694 * s3c64xx_eint_eint0_init() - setup handling of external wakeup interrupts.
695 * @d: driver data of samsung pinctrl driver.
696 */
697 static int s3c64xx_eint_eint0_init(struct samsung_pinctrl_drv_data *d)
698 {
699 struct device *dev = d->dev;
700 struct device_node *eint0_np = NULL;
701 struct device_node *np;
702 struct samsung_pin_bank *bank;
703 struct s3c64xx_eint0_data *data;
704 unsigned int i;
705
706 for_each_child_of_node(dev->of_node, np) {
707 if (of_match_node(s3c64xx_eint0_irq_ids, np)) {
708 eint0_np = np;
709 break;
710 }
711 }
712 if (!eint0_np)
713 return -ENODEV;
714
715 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
716 if (!data)
717 return -ENOMEM;
718 data->drvdata = d;
719
720 for (i = 0; i < NUM_EINT0_IRQ; ++i) {
721 unsigned int irq;
722
723 irq = irq_of_parse_and_map(eint0_np, i);
724 if (!irq) {
725 dev_err(dev, "failed to get wakeup EINT IRQ %d\n", i);
726 return -ENXIO;
727 }
728
729 irq_set_chained_handler_and_data(irq,
730 s3c64xx_eint0_handlers[i],
731 data);
732 }
733
734 bank = d->pin_banks;
735 for (i = 0; i < d->nr_banks; ++i, ++bank) {
736 struct s3c64xx_eint0_domain_data *ddata;
737 unsigned int nr_eints;
738 unsigned int mask;
739 unsigned int irq;
740 unsigned int pin;
741
742 if (bank->eint_type != EINT_TYPE_WKUP)
743 continue;
744
745 mask = bank->eint_mask;
746 nr_eints = fls(mask);
747
748 ddata = devm_kzalloc(dev,
749 sizeof(*ddata) + nr_eints, GFP_KERNEL);
750 if (!ddata)
751 return -ENOMEM;
752 ddata->bank = bank;
753
754 bank->irq_domain = irq_domain_add_linear(bank->of_node,
755 nr_eints, &s3c64xx_eint0_irqd_ops, ddata);
756 if (!bank->irq_domain) {
757 dev_err(dev, "wkup irq domain add failed\n");
758 return -ENXIO;
759 }
760
761 irq = bank->eint_offset;
762 mask = bank->eint_mask;
763 for (pin = 0; mask; ++pin, mask >>= 1) {
764 if (!(mask & 1))
765 continue;
766 data->domains[irq] = bank->irq_domain;
767 data->pins[irq] = pin;
768 ddata->eints[pin] = irq;
769 ++irq;
770 }
771 }
772
773 return 0;
774 }
775
776 /* pin banks of s3c64xx pin-controller 0 */
777 static const struct samsung_pin_bank_data s3c64xx_pin_banks0[] __initconst = {
778 PIN_BANK_4BIT_EINTG(8, 0x000, "gpa", 0),
779 PIN_BANK_4BIT_EINTG(7, 0x020, "gpb", 8),
780 PIN_BANK_4BIT_EINTG(8, 0x040, "gpc", 16),
781 PIN_BANK_4BIT_EINTG(5, 0x060, "gpd", 32),
782 PIN_BANK_4BIT(5, 0x080, "gpe"),
783 PIN_BANK_2BIT_EINTG(16, 0x0a0, "gpf", 48, 0x3fff),
784 PIN_BANK_4BIT_EINTG(7, 0x0c0, "gpg", 64),
785 PIN_BANK_4BIT2_EINTG(10, 0x0e0, "gph", 80),
786 PIN_BANK_2BIT(16, 0x100, "gpi"),
787 PIN_BANK_2BIT(12, 0x120, "gpj"),
788 PIN_BANK_4BIT2_ALIVE(16, 0x800, "gpk"),
789 PIN_BANK_4BIT2_EINTW(15, 0x810, "gpl", 16, 0x7f00),
790 PIN_BANK_4BIT_EINTW(6, 0x820, "gpm", 23, 0x1f),
791 PIN_BANK_2BIT_EINTW(16, 0x830, "gpn", 0),
792 PIN_BANK_2BIT_EINTG(16, 0x140, "gpo", 96, 0xffff),
793 PIN_BANK_2BIT_EINTG(15, 0x160, "gpp", 112, 0x7fff),
794 PIN_BANK_2BIT_EINTG(9, 0x180, "gpq", 128, 0x1ff),
795 };
796
797 /*
798 * Samsung pinctrl driver data for S3C64xx SoC. S3C64xx SoC includes
799 * one gpio/pin-mux/pinconfig controller.
800 */
801 const struct samsung_pin_ctrl s3c64xx_pin_ctrl[] __initconst = {
802 {
803 /* pin-controller instance 1 data */
804 .pin_banks = s3c64xx_pin_banks0,
805 .nr_banks = ARRAY_SIZE(s3c64xx_pin_banks0),
806 .eint_gpio_init = s3c64xx_eint_gpio_init,
807 .eint_wkup_init = s3c64xx_eint_eint0_init,
808 },
809 };
Linux with added FPC-III support