2 * Open Host Controller Interface (OHCI) driver for USB.
4 * Maintainer: Alan Stern <stern@rowland.harvard.edu>
6 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
7 * (C) Copyright 2000-2004 David Brownell <dbrownell@users.sourceforge.net>
9 * [ Initialisation is based on Linus' ]
10 * [ uhci code and gregs ohci fragments ]
11 * [ (C) Copyright 1999 Linus Torvalds ]
12 * [ (C) Copyright 1999 Gregory P. Smith]
15 * OHCI is the main "non-Intel/VIA" standard for USB 1.1 host controller
16 * interfaces (though some non-x86 Intel chips use it). It supports
17 * smarter hardware than UHCI. A download link for the spec available
18 * through the http://www.usb.org website.
20 * This file is licenced under the GPL.
23 #include <linux/module.h>
24 #include <linux/moduleparam.h>
25 #include <linux/pci.h>
26 #include <linux/kernel.h>
27 #include <linux/delay.h>
28 #include <linux/ioport.h>
29 #include <linux/sched.h>
30 #include <linux/slab.h>
31 #include <linux/errno.h>
32 #include <linux/init.h>
33 #include <linux/timer.h>
34 #include <linux/list.h>
35 #include <linux/usb.h>
36 #include <linux/usb/otg.h>
37 #include <linux/usb/hcd.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/dmapool.h>
40 #include <linux/workqueue.h>
41 #include <linux/debugfs.h>
45 #include <asm/unaligned.h>
46 #include <asm/byteorder.h>
49 #define DRIVER_AUTHOR "Roman Weissgaerber, David Brownell"
50 #define DRIVER_DESC "USB 1.1 'Open' Host Controller (OHCI) Driver"
52 /*-------------------------------------------------------------------------*/
54 /* For initializing controller (mask in an HCFS mode too) */
55 #define OHCI_CONTROL_INIT OHCI_CTRL_CBSR
56 #define OHCI_INTR_INIT \
57 (OHCI_INTR_MIE | OHCI_INTR_RHSC | OHCI_INTR_UE \
58 | OHCI_INTR_RD | OHCI_INTR_WDH)
61 /* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */
65 #ifdef CONFIG_ARCH_OMAP
66 /* OMAP doesn't support IR (no SMM; not needed) */
70 /*-------------------------------------------------------------------------*/
72 static const char hcd_name
[] = "ohci_hcd";
74 #define STATECHANGE_DELAY msecs_to_jiffies(300)
75 #define IO_WATCHDOG_DELAY msecs_to_jiffies(275)
78 #include "pci-quirks.h"
80 static void ohci_dump(struct ohci_hcd
*ohci
);
81 static void ohci_stop(struct usb_hcd
*hcd
);
82 static void io_watchdog_func(unsigned long _ohci
);
91 * On architectures with edge-triggered interrupts we must never return
94 #if defined(CONFIG_SA1111) /* ... or other edge-triggered systems */
95 #define IRQ_NOTMINE IRQ_HANDLED
97 #define IRQ_NOTMINE IRQ_NONE
101 /* Some boards misreport power switching/overcurrent */
102 static bool distrust_firmware
= true;
103 module_param (distrust_firmware
, bool, 0);
104 MODULE_PARM_DESC (distrust_firmware
,
105 "true to distrust firmware power/overcurrent setup");
107 /* Some boards leave IR set wrongly, since they fail BIOS/SMM handshakes */
108 static bool no_handshake
;
109 module_param (no_handshake
, bool, 0);
110 MODULE_PARM_DESC (no_handshake
, "true (not default) disables BIOS handshake");
112 /*-------------------------------------------------------------------------*/
114 static int number_of_tds(struct urb
*urb
)
116 int len
, i
, num
, this_sg_len
;
117 struct scatterlist
*sg
;
119 len
= urb
->transfer_buffer_length
;
120 i
= urb
->num_mapped_sgs
;
122 if (len
> 0 && i
> 0) { /* Scatter-gather transfer */
126 this_sg_len
= min_t(int, sg_dma_len(sg
), len
);
127 num
+= DIV_ROUND_UP(this_sg_len
, 4096);
129 if (--i
<= 0 || len
<= 0)
134 } else { /* Non-SG transfer */
135 /* one TD for every 4096 Bytes (could be up to 8K) */
136 num
= DIV_ROUND_UP(len
, 4096);
142 * queue up an urb for anything except the root hub
144 static int ohci_urb_enqueue (
149 struct ohci_hcd
*ohci
= hcd_to_ohci (hcd
);
151 urb_priv_t
*urb_priv
;
152 unsigned int pipe
= urb
->pipe
;
157 /* every endpoint has a ed, locate and maybe (re)initialize it */
158 ed
= ed_get(ohci
, urb
->ep
, urb
->dev
, pipe
, urb
->interval
);
162 /* for the private part of the URB we need the number of TDs (size) */
165 /* td_submit_urb() doesn't yet handle these */
166 if (urb
->transfer_buffer_length
> 4096)
169 /* 1 TD for setup, 1 for ACK, plus ... */
172 // case PIPE_INTERRUPT:
175 size
+= number_of_tds(urb
);
176 /* maybe a zero-length packet to wrap it up */
179 else if ((urb
->transfer_flags
& URB_ZERO_PACKET
) != 0
180 && (urb
->transfer_buffer_length
181 % usb_maxpacket (urb
->dev
, pipe
,
182 usb_pipeout (pipe
))) == 0)
185 case PIPE_ISOCHRONOUS
: /* number of packets from URB */
186 size
= urb
->number_of_packets
;
190 /* allocate the private part of the URB */
191 urb_priv
= kzalloc (sizeof (urb_priv_t
) + size
* sizeof (struct td
*),
195 INIT_LIST_HEAD (&urb_priv
->pending
);
196 urb_priv
->length
= size
;
199 /* allocate the TDs (deferring hash chain updates) */
200 for (i
= 0; i
< size
; i
++) {
201 urb_priv
->td
[i
] = td_alloc (ohci
, mem_flags
);
202 if (!urb_priv
->td
[i
]) {
203 urb_priv
->length
= i
;
204 urb_free_priv (ohci
, urb_priv
);
209 spin_lock_irqsave (&ohci
->lock
, flags
);
211 /* don't submit to a dead HC */
212 if (!HCD_HW_ACCESSIBLE(hcd
)) {
216 if (ohci
->rh_state
!= OHCI_RH_RUNNING
) {
220 retval
= usb_hcd_link_urb_to_ep(hcd
, urb
);
224 /* schedule the ed if needed */
225 if (ed
->state
== ED_IDLE
) {
226 retval
= ed_schedule (ohci
, ed
);
228 usb_hcd_unlink_urb_from_ep(hcd
, urb
);
232 /* Start up the I/O watchdog timer, if it's not running */
233 if (!timer_pending(&ohci
->io_watchdog
) &&
234 list_empty(&ohci
->eds_in_use
) &&
235 !(ohci
->flags
& OHCI_QUIRK_QEMU
)) {
236 ohci
->prev_frame_no
= ohci_frame_no(ohci
);
237 mod_timer(&ohci
->io_watchdog
,
238 jiffies
+ IO_WATCHDOG_DELAY
);
240 list_add(&ed
->in_use_list
, &ohci
->eds_in_use
);
242 if (ed
->type
== PIPE_ISOCHRONOUS
) {
243 u16 frame
= ohci_frame_no(ohci
);
245 /* delay a few frames before the first TD */
246 frame
+= max_t (u16
, 8, ed
->interval
);
247 frame
&= ~(ed
->interval
- 1);
249 urb
->start_frame
= frame
;
250 ed
->last_iso
= frame
+ ed
->interval
* (size
- 1);
252 } else if (ed
->type
== PIPE_ISOCHRONOUS
) {
253 u16 next
= ohci_frame_no(ohci
) + 1;
254 u16 frame
= ed
->last_iso
+ ed
->interval
;
255 u16 length
= ed
->interval
* (size
- 1);
257 /* Behind the scheduling threshold? */
258 if (unlikely(tick_before(frame
, next
))) {
260 /* URB_ISO_ASAP: Round up to the first available slot */
261 if (urb
->transfer_flags
& URB_ISO_ASAP
) {
262 frame
+= (next
- frame
+ ed
->interval
- 1) &
266 * Not ASAP: Use the next slot in the stream,
271 * Some OHCI hardware doesn't handle late TDs
272 * correctly. After retiring them it proceeds
273 * to the next ED instead of the next TD.
274 * Therefore we have to omit the late TDs
277 urb_priv
->td_cnt
= DIV_ROUND_UP(
278 (u16
) (next
- frame
),
280 if (urb_priv
->td_cnt
>= urb_priv
->length
) {
281 ++urb_priv
->td_cnt
; /* Mark it */
282 ohci_dbg(ohci
, "iso underrun %p (%u+%u < %u)\n",
288 urb
->start_frame
= frame
;
289 ed
->last_iso
= frame
+ length
;
292 /* fill the TDs and link them to the ed; and
293 * enable that part of the schedule, if needed
294 * and update count of queued periodic urbs
296 urb
->hcpriv
= urb_priv
;
297 td_submit_urb (ohci
, urb
);
301 urb_free_priv (ohci
, urb_priv
);
302 spin_unlock_irqrestore (&ohci
->lock
, flags
);
307 * decouple the URB from the HC queues (TDs, urb_priv).
308 * reporting is always done
309 * asynchronously, and we might be dealing with an urb that's
310 * partially transferred, or an ED with other urbs being unlinked.
312 static int ohci_urb_dequeue(struct usb_hcd
*hcd
, struct urb
*urb
, int status
)
314 struct ohci_hcd
*ohci
= hcd_to_ohci (hcd
);
317 urb_priv_t
*urb_priv
;
319 spin_lock_irqsave (&ohci
->lock
, flags
);
320 rc
= usb_hcd_check_unlink_urb(hcd
, urb
, status
);
323 /* Unless an IRQ completed the unlink while it was being
324 * handed to us, flag it for unlink and giveback, and force
325 * some upcoming INTR_SF to call finish_unlinks()
327 urb_priv
= urb
->hcpriv
;
328 if (urb_priv
->ed
->state
== ED_OPER
)
329 start_ed_unlink(ohci
, urb_priv
->ed
);
331 if (ohci
->rh_state
!= OHCI_RH_RUNNING
) {
332 /* With HC dead, we can clean up right away */
336 spin_unlock_irqrestore (&ohci
->lock
, flags
);
340 /*-------------------------------------------------------------------------*/
342 /* frees config/altsetting state for endpoints,
343 * including ED memory, dummy TD, and bulk/intr data toggle
347 ohci_endpoint_disable (struct usb_hcd
*hcd
, struct usb_host_endpoint
*ep
)
349 struct ohci_hcd
*ohci
= hcd_to_ohci (hcd
);
351 struct ed
*ed
= ep
->hcpriv
;
352 unsigned limit
= 1000;
354 /* ASSERT: any requests/urbs are being unlinked */
355 /* ASSERT: nobody can be submitting urbs for this any more */
361 spin_lock_irqsave (&ohci
->lock
, flags
);
363 if (ohci
->rh_state
!= OHCI_RH_RUNNING
) {
370 case ED_UNLINK
: /* wait for hw to finish? */
371 /* major IRQ delivery trouble loses INTR_SF too... */
373 ohci_warn(ohci
, "ED unlink timeout\n");
376 spin_unlock_irqrestore (&ohci
->lock
, flags
);
377 schedule_timeout_uninterruptible(1);
379 case ED_IDLE
: /* fully unlinked */
380 if (list_empty (&ed
->td_list
)) {
381 td_free (ohci
, ed
->dummy
);
385 /* else FALL THROUGH */
387 /* caller was supposed to have unlinked any requests;
388 * that's not our job. can't recover; must leak ed.
390 ohci_err (ohci
, "leak ed %p (#%02x) state %d%s\n",
391 ed
, ep
->desc
.bEndpointAddress
, ed
->state
,
392 list_empty (&ed
->td_list
) ? "" : " (has tds)");
393 td_free (ohci
, ed
->dummy
);
397 spin_unlock_irqrestore (&ohci
->lock
, flags
);
400 static int ohci_get_frame (struct usb_hcd
*hcd
)
402 struct ohci_hcd
*ohci
= hcd_to_ohci (hcd
);
404 return ohci_frame_no(ohci
);
407 static void ohci_usb_reset (struct ohci_hcd
*ohci
)
409 ohci
->hc_control
= ohci_readl (ohci
, &ohci
->regs
->control
);
410 ohci
->hc_control
&= OHCI_CTRL_RWC
;
411 ohci_writel (ohci
, ohci
->hc_control
, &ohci
->regs
->control
);
412 ohci
->rh_state
= OHCI_RH_HALTED
;
415 /* ohci_shutdown forcibly disables IRQs and DMA, helping kexec and
416 * other cases where the next software may expect clean state from the
417 * "firmware". this is bus-neutral, unlike shutdown() methods.
420 ohci_shutdown (struct usb_hcd
*hcd
)
422 struct ohci_hcd
*ohci
;
424 ohci
= hcd_to_ohci (hcd
);
425 ohci_writel(ohci
, (u32
) ~0, &ohci
->regs
->intrdisable
);
427 /* Software reset, after which the controller goes into SUSPEND */
428 ohci_writel(ohci
, OHCI_HCR
, &ohci
->regs
->cmdstatus
);
429 ohci_readl(ohci
, &ohci
->regs
->cmdstatus
); /* flush the writes */
432 ohci_writel(ohci
, ohci
->fminterval
, &ohci
->regs
->fminterval
);
433 ohci
->rh_state
= OHCI_RH_HALTED
;
436 /*-------------------------------------------------------------------------*
438 *-------------------------------------------------------------------------*/
440 /* init memory, and kick BIOS/SMM off */
442 static int ohci_init (struct ohci_hcd
*ohci
)
445 struct usb_hcd
*hcd
= ohci_to_hcd(ohci
);
447 /* Accept arbitrarily long scatter-gather lists */
448 hcd
->self
.sg_tablesize
= ~0;
450 if (distrust_firmware
)
451 ohci
->flags
|= OHCI_QUIRK_HUB_POWER
;
453 ohci
->rh_state
= OHCI_RH_HALTED
;
454 ohci
->regs
= hcd
->regs
;
456 /* REVISIT this BIOS handshake is now moved into PCI "quirks", and
457 * was never needed for most non-PCI systems ... remove the code?
461 /* SMM owns the HC? not for long! */
462 if (!no_handshake
&& ohci_readl (ohci
,
463 &ohci
->regs
->control
) & OHCI_CTRL_IR
) {
466 ohci_dbg (ohci
, "USB HC TakeOver from BIOS/SMM\n");
468 /* this timeout is arbitrary. we make it long, so systems
469 * depending on usb keyboards may be usable even if the
470 * BIOS/SMM code seems pretty broken.
472 temp
= 500; /* arbitrary: five seconds */
474 ohci_writel (ohci
, OHCI_INTR_OC
, &ohci
->regs
->intrenable
);
475 ohci_writel (ohci
, OHCI_OCR
, &ohci
->regs
->cmdstatus
);
476 while (ohci_readl (ohci
, &ohci
->regs
->control
) & OHCI_CTRL_IR
) {
479 ohci_err (ohci
, "USB HC takeover failed!"
480 " (BIOS/SMM bug)\n");
484 ohci_usb_reset (ohci
);
488 /* Disable HC interrupts */
489 ohci_writel (ohci
, OHCI_INTR_MIE
, &ohci
->regs
->intrdisable
);
491 /* flush the writes, and save key bits like RWC */
492 if (ohci_readl (ohci
, &ohci
->regs
->control
) & OHCI_CTRL_RWC
)
493 ohci
->hc_control
|= OHCI_CTRL_RWC
;
495 /* Read the number of ports unless overridden */
496 if (ohci
->num_ports
== 0)
497 ohci
->num_ports
= roothub_a(ohci
) & RH_A_NDP
;
502 setup_timer(&ohci
->io_watchdog
, io_watchdog_func
,
503 (unsigned long) ohci
);
505 ohci
->hcca
= dma_alloc_coherent (hcd
->self
.controller
,
506 sizeof(*ohci
->hcca
), &ohci
->hcca_dma
, GFP_KERNEL
);
510 if ((ret
= ohci_mem_init (ohci
)) < 0)
513 create_debug_files (ohci
);
519 /*-------------------------------------------------------------------------*/
521 /* Start an OHCI controller, set the BUS operational
522 * resets USB and controller
525 static int ohci_run (struct ohci_hcd
*ohci
)
528 int first
= ohci
->fminterval
== 0;
529 struct usb_hcd
*hcd
= ohci_to_hcd(ohci
);
531 ohci
->rh_state
= OHCI_RH_HALTED
;
533 /* boot firmware should have set this up (5.1.1.3.1) */
536 val
= ohci_readl (ohci
, &ohci
->regs
->fminterval
);
537 ohci
->fminterval
= val
& 0x3fff;
538 if (ohci
->fminterval
!= FI
)
539 ohci_dbg (ohci
, "fminterval delta %d\n",
540 ohci
->fminterval
- FI
);
541 ohci
->fminterval
|= FSMP (ohci
->fminterval
) << 16;
542 /* also: power/overcurrent flags in roothub.a */
545 /* Reset USB nearly "by the book". RemoteWakeupConnected has
546 * to be checked in case boot firmware (BIOS/SMM/...) has set up
547 * wakeup in a way the bus isn't aware of (e.g., legacy PCI PM).
548 * If the bus glue detected wakeup capability then it should
549 * already be enabled; if so we'll just enable it again.
551 if ((ohci
->hc_control
& OHCI_CTRL_RWC
) != 0)
552 device_set_wakeup_capable(hcd
->self
.controller
, 1);
554 switch (ohci
->hc_control
& OHCI_CTRL_HCFS
) {
558 case OHCI_USB_SUSPEND
:
559 case OHCI_USB_RESUME
:
560 ohci
->hc_control
&= OHCI_CTRL_RWC
;
561 ohci
->hc_control
|= OHCI_USB_RESUME
;
562 val
= 10 /* msec wait */;
564 // case OHCI_USB_RESET:
566 ohci
->hc_control
&= OHCI_CTRL_RWC
;
567 ohci
->hc_control
|= OHCI_USB_RESET
;
568 val
= 50 /* msec wait */;
571 ohci_writel (ohci
, ohci
->hc_control
, &ohci
->regs
->control
);
573 (void) ohci_readl (ohci
, &ohci
->regs
->control
);
576 memset (ohci
->hcca
, 0, sizeof (struct ohci_hcca
));
578 /* 2msec timelimit here means no irqs/preempt */
579 spin_lock_irq (&ohci
->lock
);
582 /* HC Reset requires max 10 us delay */
583 ohci_writel (ohci
, OHCI_HCR
, &ohci
->regs
->cmdstatus
);
584 val
= 30; /* ... allow extra time */
585 while ((ohci_readl (ohci
, &ohci
->regs
->cmdstatus
) & OHCI_HCR
) != 0) {
587 spin_unlock_irq (&ohci
->lock
);
588 ohci_err (ohci
, "USB HC reset timed out!\n");
594 /* now we're in the SUSPEND state ... must go OPERATIONAL
595 * within 2msec else HC enters RESUME
597 * ... but some hardware won't init fmInterval "by the book"
598 * (SiS, OPTi ...), so reset again instead. SiS doesn't need
599 * this if we write fmInterval after we're OPERATIONAL.
600 * Unclear about ALi, ServerWorks, and others ... this could
601 * easily be a longstanding bug in chip init on Linux.
603 if (ohci
->flags
& OHCI_QUIRK_INITRESET
) {
604 ohci_writel (ohci
, ohci
->hc_control
, &ohci
->regs
->control
);
605 // flush those writes
606 (void) ohci_readl (ohci
, &ohci
->regs
->control
);
609 /* Tell the controller where the control and bulk lists are
610 * The lists are empty now. */
611 ohci_writel (ohci
, 0, &ohci
->regs
->ed_controlhead
);
612 ohci_writel (ohci
, 0, &ohci
->regs
->ed_bulkhead
);
614 /* a reset clears this */
615 ohci_writel (ohci
, (u32
) ohci
->hcca_dma
, &ohci
->regs
->hcca
);
617 periodic_reinit (ohci
);
619 /* some OHCI implementations are finicky about how they init.
620 * bogus values here mean not even enumeration could work.
622 if ((ohci_readl (ohci
, &ohci
->regs
->fminterval
) & 0x3fff0000) == 0
623 || !ohci_readl (ohci
, &ohci
->regs
->periodicstart
)) {
624 if (!(ohci
->flags
& OHCI_QUIRK_INITRESET
)) {
625 ohci
->flags
|= OHCI_QUIRK_INITRESET
;
626 ohci_dbg (ohci
, "enabling initreset quirk\n");
629 spin_unlock_irq (&ohci
->lock
);
630 ohci_err (ohci
, "init err (%08x %04x)\n",
631 ohci_readl (ohci
, &ohci
->regs
->fminterval
),
632 ohci_readl (ohci
, &ohci
->regs
->periodicstart
));
636 /* use rhsc irqs after hub_wq is allocated */
637 set_bit(HCD_FLAG_POLL_RH
, &hcd
->flags
);
638 hcd
->uses_new_polling
= 1;
640 /* start controller operations */
641 ohci
->hc_control
&= OHCI_CTRL_RWC
;
642 ohci
->hc_control
|= OHCI_CONTROL_INIT
| OHCI_USB_OPER
;
643 ohci_writel (ohci
, ohci
->hc_control
, &ohci
->regs
->control
);
644 ohci
->rh_state
= OHCI_RH_RUNNING
;
646 /* wake on ConnectStatusChange, matching external hubs */
647 ohci_writel (ohci
, RH_HS_DRWE
, &ohci
->regs
->roothub
.status
);
649 /* Choose the interrupts we care about now, others later on demand */
650 mask
= OHCI_INTR_INIT
;
651 ohci_writel (ohci
, ~0, &ohci
->regs
->intrstatus
);
652 ohci_writel (ohci
, mask
, &ohci
->regs
->intrenable
);
654 /* handle root hub init quirks ... */
655 val
= roothub_a (ohci
);
656 val
&= ~(RH_A_PSM
| RH_A_OCPM
);
657 if (ohci
->flags
& OHCI_QUIRK_SUPERIO
) {
658 /* NSC 87560 and maybe others */
660 val
&= ~(RH_A_POTPGT
| RH_A_NPS
);
661 ohci_writel (ohci
, val
, &ohci
->regs
->roothub
.a
);
662 } else if ((ohci
->flags
& OHCI_QUIRK_AMD756
) ||
663 (ohci
->flags
& OHCI_QUIRK_HUB_POWER
)) {
664 /* hub power always on; required for AMD-756 and some
665 * Mac platforms. ganged overcurrent reporting, if any.
668 ohci_writel (ohci
, val
, &ohci
->regs
->roothub
.a
);
670 ohci_writel (ohci
, RH_HS_LPSC
, &ohci
->regs
->roothub
.status
);
671 ohci_writel (ohci
, (val
& RH_A_NPS
) ? 0 : RH_B_PPCM
,
672 &ohci
->regs
->roothub
.b
);
673 // flush those writes
674 (void) ohci_readl (ohci
, &ohci
->regs
->control
);
676 ohci
->next_statechange
= jiffies
+ STATECHANGE_DELAY
;
677 spin_unlock_irq (&ohci
->lock
);
679 // POTPGT delay is bits 24-31, in 2 ms units.
680 mdelay ((val
>> 23) & 0x1fe);
687 /* ohci_setup routine for generic controller initialization */
689 int ohci_setup(struct usb_hcd
*hcd
)
691 struct ohci_hcd
*ohci
= hcd_to_ohci(hcd
);
695 return ohci_init(ohci
);
697 EXPORT_SYMBOL_GPL(ohci_setup
);
699 /* ohci_start routine for generic controller start of all OHCI bus glue */
700 static int ohci_start(struct usb_hcd
*hcd
)
702 struct ohci_hcd
*ohci
= hcd_to_ohci(hcd
);
705 ret
= ohci_run(ohci
);
707 ohci_err(ohci
, "can't start\n");
713 /*-------------------------------------------------------------------------*/
716 * Some OHCI controllers are known to lose track of completed TDs. They
717 * don't add the TDs to the hardware done queue, which means we never see
718 * them as being completed.
720 * This watchdog routine checks for such problems. Without some way to
721 * tell when those TDs have completed, we would never take their EDs off
722 * the unlink list. As a result, URBs could never be dequeued and
723 * endpoints could never be released.
725 static void io_watchdog_func(unsigned long _ohci
)
727 struct ohci_hcd
*ohci
= (struct ohci_hcd
*) _ohci
;
728 bool takeback_all_pending
= false;
732 struct td
*td
, *td_start
, *td_next
;
736 spin_lock_irqsave(&ohci
->lock
, flags
);
739 * One way to lose track of completed TDs is if the controller
740 * never writes back the done queue head. If it hasn't been
741 * written back since the last time this function ran and if it
742 * was non-empty at that time, something is badly wrong with the
745 status
= ohci_readl(ohci
, &ohci
->regs
->intrstatus
);
746 if (!(status
& OHCI_INTR_WDH
) && ohci
->wdh_cnt
== ohci
->prev_wdh_cnt
) {
747 if (ohci
->prev_donehead
) {
748 ohci_err(ohci
, "HcDoneHead not written back; disabled\n");
750 usb_hc_died(ohci_to_hcd(ohci
));
752 ohci_shutdown(ohci_to_hcd(ohci
));
755 /* No write back because the done queue was empty */
756 takeback_all_pending
= true;
760 /* Check every ED which might have pending TDs */
761 list_for_each_entry(ed
, &ohci
->eds_in_use
, in_use_list
) {
762 if (ed
->pending_td
) {
763 if (takeback_all_pending
||
764 OKAY_TO_TAKEBACK(ohci
, ed
)) {
765 unsigned tmp
= hc32_to_cpu(ohci
, ed
->hwINFO
);
767 ohci_dbg(ohci
, "takeback pending TD for dev %d ep 0x%x\n",
769 (0x000f & (tmp
>> 7)) +
770 ((tmp
& ED_IN
) >> 5));
771 add_to_done_list(ohci
, ed
->pending_td
);
775 /* Starting from the latest pending TD, */
778 /* or the last TD on the done list, */
780 list_for_each_entry(td_next
, &ed
->td_list
, td_list
) {
781 if (!td_next
->next_dl_td
)
787 /* find the last TD processed by the controller. */
788 head
= hc32_to_cpu(ohci
, ACCESS_ONCE(ed
->hwHeadP
)) & TD_MASK
;
790 td_next
= list_prepare_entry(td
, &ed
->td_list
, td_list
);
791 list_for_each_entry_continue(td_next
, &ed
->td_list
, td_list
) {
792 if (head
== (u32
) td_next
->td_dma
)
794 td
= td_next
; /* head pointer has passed this TD */
796 if (td
!= td_start
) {
798 * In case a WDH cycle is in progress, we will wait
799 * for the next two cycles to complete before assuming
800 * this TD will never get on the done queue.
802 ed
->takeback_wdh_cnt
= ohci
->wdh_cnt
+ 2;
809 if (ohci
->rh_state
== OHCI_RH_RUNNING
) {
812 * Sometimes a controller just stops working. We can tell
813 * by checking that the frame counter has advanced since
814 * the last time we ran.
816 * But be careful: Some controllers violate the spec by
817 * stopping their frame counter when no ports are active.
819 frame_no
= ohci_frame_no(ohci
);
820 if (frame_no
== ohci
->prev_frame_no
) {
825 for (i
= 0; i
< ohci
->num_ports
; ++i
) {
826 tmp
= roothub_portstatus(ohci
, i
);
827 /* Enabled and not suspended? */
828 if ((tmp
& RH_PS_PES
) && !(tmp
& RH_PS_PSS
))
832 if (active_cnt
> 0) {
833 ohci_err(ohci
, "frame counter not updating; disabled\n");
837 if (!list_empty(&ohci
->eds_in_use
)) {
838 ohci
->prev_frame_no
= frame_no
;
839 ohci
->prev_wdh_cnt
= ohci
->wdh_cnt
;
840 ohci
->prev_donehead
= ohci_readl(ohci
,
841 &ohci
->regs
->donehead
);
842 mod_timer(&ohci
->io_watchdog
,
843 jiffies
+ IO_WATCHDOG_DELAY
);
848 spin_unlock_irqrestore(&ohci
->lock
, flags
);
851 /* an interrupt happens */
853 static irqreturn_t
ohci_irq (struct usb_hcd
*hcd
)
855 struct ohci_hcd
*ohci
= hcd_to_ohci (hcd
);
856 struct ohci_regs __iomem
*regs
= ohci
->regs
;
859 /* Read interrupt status (and flush pending writes). We ignore the
860 * optimization of checking the LSB of hcca->done_head; it doesn't
861 * work on all systems (edge triggering for OHCI can be a factor).
863 ints
= ohci_readl(ohci
, ®s
->intrstatus
);
865 /* Check for an all 1's result which is a typical consequence
866 * of dead, unclocked, or unplugged (CardBus...) devices
868 if (ints
== ~(u32
)0) {
869 ohci
->rh_state
= OHCI_RH_HALTED
;
870 ohci_dbg (ohci
, "device removed!\n");
875 /* We only care about interrupts that are enabled */
876 ints
&= ohci_readl(ohci
, ®s
->intrenable
);
878 /* interrupt for some other device? */
879 if (ints
== 0 || unlikely(ohci
->rh_state
== OHCI_RH_HALTED
))
882 if (ints
& OHCI_INTR_UE
) {
883 // e.g. due to PCI Master/Target Abort
884 if (quirk_nec(ohci
)) {
885 /* Workaround for a silicon bug in some NEC chips used
886 * in Apple's PowerBooks. Adapted from Darwin code.
888 ohci_err (ohci
, "OHCI Unrecoverable Error, scheduling NEC chip restart\n");
890 ohci_writel (ohci
, OHCI_INTR_UE
, ®s
->intrdisable
);
892 schedule_work (&ohci
->nec_work
);
894 ohci_err (ohci
, "OHCI Unrecoverable Error, disabled\n");
895 ohci
->rh_state
= OHCI_RH_HALTED
;
900 ohci_usb_reset (ohci
);
903 if (ints
& OHCI_INTR_RHSC
) {
904 ohci_dbg(ohci
, "rhsc\n");
905 ohci
->next_statechange
= jiffies
+ STATECHANGE_DELAY
;
906 ohci_writel(ohci
, OHCI_INTR_RD
| OHCI_INTR_RHSC
,
909 /* NOTE: Vendors didn't always make the same implementation
910 * choices for RHSC. Many followed the spec; RHSC triggers
911 * on an edge, like setting and maybe clearing a port status
912 * change bit. With others it's level-triggered, active
913 * until hub_wq clears all the port status change bits. We'll
914 * always disable it here and rely on polling until hub_wq
917 ohci_writel(ohci
, OHCI_INTR_RHSC
, ®s
->intrdisable
);
918 usb_hcd_poll_rh_status(hcd
);
921 /* For connect and disconnect events, we expect the controller
922 * to turn on RHSC along with RD. But for remote wakeup events
923 * this might not happen.
925 else if (ints
& OHCI_INTR_RD
) {
926 ohci_dbg(ohci
, "resume detect\n");
927 ohci_writel(ohci
, OHCI_INTR_RD
, ®s
->intrstatus
);
928 set_bit(HCD_FLAG_POLL_RH
, &hcd
->flags
);
929 if (ohci
->autostop
) {
930 spin_lock (&ohci
->lock
);
931 ohci_rh_resume (ohci
);
932 spin_unlock (&ohci
->lock
);
934 usb_hcd_resume_root_hub(hcd
);
937 spin_lock(&ohci
->lock
);
938 if (ints
& OHCI_INTR_WDH
)
939 update_done_list(ohci
);
941 /* could track INTR_SO to reduce available PCI/... bandwidth */
943 /* handle any pending URB/ED unlinks, leaving INTR_SF enabled
944 * when there's still unlinking to be done (next frame).
947 if ((ints
& OHCI_INTR_SF
) != 0 && !ohci
->ed_rm_list
948 && ohci
->rh_state
== OHCI_RH_RUNNING
)
949 ohci_writel (ohci
, OHCI_INTR_SF
, ®s
->intrdisable
);
951 if (ohci
->rh_state
== OHCI_RH_RUNNING
) {
952 ohci_writel (ohci
, ints
, ®s
->intrstatus
);
953 if (ints
& OHCI_INTR_WDH
)
956 ohci_writel (ohci
, OHCI_INTR_MIE
, ®s
->intrenable
);
957 // flush those writes
958 (void) ohci_readl (ohci
, &ohci
->regs
->control
);
960 spin_unlock(&ohci
->lock
);
965 /*-------------------------------------------------------------------------*/
967 static void ohci_stop (struct usb_hcd
*hcd
)
969 struct ohci_hcd
*ohci
= hcd_to_ohci (hcd
);
974 flush_work(&ohci
->nec_work
);
975 del_timer_sync(&ohci
->io_watchdog
);
977 ohci_writel (ohci
, OHCI_INTR_MIE
, &ohci
->regs
->intrdisable
);
978 ohci_usb_reset(ohci
);
979 free_irq(hcd
->irq
, hcd
);
982 if (quirk_amdiso(ohci
))
985 remove_debug_files (ohci
);
986 ohci_mem_cleanup (ohci
);
988 dma_free_coherent (hcd
->self
.controller
,
990 ohci
->hcca
, ohci
->hcca_dma
);
996 /*-------------------------------------------------------------------------*/
998 #if defined(CONFIG_PM) || defined(CONFIG_USB_PCI)
1000 /* must not be called from interrupt context */
1001 int ohci_restart(struct ohci_hcd
*ohci
)
1005 struct urb_priv
*priv
;
1008 spin_lock_irq(&ohci
->lock
);
1009 ohci
->rh_state
= OHCI_RH_HALTED
;
1011 /* Recycle any "live" eds/tds (and urbs). */
1012 if (!list_empty (&ohci
->pending
))
1013 ohci_dbg(ohci
, "abort schedule...\n");
1014 list_for_each_entry (priv
, &ohci
->pending
, pending
) {
1015 struct urb
*urb
= priv
->td
[0]->urb
;
1016 struct ed
*ed
= priv
->ed
;
1018 switch (ed
->state
) {
1020 ed
->state
= ED_UNLINK
;
1021 ed
->hwINFO
|= cpu_to_hc32(ohci
, ED_DEQUEUE
);
1022 ed_deschedule (ohci
, ed
);
1024 ed
->ed_next
= ohci
->ed_rm_list
;
1026 ohci
->ed_rm_list
= ed
;
1031 ohci_dbg(ohci
, "bogus ed %p state %d\n",
1036 urb
->unlinked
= -ESHUTDOWN
;
1039 spin_unlock_irq(&ohci
->lock
);
1041 /* paranoia, in case that didn't work: */
1043 /* empty the interrupt branches */
1044 for (i
= 0; i
< NUM_INTS
; i
++) ohci
->load
[i
] = 0;
1045 for (i
= 0; i
< NUM_INTS
; i
++) ohci
->hcca
->int_table
[i
] = 0;
1047 /* no EDs to remove */
1048 ohci
->ed_rm_list
= NULL
;
1050 /* empty control and bulk lists */
1051 ohci
->ed_controltail
= NULL
;
1052 ohci
->ed_bulktail
= NULL
;
1054 if ((temp
= ohci_run (ohci
)) < 0) {
1055 ohci_err (ohci
, "can't restart, %d\n", temp
);
1058 ohci_dbg(ohci
, "restart complete\n");
1061 EXPORT_SYMBOL_GPL(ohci_restart
);
1067 int ohci_suspend(struct usb_hcd
*hcd
, bool do_wakeup
)
1069 struct ohci_hcd
*ohci
= hcd_to_ohci (hcd
);
1070 unsigned long flags
;
1073 /* Disable irq emission and mark HW unaccessible. Use
1074 * the spinlock to properly synchronize with possible pending
1075 * RH suspend or resume activity.
1077 spin_lock_irqsave (&ohci
->lock
, flags
);
1078 ohci_writel(ohci
, OHCI_INTR_MIE
, &ohci
->regs
->intrdisable
);
1079 (void)ohci_readl(ohci
, &ohci
->regs
->intrdisable
);
1081 clear_bit(HCD_FLAG_HW_ACCESSIBLE
, &hcd
->flags
);
1082 spin_unlock_irqrestore (&ohci
->lock
, flags
);
1084 synchronize_irq(hcd
->irq
);
1086 if (do_wakeup
&& HCD_WAKEUP_PENDING(hcd
)) {
1087 ohci_resume(hcd
, false);
1092 EXPORT_SYMBOL_GPL(ohci_suspend
);
1095 int ohci_resume(struct usb_hcd
*hcd
, bool hibernated
)
1097 struct ohci_hcd
*ohci
= hcd_to_ohci(hcd
);
1099 bool need_reinit
= false;
1101 set_bit(HCD_FLAG_HW_ACCESSIBLE
, &hcd
->flags
);
1103 /* Make sure resume from hibernation re-enumerates everything */
1105 ohci_usb_reset(ohci
);
1107 /* See if the controller is already running or has been reset */
1108 ohci
->hc_control
= ohci_readl(ohci
, &ohci
->regs
->control
);
1109 if (ohci
->hc_control
& (OHCI_CTRL_IR
| OHCI_SCHED_ENABLES
)) {
1112 switch (ohci
->hc_control
& OHCI_CTRL_HCFS
) {
1114 case OHCI_USB_RESET
:
1119 /* If needed, reinitialize and suspend the root hub */
1121 spin_lock_irq(&ohci
->lock
);
1122 ohci_rh_resume(ohci
);
1123 ohci_rh_suspend(ohci
, 0);
1124 spin_unlock_irq(&ohci
->lock
);
1127 /* Normally just turn on port power and enable interrupts */
1129 ohci_dbg(ohci
, "powerup ports\n");
1130 for (port
= 0; port
< ohci
->num_ports
; port
++)
1131 ohci_writel(ohci
, RH_PS_PPS
,
1132 &ohci
->regs
->roothub
.portstatus
[port
]);
1134 ohci_writel(ohci
, OHCI_INTR_MIE
, &ohci
->regs
->intrenable
);
1135 ohci_readl(ohci
, &ohci
->regs
->intrenable
);
1139 usb_hcd_resume_root_hub(hcd
);
1143 EXPORT_SYMBOL_GPL(ohci_resume
);
1147 /*-------------------------------------------------------------------------*/
1150 * Generic structure: This gets copied for platform drivers so that
1151 * individual entries can be overridden as needed.
1154 static const struct hc_driver ohci_hc_driver
= {
1155 .description
= hcd_name
,
1156 .product_desc
= "OHCI Host Controller",
1157 .hcd_priv_size
= sizeof(struct ohci_hcd
),
1160 * generic hardware linkage
1163 .flags
= HCD_MEMORY
| HCD_USB11
,
1166 * basic lifecycle operations
1168 .reset
= ohci_setup
,
1169 .start
= ohci_start
,
1171 .shutdown
= ohci_shutdown
,
1174 * managing i/o requests and associated device resources
1176 .urb_enqueue
= ohci_urb_enqueue
,
1177 .urb_dequeue
= ohci_urb_dequeue
,
1178 .endpoint_disable
= ohci_endpoint_disable
,
1181 * scheduling support
1183 .get_frame_number
= ohci_get_frame
,
1188 .hub_status_data
= ohci_hub_status_data
,
1189 .hub_control
= ohci_hub_control
,
1191 .bus_suspend
= ohci_bus_suspend
,
1192 .bus_resume
= ohci_bus_resume
,
1194 .start_port_reset
= ohci_start_port_reset
,
1197 void ohci_init_driver(struct hc_driver
*drv
,
1198 const struct ohci_driver_overrides
*over
)
1200 /* Copy the generic table to drv and then apply the overrides */
1201 *drv
= ohci_hc_driver
;
1204 drv
->product_desc
= over
->product_desc
;
1205 drv
->hcd_priv_size
+= over
->extra_priv_size
;
1207 drv
->reset
= over
->reset
;
1210 EXPORT_SYMBOL_GPL(ohci_init_driver
);
1212 /*-------------------------------------------------------------------------*/
1214 MODULE_AUTHOR (DRIVER_AUTHOR
);
1215 MODULE_DESCRIPTION(DRIVER_DESC
);
1216 MODULE_LICENSE ("GPL");
1218 #if defined(CONFIG_ARCH_SA1100) && defined(CONFIG_SA1111)
1219 #include "ohci-sa1111.c"
1220 #define SA1111_DRIVER ohci_hcd_sa1111_driver
1223 #ifdef CONFIG_USB_OHCI_HCD_PPC_OF
1224 #include "ohci-ppc-of.c"
1225 #define OF_PLATFORM_DRIVER ohci_hcd_ppc_of_driver
1228 #ifdef CONFIG_PPC_PS3
1229 #include "ohci-ps3.c"
1230 #define PS3_SYSTEM_BUS_DRIVER ps3_ohci_driver
1233 #ifdef CONFIG_MFD_SM501
1234 #include "ohci-sm501.c"
1235 #define SM501_OHCI_DRIVER ohci_hcd_sm501_driver
1238 #ifdef CONFIG_MFD_TC6393XB
1239 #include "ohci-tmio.c"
1240 #define TMIO_OHCI_DRIVER ohci_hcd_tmio_driver
1243 #ifdef CONFIG_TILE_USB
1244 #include "ohci-tilegx.c"
1245 #define PLATFORM_DRIVER ohci_hcd_tilegx_driver
1248 static int __init
ohci_hcd_mod_init(void)
1255 printk(KERN_INFO
"%s: " DRIVER_DESC
"\n", hcd_name
);
1256 pr_debug ("%s: block sizes: ed %zd td %zd\n", hcd_name
,
1257 sizeof (struct ed
), sizeof (struct td
));
1258 set_bit(USB_OHCI_LOADED
, &usb_hcds_loaded
);
1260 ohci_debug_root
= debugfs_create_dir("ohci", usb_debug_root
);
1261 if (!ohci_debug_root
) {
1266 #ifdef PS3_SYSTEM_BUS_DRIVER
1267 retval
= ps3_ohci_driver_register(&PS3_SYSTEM_BUS_DRIVER
);
1272 #ifdef PLATFORM_DRIVER
1273 retval
= platform_driver_register(&PLATFORM_DRIVER
);
1275 goto error_platform
;
1278 #ifdef OF_PLATFORM_DRIVER
1279 retval
= platform_driver_register(&OF_PLATFORM_DRIVER
);
1281 goto error_of_platform
;
1284 #ifdef SA1111_DRIVER
1285 retval
= sa1111_driver_register(&SA1111_DRIVER
);
1290 #ifdef SM501_OHCI_DRIVER
1291 retval
= platform_driver_register(&SM501_OHCI_DRIVER
);
1296 #ifdef TMIO_OHCI_DRIVER
1297 retval
= platform_driver_register(&TMIO_OHCI_DRIVER
);
1305 #ifdef TMIO_OHCI_DRIVER
1306 platform_driver_unregister(&TMIO_OHCI_DRIVER
);
1309 #ifdef SM501_OHCI_DRIVER
1310 platform_driver_unregister(&SM501_OHCI_DRIVER
);
1313 #ifdef SA1111_DRIVER
1314 sa1111_driver_unregister(&SA1111_DRIVER
);
1317 #ifdef OF_PLATFORM_DRIVER
1318 platform_driver_unregister(&OF_PLATFORM_DRIVER
);
1321 #ifdef PLATFORM_DRIVER
1322 platform_driver_unregister(&PLATFORM_DRIVER
);
1325 #ifdef PS3_SYSTEM_BUS_DRIVER
1326 ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER
);
1329 debugfs_remove(ohci_debug_root
);
1330 ohci_debug_root
= NULL
;
1333 clear_bit(USB_OHCI_LOADED
, &usb_hcds_loaded
);
1336 module_init(ohci_hcd_mod_init
);
1338 static void __exit
ohci_hcd_mod_exit(void)
1340 #ifdef TMIO_OHCI_DRIVER
1341 platform_driver_unregister(&TMIO_OHCI_DRIVER
);
1343 #ifdef SM501_OHCI_DRIVER
1344 platform_driver_unregister(&SM501_OHCI_DRIVER
);
1346 #ifdef SA1111_DRIVER
1347 sa1111_driver_unregister(&SA1111_DRIVER
);
1349 #ifdef OF_PLATFORM_DRIVER
1350 platform_driver_unregister(&OF_PLATFORM_DRIVER
);
1352 #ifdef PLATFORM_DRIVER
1353 platform_driver_unregister(&PLATFORM_DRIVER
);
1355 #ifdef PS3_SYSTEM_BUS_DRIVER
1356 ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER
);
1358 debugfs_remove(ohci_debug_root
);
1359 clear_bit(USB_OHCI_LOADED
, &usb_hcds_loaded
);
1361 module_exit(ohci_hcd_mod_exit
);