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iwmc3200wifi: Set WEP key from connect
[linux/fpc-iii.git] / drivers / usb / host / r8a66597.h
blobd72680b433f93c2309d7c17acbee40cab8281c45
1 /*
2 * R8A66597 HCD (Host Controller Driver)
3 *
4 * Copyright (C) 2006-2007 Renesas Solutions Corp.
5 * Portions Copyright (C) 2004 Psion Teklogix (for NetBook PRO)
6 * Portions Copyright (C) 2004-2005 David Brownell
7 * Portions Copyright (C) 1999 Roman Weissgaerber
8 *
9 * Author : Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; version 2 of the License.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 *
24 */
25
26 #ifndef __R8A66597_H__
27 #define __R8A66597_H__
28
29 #if defined(CONFIG_SUPERH_ON_CHIP_R8A66597) && defined(CONFIG_HAVE_CLK)
30 #include <linux/clk.h>
31 #endif
32
33 #include <linux/usb/r8a66597.h>
34
35 #define SYSCFG0 0x00
36 #define SYSCFG1 0x02
37 #define SYSSTS0 0x04
38 #define SYSSTS1 0x06
39 #define DVSTCTR0 0x08
40 #define DVSTCTR1 0x0A
41 #define TESTMODE 0x0C
42 #define PINCFG 0x0E
43 #define DMA0CFG 0x10
44 #define DMA1CFG 0x12
45 #define CFIFO 0x14
46 #define D0FIFO 0x18
47 #define D1FIFO 0x1C
48 #define CFIFOSEL 0x20
49 #define CFIFOCTR 0x22
50 #define CFIFOSIE 0x24
51 #define D0FIFOSEL 0x28
52 #define D0FIFOCTR 0x2A
53 #define D1FIFOSEL 0x2C
54 #define D1FIFOCTR 0x2E
55 #define INTENB0 0x30
56 #define INTENB1 0x32
57 #define INTENB2 0x34
58 #define BRDYENB 0x36
59 #define NRDYENB 0x38
60 #define BEMPENB 0x3A
61 #define SOFCFG 0x3C
62 #define INTSTS0 0x40
63 #define INTSTS1 0x42
64 #define INTSTS2 0x44
65 #define BRDYSTS 0x46
66 #define NRDYSTS 0x48
67 #define BEMPSTS 0x4A
68 #define FRMNUM 0x4C
69 #define UFRMNUM 0x4E
70 #define USBADDR 0x50
71 #define USBREQ 0x54
72 #define USBVAL 0x56
73 #define USBINDX 0x58
74 #define USBLENG 0x5A
75 #define DCPCFG 0x5C
76 #define DCPMAXP 0x5E
77 #define DCPCTR 0x60
78 #define PIPESEL 0x64
79 #define PIPECFG 0x68
80 #define PIPEBUF 0x6A
81 #define PIPEMAXP 0x6C
82 #define PIPEPERI 0x6E
83 #define PIPE1CTR 0x70
84 #define PIPE2CTR 0x72
85 #define PIPE3CTR 0x74
86 #define PIPE4CTR 0x76
87 #define PIPE5CTR 0x78
88 #define PIPE6CTR 0x7A
89 #define PIPE7CTR 0x7C
90 #define PIPE8CTR 0x7E
91 #define PIPE9CTR 0x80
92 #define PIPE1TRE 0x90
93 #define PIPE1TRN 0x92
94 #define PIPE2TRE 0x94
95 #define PIPE2TRN 0x96
96 #define PIPE3TRE 0x98
97 #define PIPE3TRN 0x9A
98 #define PIPE4TRE 0x9C
99 #define PIPE4TRN 0x9E
100 #define PIPE5TRE 0xA0
101 #define PIPE5TRN 0xA2
102 #define DEVADD0 0xD0
103 #define DEVADD1 0xD2
104 #define DEVADD2 0xD4
105 #define DEVADD3 0xD6
106 #define DEVADD4 0xD8
107 #define DEVADD5 0xDA
108 #define DEVADD6 0xDC
109 #define DEVADD7 0xDE
110 #define DEVADD8 0xE0
111 #define DEVADD9 0xE2
112 #define DEVADDA 0xE4
113
114 /* System Configuration Control Register */
115 #define XTAL 0xC000 /* b15-14: Crystal selection */
116 #define XTAL48 0x8000 /* 48MHz */
117 #define XTAL24 0x4000 /* 24MHz */
118 #define XTAL12 0x0000 /* 12MHz */
119 #define XCKE 0x2000 /* b13: External clock enable */
120 #define PLLC 0x0800 /* b11: PLL control */
121 #define SCKE 0x0400 /* b10: USB clock enable */
122 #define PCSDIS 0x0200 /* b9: not CS wakeup */
123 #define LPSME 0x0100 /* b8: Low power sleep mode */
124 #define HSE 0x0080 /* b7: Hi-speed enable */
125 #define DCFM 0x0040 /* b6: Controller function select */
126 #define DRPD 0x0020 /* b5: D+/- pull down control */
127 #define DPRPU 0x0010 /* b4: D+ pull up control */
128 #define USBE 0x0001 /* b0: USB module operation enable */
129
130 /* System Configuration Status Register */
131 #define OVCBIT 0x8000 /* b15-14: Over-current bit */
132 #define OVCMON 0xC000 /* b15-14: Over-current monitor */
133 #define SOFEA 0x0020 /* b5: SOF monitor */
134 #define IDMON 0x0004 /* b3: ID-pin monitor */
135 #define LNST 0x0003 /* b1-0: D+, D- line status */
136 #define SE1 0x0003 /* SE1 */
137 #define FS_KSTS 0x0002 /* Full-Speed K State */
138 #define FS_JSTS 0x0001 /* Full-Speed J State */
139 #define LS_JSTS 0x0002 /* Low-Speed J State */
140 #define LS_KSTS 0x0001 /* Low-Speed K State */
141 #define SE0 0x0000 /* SE0 */
142
143 /* Device State Control Register */
144 #define EXTLP0 0x0400 /* b10: External port */
145 #define VBOUT 0x0200 /* b9: VBUS output */
146 #define WKUP 0x0100 /* b8: Remote wakeup */
147 #define RWUPE 0x0080 /* b7: Remote wakeup sense */
148 #define USBRST 0x0040 /* b6: USB reset enable */
149 #define RESUME 0x0020 /* b5: Resume enable */
150 #define UACT 0x0010 /* b4: USB bus enable */
151 #define RHST 0x0007 /* b1-0: Reset handshake status */
152 #define HSPROC 0x0004 /* HS handshake is processing */
153 #define HSMODE 0x0003 /* Hi-Speed mode */
154 #define FSMODE 0x0002 /* Full-Speed mode */
155 #define LSMODE 0x0001 /* Low-Speed mode */
156 #define UNDECID 0x0000 /* Undecided */
157
158 /* Test Mode Register */
159 #define UTST 0x000F /* b3-0: Test select */
160 #define H_TST_PACKET 0x000C /* HOST TEST Packet */
161 #define H_TST_SE0_NAK 0x000B /* HOST TEST SE0 NAK */
162 #define H_TST_K 0x000A /* HOST TEST K */
163 #define H_TST_J 0x0009 /* HOST TEST J */
164 #define H_TST_NORMAL 0x0000 /* HOST Normal Mode */
165 #define P_TST_PACKET 0x0004 /* PERI TEST Packet */
166 #define P_TST_SE0_NAK 0x0003 /* PERI TEST SE0 NAK */
167 #define P_TST_K 0x0002 /* PERI TEST K */
168 #define P_TST_J 0x0001 /* PERI TEST J */
169 #define P_TST_NORMAL 0x0000 /* PERI Normal Mode */
170
171 /* Data Pin Configuration Register */
172 #define LDRV 0x8000 /* b15: Drive Current Adjust */
173 #define VIF1 0x0000 /* VIF = 1.8V */
174 #define VIF3 0x8000 /* VIF = 3.3V */
175 #define INTA 0x0001 /* b1: USB INT-pin active */
176
177 /* DMAx Pin Configuration Register */
178 #define DREQA 0x4000 /* b14: Dreq active select */
179 #define BURST 0x2000 /* b13: Burst mode */
180 #define DACKA 0x0400 /* b10: Dack active select */
181 #define DFORM 0x0380 /* b9-7: DMA mode select */
182 #define CPU_ADR_RD_WR 0x0000 /* Address + RD/WR mode (CPU bus) */
183 #define CPU_DACK_RD_WR 0x0100 /* DACK + RD/WR mode (CPU bus) */
184 #define CPU_DACK_ONLY 0x0180 /* DACK only mode (CPU bus) */
185 #define SPLIT_DACK_ONLY 0x0200 /* DACK only mode (SPLIT bus) */
186 #define DENDA 0x0040 /* b6: Dend active select */
187 #define PKTM 0x0020 /* b5: Packet mode */
188 #define DENDE 0x0010 /* b4: Dend enable */
189 #define OBUS 0x0004 /* b2: OUTbus mode */
190
191 /* CFIFO/DxFIFO Port Select Register */
192 #define RCNT 0x8000 /* b15: Read count mode */
193 #define REW 0x4000 /* b14: Buffer rewind */
194 #define DCLRM 0x2000 /* b13: DMA buffer clear mode */
195 #define DREQE 0x1000 /* b12: DREQ output enable */
196 #if defined(CONFIG_SUPERH_ON_CHIP_R8A66597)
197 #define MBW 0x0800
198 #else
199 #define MBW 0x0400 /* b10: Maximum bit width for FIFO access */
200 #endif
201 #define MBW_8 0x0000 /* 8bit */
202 #define MBW_16 0x0400 /* 16bit */
203 #define BIGEND 0x0100 /* b8: Big endian mode */
204 #define BYTE_LITTLE 0x0000 /* little dendian */
205 #define BYTE_BIG 0x0100 /* big endifan */
206 #define ISEL 0x0020 /* b5: DCP FIFO port direction select */
207 #define CURPIPE 0x000F /* b2-0: PIPE select */
208
209 /* CFIFO/DxFIFO Port Control Register */
210 #define BVAL 0x8000 /* b15: Buffer valid flag */
211 #define BCLR 0x4000 /* b14: Buffer clear */
212 #define FRDY 0x2000 /* b13: FIFO ready */
213 #define DTLN 0x0FFF /* b11-0: FIFO received data length */
214
215 /* Interrupt Enable Register 0 */
216 #define VBSE 0x8000 /* b15: VBUS interrupt */
217 #define RSME 0x4000 /* b14: Resume interrupt */
218 #define SOFE 0x2000 /* b13: Frame update interrupt */
219 #define DVSE 0x1000 /* b12: Device state transition interrupt */
220 #define CTRE 0x0800 /* b11: Control transfer stage transition interrupt */
221 #define BEMPE 0x0400 /* b10: Buffer empty interrupt */
222 #define NRDYE 0x0200 /* b9: Buffer not ready interrupt */
223 #define BRDYE 0x0100 /* b8: Buffer ready interrupt */
224
225 /* Interrupt Enable Register 1 */
226 #define OVRCRE 0x8000 /* b15: Over-current interrupt */
227 #define BCHGE 0x4000 /* b14: USB us chenge interrupt */
228 #define DTCHE 0x1000 /* b12: Detach sense interrupt */
229 #define ATTCHE 0x0800 /* b11: Attach sense interrupt */
230 #define EOFERRE 0x0040 /* b6: EOF error interrupt */
231 #define SIGNE 0x0020 /* b5: SETUP IGNORE interrupt */
232 #define SACKE 0x0010 /* b4: SETUP ACK interrupt */
233
234 /* BRDY Interrupt Enable/Status Register */
235 #define BRDY9 0x0200 /* b9: PIPE9 */
236 #define BRDY8 0x0100 /* b8: PIPE8 */
237 #define BRDY7 0x0080 /* b7: PIPE7 */
238 #define BRDY6 0x0040 /* b6: PIPE6 */
239 #define BRDY5 0x0020 /* b5: PIPE5 */
240 #define BRDY4 0x0010 /* b4: PIPE4 */
241 #define BRDY3 0x0008 /* b3: PIPE3 */
242 #define BRDY2 0x0004 /* b2: PIPE2 */
243 #define BRDY1 0x0002 /* b1: PIPE1 */
244 #define BRDY0 0x0001 /* b1: PIPE0 */
245
246 /* NRDY Interrupt Enable/Status Register */
247 #define NRDY9 0x0200 /* b9: PIPE9 */
248 #define NRDY8 0x0100 /* b8: PIPE8 */
249 #define NRDY7 0x0080 /* b7: PIPE7 */
250 #define NRDY6 0x0040 /* b6: PIPE6 */
251 #define NRDY5 0x0020 /* b5: PIPE5 */
252 #define NRDY4 0x0010 /* b4: PIPE4 */
253 #define NRDY3 0x0008 /* b3: PIPE3 */
254 #define NRDY2 0x0004 /* b2: PIPE2 */
255 #define NRDY1 0x0002 /* b1: PIPE1 */
256 #define NRDY0 0x0001 /* b1: PIPE0 */
257
258 /* BEMP Interrupt Enable/Status Register */
259 #define BEMP9 0x0200 /* b9: PIPE9 */
260 #define BEMP8 0x0100 /* b8: PIPE8 */
261 #define BEMP7 0x0080 /* b7: PIPE7 */
262 #define BEMP6 0x0040 /* b6: PIPE6 */
263 #define BEMP5 0x0020 /* b5: PIPE5 */
264 #define BEMP4 0x0010 /* b4: PIPE4 */
265 #define BEMP3 0x0008 /* b3: PIPE3 */
266 #define BEMP2 0x0004 /* b2: PIPE2 */
267 #define BEMP1 0x0002 /* b1: PIPE1 */
268 #define BEMP0 0x0001 /* b0: PIPE0 */
269
270 /* SOF Pin Configuration Register */
271 #define TRNENSEL 0x0100 /* b8: Select transaction enable period */
272 #define BRDYM 0x0040 /* b6: BRDY clear timing */
273 #define INTL 0x0020 /* b5: Interrupt sense select */
274 #define EDGESTS 0x0010 /* b4: */
275 #define SOFMODE 0x000C /* b3-2: SOF pin select */
276 #define SOF_125US 0x0008 /* SOF OUT 125us Frame Signal */
277 #define SOF_1MS 0x0004 /* SOF OUT 1ms Frame Signal */
278 #define SOF_DISABLE 0x0000 /* SOF OUT Disable */
279
280 /* Interrupt Status Register 0 */
281 #define VBINT 0x8000 /* b15: VBUS interrupt */
282 #define RESM 0x4000 /* b14: Resume interrupt */
283 #define SOFR 0x2000 /* b13: SOF frame update interrupt */
284 #define DVST 0x1000 /* b12: Device state transition interrupt */
285 #define CTRT 0x0800 /* b11: Control transfer stage transition interrupt */
286 #define BEMP 0x0400 /* b10: Buffer empty interrupt */
287 #define NRDY 0x0200 /* b9: Buffer not ready interrupt */
288 #define BRDY 0x0100 /* b8: Buffer ready interrupt */
289 #define VBSTS 0x0080 /* b7: VBUS input port */
290 #define DVSQ 0x0070 /* b6-4: Device state */
291 #define DS_SPD_CNFG 0x0070 /* Suspend Configured */
292 #define DS_SPD_ADDR 0x0060 /* Suspend Address */
293 #define DS_SPD_DFLT 0x0050 /* Suspend Default */
294 #define DS_SPD_POWR 0x0040 /* Suspend Powered */
295 #define DS_SUSP 0x0040 /* Suspend */
296 #define DS_CNFG 0x0030 /* Configured */
297 #define DS_ADDS 0x0020 /* Address */
298 #define DS_DFLT 0x0010 /* Default */
299 #define DS_POWR 0x0000 /* Powered */
300 #define DVSQS 0x0030 /* b5-4: Device state */
301 #define VALID 0x0008 /* b3: Setup packet detected flag */
302 #define CTSQ 0x0007 /* b2-0: Control transfer stage */
303 #define CS_SQER 0x0006 /* Sequence error */
304 #define CS_WRND 0x0005 /* Control write nodata status stage */
305 #define CS_WRSS 0x0004 /* Control write status stage */
306 #define CS_WRDS 0x0003 /* Control write data stage */
307 #define CS_RDSS 0x0002 /* Control read status stage */
308 #define CS_RDDS 0x0001 /* Control read data stage */
309 #define CS_IDST 0x0000 /* Idle or setup stage */
310
311 /* Interrupt Status Register 1 */
312 #define OVRCR 0x8000 /* b15: Over-current interrupt */
313 #define BCHG 0x4000 /* b14: USB bus chenge interrupt */
314 #define DTCH 0x1000 /* b12: Detach sense interrupt */
315 #define ATTCH 0x0800 /* b11: Attach sense interrupt */
316 #define EOFERR 0x0040 /* b6: EOF-error interrupt */
317 #define SIGN 0x0020 /* b5: Setup ignore interrupt */
318 #define SACK 0x0010 /* b4: Setup acknowledge interrupt */
319
320 /* Frame Number Register */
321 #define OVRN 0x8000 /* b15: Overrun error */
322 #define CRCE 0x4000 /* b14: Received data error */
323 #define FRNM 0x07FF /* b10-0: Frame number */
324
325 /* Micro Frame Number Register */
326 #define UFRNM 0x0007 /* b2-0: Micro frame number */
327
328 /* Default Control Pipe Maxpacket Size Register */
329 /* Pipe Maxpacket Size Register */
330 #define DEVSEL 0xF000 /* b15-14: Device address select */
331 #define MAXP 0x007F /* b6-0: Maxpacket size of default control pipe */
332
333 /* Default Control Pipe Control Register */
334 #define BSTS 0x8000 /* b15: Buffer status */
335 #define SUREQ 0x4000 /* b14: Send USB request */
336 #define CSCLR 0x2000 /* b13: complete-split status clear */
337 #define CSSTS 0x1000 /* b12: complete-split status */
338 #define SUREQCLR 0x0800 /* b11: stop setup request */
339 #define SQCLR 0x0100 /* b8: Sequence toggle bit clear */
340 #define SQSET 0x0080 /* b7: Sequence toggle bit set */
341 #define SQMON 0x0040 /* b6: Sequence toggle bit monitor */
342 #define PBUSY 0x0020 /* b5: pipe busy */
343 #define PINGE 0x0010 /* b4: ping enable */
344 #define CCPL 0x0004 /* b2: Enable control transfer complete */
345 #define PID 0x0003 /* b1-0: Response PID */
346 #define PID_STALL11 0x0003 /* STALL */
347 #define PID_STALL 0x0002 /* STALL */
348 #define PID_BUF 0x0001 /* BUF */
349 #define PID_NAK 0x0000 /* NAK */
350
351 /* Pipe Window Select Register */
352 #define PIPENM 0x0007 /* b2-0: Pipe select */
353
354 /* Pipe Configuration Register */
355 #define R8A66597_TYP 0xC000 /* b15-14: Transfer type */
356 #define R8A66597_ISO 0xC000 /* Isochronous */
357 #define R8A66597_INT 0x8000 /* Interrupt */
358 #define R8A66597_BULK 0x4000 /* Bulk */
359 #define R8A66597_BFRE 0x0400 /* b10: Buffer ready interrupt mode select */
360 #define R8A66597_DBLB 0x0200 /* b9: Double buffer mode select */
361 #define R8A66597_CNTMD 0x0100 /* b8: Continuous transfer mode select */
362 #define R8A66597_SHTNAK 0x0080 /* b7: Transfer end NAK */
363 #define R8A66597_DIR 0x0010 /* b4: Transfer direction select */
364 #define R8A66597_EPNUM 0x000F /* b3-0: Eendpoint number select */
365
366 /* Pipe Buffer Configuration Register */
367 #define BUFSIZE 0x7C00 /* b14-10: Pipe buffer size */
368 #define BUFNMB 0x007F /* b6-0: Pipe buffer number */
369 #define PIPE0BUF 256
370 #define PIPExBUF 64
371
372 /* Pipe Maxpacket Size Register */
373 #define MXPS 0x07FF /* b10-0: Maxpacket size */
374
375 /* Pipe Cycle Configuration Register */
376 #define IFIS 0x1000 /* b12: Isochronous in-buffer flush mode select */
377 #define IITV 0x0007 /* b2-0: Isochronous interval */
378
379 /* Pipex Control Register */
380 #define BSTS 0x8000 /* b15: Buffer status */
381 #define INBUFM 0x4000 /* b14: IN buffer monitor (Only for PIPE1 to 5) */
382 #define CSCLR 0x2000 /* b13: complete-split status clear */
383 #define CSSTS 0x1000 /* b12: complete-split status */
384 #define ATREPM 0x0400 /* b10: Auto repeat mode */
385 #define ACLRM 0x0200 /* b9: Out buffer auto clear mode */
386 #define SQCLR 0x0100 /* b8: Sequence toggle bit clear */
387 #define SQSET 0x0080 /* b7: Sequence toggle bit set */
388 #define SQMON 0x0040 /* b6: Sequence toggle bit monitor */
389 #define PBUSY 0x0020 /* b5: pipe busy */
390 #define PID 0x0003 /* b1-0: Response PID */
391
392 /* PIPExTRE */
393 #define TRENB 0x0200 /* b9: Transaction counter enable */
394 #define TRCLR 0x0100 /* b8: Transaction counter clear */
395
396 /* PIPExTRN */
397 #define TRNCNT 0xFFFF /* b15-0: Transaction counter */
398
399 /* DEVADDx */
400 #define UPPHUB 0x7800
401 #define HUBPORT 0x0700
402 #define USBSPD 0x00C0
403 #define RTPORT 0x0001
404
405 #define R8A66597_MAX_NUM_PIPE 10
406 #define R8A66597_BUF_BSIZE 8
407 #define R8A66597_MAX_DEVICE 10
408 #if defined(CONFIG_SUPERH_ON_CHIP_R8A66597)
409 #define R8A66597_MAX_ROOT_HUB 1
410 #else
411 #define R8A66597_MAX_ROOT_HUB 2
412 #endif
413 #define R8A66597_MAX_SAMPLING 5
414 #define R8A66597_RH_POLL_TIME 10
415 #define R8A66597_MAX_DMA_CHANNEL 2
416 #define R8A66597_PIPE_NO_DMA R8A66597_MAX_DMA_CHANNEL
417 #define check_bulk_or_isoc(pipenum) ((pipenum >= 1 && pipenum <= 5))
418 #define check_interrupt(pipenum) ((pipenum >= 6 && pipenum <= 9))
419 #define make_devsel(addr) (addr << 12)
420
421 struct r8a66597_pipe_info {
422 unsigned long timer_interval;
423 u16 pipenum;
424 u16 address; /* R8A66597 HCD usb address */
425 u16 epnum;
426 u16 maxpacket;
427 u16 type;
428 u16 bufnum;
429 u16 buf_bsize;
430 u16 interval;
431 u16 dir_in;
432 };
433
434 struct r8a66597_pipe {
435 struct r8a66597_pipe_info info;
436
437 unsigned long fifoaddr;
438 unsigned long fifosel;
439 unsigned long fifoctr;
440 unsigned long pipectr;
441 unsigned long pipetre;
442 unsigned long pipetrn;
443 };
444
445 struct r8a66597_td {
446 struct r8a66597_pipe *pipe;
447 struct urb *urb;
448 struct list_head queue;
449
450 u16 type;
451 u16 pipenum;
452 int iso_cnt;
453
454 u16 address; /* R8A66597's USB address */
455 u16 maxpacket;
456
457 unsigned zero_packet:1;
458 unsigned short_packet:1;
459 unsigned set_address:1;
460 };
461
462 struct r8a66597_device {
463 u16 address; /* R8A66597's USB address */
464 u16 hub_port;
465 u16 root_port;
466
467 unsigned short ep_in_toggle;
468 unsigned short ep_out_toggle;
469 unsigned char pipe_cnt[R8A66597_MAX_NUM_PIPE];
470 unsigned char dma_map;
471
472 enum usb_device_state state;
473
474 struct usb_device *udev;
475 int usb_address;
476 struct list_head device_list;
477 };
478
479 struct r8a66597_root_hub {
480 u32 port;
481 u16 old_syssts;
482 int scount;
483
484 struct r8a66597_device *dev;
485 };
486
487 struct r8a66597 {
488 spinlock_t lock;
489 unsigned long reg;
490 #if defined(CONFIG_SUPERH_ON_CHIP_R8A66597) && defined(CONFIG_HAVE_CLK)
491 struct clk *clk;
492 #endif
493 struct r8a66597_platdata *pdata;
494 struct r8a66597_device device0;
495 struct r8a66597_root_hub root_hub[R8A66597_MAX_ROOT_HUB];
496 struct list_head pipe_queue[R8A66597_MAX_NUM_PIPE];
497
498 struct timer_list rh_timer;
499 struct timer_list td_timer[R8A66597_MAX_NUM_PIPE];
500 struct timer_list interval_timer[R8A66597_MAX_NUM_PIPE];
501
502 unsigned short address_map;
503 unsigned short timeout_map;
504 unsigned short interval_map;
505 unsigned char pipe_cnt[R8A66597_MAX_NUM_PIPE];
506 unsigned char dma_map;
507
508 struct list_head child_device;
509 unsigned long child_connect_map[4];
510
511 unsigned bus_suspended:1;
512 unsigned irq_sense_low:1;
513 };
514
515 static inline struct r8a66597 *hcd_to_r8a66597(struct usb_hcd *hcd)
516 {
517 return (struct r8a66597 *)(hcd->hcd_priv);
518 }
519
520 static inline struct usb_hcd *r8a66597_to_hcd(struct r8a66597 *r8a66597)
521 {
522 return container_of((void *)r8a66597, struct usb_hcd, hcd_priv);
523 }
524
525 static inline struct r8a66597_td *r8a66597_get_td(struct r8a66597 *r8a66597,
526 u16 pipenum)
527 {
528 if (unlikely(list_empty(&r8a66597->pipe_queue[pipenum])))
529 return NULL;
530
531 return list_entry(r8a66597->pipe_queue[pipenum].next,
532 struct r8a66597_td, queue);
533 }
534
535 static inline struct urb *r8a66597_get_urb(struct r8a66597 *r8a66597,
536 u16 pipenum)
537 {
538 struct r8a66597_td *td;
539
540 td = r8a66597_get_td(r8a66597, pipenum);
541 return (td ? td->urb : NULL);
542 }
543
544 static inline u16 r8a66597_read(struct r8a66597 *r8a66597, unsigned long offset)
545 {
546 return inw(r8a66597->reg + offset);
547 }
548
549 static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597,
550 unsigned long offset, u16 *buf,
551 int len)
552 {
553 #if defined(CONFIG_SUPERH_ON_CHIP_R8A66597)
554 unsigned long fifoaddr = r8a66597->reg + offset;
555 unsigned long count;
556
557 count = len / 4;
558 insl(fifoaddr, buf, count);
559
560 if (len & 0x00000003) {
561 unsigned long tmp = inl(fifoaddr);
562 memcpy((unsigned char *)buf + count * 4, &tmp, len & 0x03);
563 }
564 #else
565 len = (len + 1) / 2;
566 insw(r8a66597->reg + offset, buf, len);
567 #endif
568 }
569
570 static inline void r8a66597_write(struct r8a66597 *r8a66597, u16 val,
571 unsigned long offset)
572 {
573 outw(val, r8a66597->reg + offset);
574 }
575
576 static inline void r8a66597_write_fifo(struct r8a66597 *r8a66597,
577 unsigned long offset, u16 *buf,
578 int len)
579 {
580 unsigned long fifoaddr = r8a66597->reg + offset;
581 #if defined(CONFIG_SUPERH_ON_CHIP_R8A66597)
582 unsigned long count;
583 unsigned char *pb;
584 int i;
585
586 count = len / 4;
587 outsl(fifoaddr, buf, count);
588
589 if (len & 0x00000003) {
590 pb = (unsigned char *)buf + count * 4;
591 for (i = 0; i < (len & 0x00000003); i++) {
592 if (r8a66597_read(r8a66597, CFIFOSEL) & BIGEND)
593 outb(pb[i], fifoaddr + i);
594 else
595 outb(pb[i], fifoaddr + 3 - i);
596 }
597 }
598 #else
599 int odd = len & 0x0001;
600
601 len = len / 2;
602 outsw(fifoaddr, buf, len);
603 if (unlikely(odd)) {
604 buf = &buf[len];
605 outb((unsigned char)*buf, fifoaddr);
606 }
607 #endif
608 }
609
610 static inline void r8a66597_mdfy(struct r8a66597 *r8a66597,
611 u16 val, u16 pat, unsigned long offset)
612 {
613 u16 tmp;
614 tmp = r8a66597_read(r8a66597, offset);
615 tmp = tmp & (~pat);
616 tmp = tmp | val;
617 r8a66597_write(r8a66597, tmp, offset);
618 }
619
620 #define r8a66597_bclr(r8a66597, val, offset) \
621 r8a66597_mdfy(r8a66597, 0, val, offset)
622 #define r8a66597_bset(r8a66597, val, offset) \
623 r8a66597_mdfy(r8a66597, val, 0, offset)
624
625 static inline unsigned long get_syscfg_reg(int port)
626 {
627 return port == 0 ? SYSCFG0 : SYSCFG1;
628 }
629
630 static inline unsigned long get_syssts_reg(int port)
631 {
632 return port == 0 ? SYSSTS0 : SYSSTS1;
633 }
634
635 static inline unsigned long get_dvstctr_reg(int port)
636 {
637 return port == 0 ? DVSTCTR0 : DVSTCTR1;
638 }
639
640 static inline unsigned long get_dmacfg_reg(int port)
641 {
642 return port == 0 ? DMA0CFG : DMA1CFG;
643 }
644
645 static inline unsigned long get_intenb_reg(int port)
646 {
647 return port == 0 ? INTENB1 : INTENB2;
648 }
649
650 static inline unsigned long get_intsts_reg(int port)
651 {
652 return port == 0 ? INTSTS1 : INTSTS2;
653 }
654
655 static inline u16 get_rh_usb_speed(struct r8a66597 *r8a66597, int port)
656 {
657 unsigned long dvstctr_reg = get_dvstctr_reg(port);
658
659 return r8a66597_read(r8a66597, dvstctr_reg) & RHST;
660 }
661
662 static inline void r8a66597_port_power(struct r8a66597 *r8a66597, int port,
663 int power)
664 {
665 unsigned long dvstctr_reg = get_dvstctr_reg(port);
666
667 if (r8a66597->pdata->port_power) {
668 r8a66597->pdata->port_power(port, power);
669 } else {
670 if (power)
671 r8a66597_bset(r8a66597, VBOUT, dvstctr_reg);
672 else
673 r8a66597_bclr(r8a66597, VBOUT, dvstctr_reg);
674 }
675 }
676
677 static inline u16 get_xtal_from_pdata(struct r8a66597_platdata *pdata)
678 {
679 u16 clock = 0;
680
681 switch (pdata->xtal) {
682 case R8A66597_PLATDATA_XTAL_12MHZ:
683 clock = XTAL12;
684 break;
685 case R8A66597_PLATDATA_XTAL_24MHZ:
686 clock = XTAL24;
687 break;
688 case R8A66597_PLATDATA_XTAL_48MHZ:
689 clock = XTAL48;
690 break;
691 default:
692 printk(KERN_ERR "r8a66597: platdata clock is wrong.\n");
693 break;
694 }
695
696 return clock;
697 }
698
699 #define get_pipectr_addr(pipenum) (PIPE1CTR + (pipenum - 1) * 2)
700 #define get_pipetre_addr(pipenum) (PIPE1TRE + (pipenum - 1) * 4)
701 #define get_pipetrn_addr(pipenum) (PIPE1TRN + (pipenum - 1) * 4)
702 #define get_devadd_addr(address) (DEVADD0 + address * 2)
703
704 #define enable_irq_ready(r8a66597, pipenum) \
705 enable_pipe_irq(r8a66597, pipenum, BRDYENB)
706 #define disable_irq_ready(r8a66597, pipenum) \
707 disable_pipe_irq(r8a66597, pipenum, BRDYENB)
708 #define enable_irq_empty(r8a66597, pipenum) \
709 enable_pipe_irq(r8a66597, pipenum, BEMPENB)
710 #define disable_irq_empty(r8a66597, pipenum) \
711 disable_pipe_irq(r8a66597, pipenum, BEMPENB)
712 #define enable_irq_nrdy(r8a66597, pipenum) \
713 enable_pipe_irq(r8a66597, pipenum, NRDYENB)
714 #define disable_irq_nrdy(r8a66597, pipenum) \
715 disable_pipe_irq(r8a66597, pipenum, NRDYENB)
716
717 #endif /* __R8A66597_H__ */
718
Linux with added FPC-III support