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dt-bindings: mtd: ingenic: Use standard ecc-engine property
[linux/fpc-iii.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_display.c
blobb083b219b1a966e9e38c318cb30c91e478f650c7
1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26 #include <drm/drmP.h>
27 #include <drm/amdgpu_drm.h>
28 #include "amdgpu.h"
29 #include "amdgpu_i2c.h"
30 #include "atom.h"
31 #include "amdgpu_connectors.h"
32 #include "amdgpu_display.h"
33 #include <asm/div64.h>
34
35 #include <linux/pm_runtime.h>
36 #include <drm/drm_crtc_helper.h>
37 #include <drm/drm_edid.h>
38 #include <drm/drm_gem_framebuffer_helper.h>
39 #include <drm/drm_fb_helper.h>
40
41 static void amdgpu_display_flip_callback(struct dma_fence *f,
42 struct dma_fence_cb *cb)
43 {
44 struct amdgpu_flip_work *work =
45 container_of(cb, struct amdgpu_flip_work, cb);
46
47 dma_fence_put(f);
48 schedule_work(&work->flip_work.work);
49 }
50
51 static bool amdgpu_display_flip_handle_fence(struct amdgpu_flip_work *work,
52 struct dma_fence **f)
53 {
54 struct dma_fence *fence= *f;
55
56 if (fence == NULL)
57 return false;
58
59 *f = NULL;
60
61 if (!dma_fence_add_callback(fence, &work->cb,
62 amdgpu_display_flip_callback))
63 return true;
64
65 dma_fence_put(fence);
66 return false;
67 }
68
69 static void amdgpu_display_flip_work_func(struct work_struct *__work)
70 {
71 struct delayed_work *delayed_work =
72 container_of(__work, struct delayed_work, work);
73 struct amdgpu_flip_work *work =
74 container_of(delayed_work, struct amdgpu_flip_work, flip_work);
75 struct amdgpu_device *adev = work->adev;
76 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[work->crtc_id];
77
78 struct drm_crtc *crtc = &amdgpu_crtc->base;
79 unsigned long flags;
80 unsigned i;
81 int vpos, hpos;
82
83 if (amdgpu_display_flip_handle_fence(work, &work->excl))
84 return;
85
86 for (i = 0; i < work->shared_count; ++i)
87 if (amdgpu_display_flip_handle_fence(work, &work->shared[i]))
88 return;
89
90 /* Wait until we're out of the vertical blank period before the one
91 * targeted by the flip
92 */
93 if (amdgpu_crtc->enabled &&
94 (amdgpu_display_get_crtc_scanoutpos(adev->ddev, work->crtc_id, 0,
95 &vpos, &hpos, NULL, NULL,
96 &crtc->hwmode)
97 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
98 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
99 (int)(work->target_vblank -
100 amdgpu_get_vblank_counter_kms(adev->ddev, amdgpu_crtc->crtc_id)) > 0) {
101 schedule_delayed_work(&work->flip_work, usecs_to_jiffies(1000));
102 return;
103 }
104
105 /* We borrow the event spin lock for protecting flip_status */
106 spin_lock_irqsave(&crtc->dev->event_lock, flags);
107
108 /* Do the flip (mmio) */
109 adev->mode_info.funcs->page_flip(adev, work->crtc_id, work->base, work->async);
110
111 /* Set the flip status */
112 amdgpu_crtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
113 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
114
115
116 DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_SUBMITTED, work: %p,\n",
117 amdgpu_crtc->crtc_id, amdgpu_crtc, work);
118
119 }
120
121 /*
122 * Handle unpin events outside the interrupt handler proper.
123 */
124 static void amdgpu_display_unpin_work_func(struct work_struct *__work)
125 {
126 struct amdgpu_flip_work *work =
127 container_of(__work, struct amdgpu_flip_work, unpin_work);
128 int r;
129
130 /* unpin of the old buffer */
131 r = amdgpu_bo_reserve(work->old_abo, true);
132 if (likely(r == 0)) {
133 r = amdgpu_bo_unpin(work->old_abo);
134 if (unlikely(r != 0)) {
135 DRM_ERROR("failed to unpin buffer after flip\n");
136 }
137 amdgpu_bo_unreserve(work->old_abo);
138 } else
139 DRM_ERROR("failed to reserve buffer after flip\n");
140
141 amdgpu_bo_unref(&work->old_abo);
142 kfree(work->shared);
143 kfree(work);
144 }
145
146 int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc,
147 struct drm_framebuffer *fb,
148 struct drm_pending_vblank_event *event,
149 uint32_t page_flip_flags, uint32_t target,
150 struct drm_modeset_acquire_ctx *ctx)
151 {
152 struct drm_device *dev = crtc->dev;
153 struct amdgpu_device *adev = dev->dev_private;
154 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
155 struct drm_gem_object *obj;
156 struct amdgpu_flip_work *work;
157 struct amdgpu_bo *new_abo;
158 unsigned long flags;
159 u64 tiling_flags;
160 int i, r;
161
162 work = kzalloc(sizeof *work, GFP_KERNEL);
163 if (work == NULL)
164 return -ENOMEM;
165
166 INIT_DELAYED_WORK(&work->flip_work, amdgpu_display_flip_work_func);
167 INIT_WORK(&work->unpin_work, amdgpu_display_unpin_work_func);
168
169 work->event = event;
170 work->adev = adev;
171 work->crtc_id = amdgpu_crtc->crtc_id;
172 work->async = (page_flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
173
174 /* schedule unpin of the old buffer */
175 obj = crtc->primary->fb->obj[0];
176
177 /* take a reference to the old object */
178 work->old_abo = gem_to_amdgpu_bo(obj);
179 amdgpu_bo_ref(work->old_abo);
180
181 obj = fb->obj[0];
182 new_abo = gem_to_amdgpu_bo(obj);
183
184 /* pin the new buffer */
185 r = amdgpu_bo_reserve(new_abo, false);
186 if (unlikely(r != 0)) {
187 DRM_ERROR("failed to reserve new abo buffer before flip\n");
188 goto cleanup;
189 }
190
191 if (!adev->enable_virtual_display) {
192 r = amdgpu_bo_pin(new_abo, amdgpu_display_supported_domains(adev));
193 if (unlikely(r != 0)) {
194 DRM_ERROR("failed to pin new abo buffer before flip\n");
195 goto unreserve;
196 }
197 }
198
199 r = amdgpu_ttm_alloc_gart(&new_abo->tbo);
200 if (unlikely(r != 0)) {
201 DRM_ERROR("%p bind failed\n", new_abo);
202 goto unpin;
203 }
204
205 r = reservation_object_get_fences_rcu(new_abo->tbo.resv, &work->excl,
206 &work->shared_count,
207 &work->shared);
208 if (unlikely(r != 0)) {
209 DRM_ERROR("failed to get fences for buffer\n");
210 goto unpin;
211 }
212
213 amdgpu_bo_get_tiling_flags(new_abo, &tiling_flags);
214 amdgpu_bo_unreserve(new_abo);
215
216 if (!adev->enable_virtual_display)
217 work->base = amdgpu_bo_gpu_offset(new_abo);
218 work->target_vblank = target - (uint32_t)drm_crtc_vblank_count(crtc) +
219 amdgpu_get_vblank_counter_kms(dev, work->crtc_id);
220
221 /* we borrow the event spin lock for protecting flip_wrok */
222 spin_lock_irqsave(&crtc->dev->event_lock, flags);
223 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_NONE) {
224 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
225 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
226 r = -EBUSY;
227 goto pflip_cleanup;
228 }
229
230 amdgpu_crtc->pflip_status = AMDGPU_FLIP_PENDING;
231 amdgpu_crtc->pflip_works = work;
232
233
234 DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_PENDING, work: %p,\n",
235 amdgpu_crtc->crtc_id, amdgpu_crtc, work);
236 /* update crtc fb */
237 crtc->primary->fb = fb;
238 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
239 amdgpu_display_flip_work_func(&work->flip_work.work);
240 return 0;
241
242 pflip_cleanup:
243 if (unlikely(amdgpu_bo_reserve(new_abo, false) != 0)) {
244 DRM_ERROR("failed to reserve new abo in error path\n");
245 goto cleanup;
246 }
247 unpin:
248 if (!adev->enable_virtual_display)
249 if (unlikely(amdgpu_bo_unpin(new_abo) != 0))
250 DRM_ERROR("failed to unpin new abo in error path\n");
251
252 unreserve:
253 amdgpu_bo_unreserve(new_abo);
254
255 cleanup:
256 amdgpu_bo_unref(&work->old_abo);
257 dma_fence_put(work->excl);
258 for (i = 0; i < work->shared_count; ++i)
259 dma_fence_put(work->shared[i]);
260 kfree(work->shared);
261 kfree(work);
262
263 return r;
264 }
265
266 int amdgpu_display_crtc_set_config(struct drm_mode_set *set,
267 struct drm_modeset_acquire_ctx *ctx)
268 {
269 struct drm_device *dev;
270 struct amdgpu_device *adev;
271 struct drm_crtc *crtc;
272 bool active = false;
273 int ret;
274
275 if (!set || !set->crtc)
276 return -EINVAL;
277
278 dev = set->crtc->dev;
279
280 ret = pm_runtime_get_sync(dev->dev);
281 if (ret < 0)
282 return ret;
283
284 ret = drm_crtc_helper_set_config(set, ctx);
285
286 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
287 if (crtc->enabled)
288 active = true;
289
290 pm_runtime_mark_last_busy(dev->dev);
291
292 adev = dev->dev_private;
293 /* if we have active crtcs and we don't have a power ref,
294 take the current one */
295 if (active && !adev->have_disp_power_ref) {
296 adev->have_disp_power_ref = true;
297 return ret;
298 }
299 /* if we have no active crtcs, then drop the power ref
300 we got before */
301 if (!active && adev->have_disp_power_ref) {
302 pm_runtime_put_autosuspend(dev->dev);
303 adev->have_disp_power_ref = false;
304 }
305
306 /* drop the power reference we got coming in here */
307 pm_runtime_put_autosuspend(dev->dev);
308 return ret;
309 }
310
311 static const char *encoder_names[41] = {
312 "NONE",
313 "INTERNAL_LVDS",
314 "INTERNAL_TMDS1",
315 "INTERNAL_TMDS2",
316 "INTERNAL_DAC1",
317 "INTERNAL_DAC2",
318 "INTERNAL_SDVOA",
319 "INTERNAL_SDVOB",
320 "SI170B",
321 "CH7303",
322 "CH7301",
323 "INTERNAL_DVO1",
324 "EXTERNAL_SDVOA",
325 "EXTERNAL_SDVOB",
326 "TITFP513",
327 "INTERNAL_LVTM1",
328 "VT1623",
329 "HDMI_SI1930",
330 "HDMI_INTERNAL",
331 "INTERNAL_KLDSCP_TMDS1",
332 "INTERNAL_KLDSCP_DVO1",
333 "INTERNAL_KLDSCP_DAC1",
334 "INTERNAL_KLDSCP_DAC2",
335 "SI178",
336 "MVPU_FPGA",
337 "INTERNAL_DDI",
338 "VT1625",
339 "HDMI_SI1932",
340 "DP_AN9801",
341 "DP_DP501",
342 "INTERNAL_UNIPHY",
343 "INTERNAL_KLDSCP_LVTMA",
344 "INTERNAL_UNIPHY1",
345 "INTERNAL_UNIPHY2",
346 "NUTMEG",
347 "TRAVIS",
348 "INTERNAL_VCE",
349 "INTERNAL_UNIPHY3",
350 "HDMI_ANX9805",
351 "INTERNAL_AMCLK",
352 "VIRTUAL",
353 };
354
355 static const char *hpd_names[6] = {
356 "HPD1",
357 "HPD2",
358 "HPD3",
359 "HPD4",
360 "HPD5",
361 "HPD6",
362 };
363
364 void amdgpu_display_print_display_setup(struct drm_device *dev)
365 {
366 struct drm_connector *connector;
367 struct amdgpu_connector *amdgpu_connector;
368 struct drm_encoder *encoder;
369 struct amdgpu_encoder *amdgpu_encoder;
370 uint32_t devices;
371 int i = 0;
372
373 DRM_INFO("AMDGPU Display Connectors\n");
374 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
375 amdgpu_connector = to_amdgpu_connector(connector);
376 DRM_INFO("Connector %d:\n", i);
377 DRM_INFO(" %s\n", connector->name);
378 if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE)
379 DRM_INFO(" %s\n", hpd_names[amdgpu_connector->hpd.hpd]);
380 if (amdgpu_connector->ddc_bus) {
381 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
382 amdgpu_connector->ddc_bus->rec.mask_clk_reg,
383 amdgpu_connector->ddc_bus->rec.mask_data_reg,
384 amdgpu_connector->ddc_bus->rec.a_clk_reg,
385 amdgpu_connector->ddc_bus->rec.a_data_reg,
386 amdgpu_connector->ddc_bus->rec.en_clk_reg,
387 amdgpu_connector->ddc_bus->rec.en_data_reg,
388 amdgpu_connector->ddc_bus->rec.y_clk_reg,
389 amdgpu_connector->ddc_bus->rec.y_data_reg);
390 if (amdgpu_connector->router.ddc_valid)
391 DRM_INFO(" DDC Router 0x%x/0x%x\n",
392 amdgpu_connector->router.ddc_mux_control_pin,
393 amdgpu_connector->router.ddc_mux_state);
394 if (amdgpu_connector->router.cd_valid)
395 DRM_INFO(" Clock/Data Router 0x%x/0x%x\n",
396 amdgpu_connector->router.cd_mux_control_pin,
397 amdgpu_connector->router.cd_mux_state);
398 } else {
399 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
400 connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
401 connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
402 connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
403 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
404 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
405 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
406 }
407 DRM_INFO(" Encoders:\n");
408 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
409 amdgpu_encoder = to_amdgpu_encoder(encoder);
410 devices = amdgpu_encoder->devices & amdgpu_connector->devices;
411 if (devices) {
412 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
413 DRM_INFO(" CRT1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
414 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
415 DRM_INFO(" CRT2: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
416 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
417 DRM_INFO(" LCD1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
418 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
419 DRM_INFO(" DFP1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
420 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
421 DRM_INFO(" DFP2: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
422 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
423 DRM_INFO(" DFP3: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
424 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
425 DRM_INFO(" DFP4: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
426 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
427 DRM_INFO(" DFP5: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
428 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
429 DRM_INFO(" DFP6: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
430 if (devices & ATOM_DEVICE_TV1_SUPPORT)
431 DRM_INFO(" TV1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
432 if (devices & ATOM_DEVICE_CV_SUPPORT)
433 DRM_INFO(" CV: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
434 }
435 }
436 i++;
437 }
438 }
439
440 /**
441 * amdgpu_display_ddc_probe
442 *
443 */
444 bool amdgpu_display_ddc_probe(struct amdgpu_connector *amdgpu_connector,
445 bool use_aux)
446 {
447 u8 out = 0x0;
448 u8 buf[8];
449 int ret;
450 struct i2c_msg msgs[] = {
451 {
452 .addr = DDC_ADDR,
453 .flags = 0,
454 .len = 1,
455 .buf = &out,
456 },
457 {
458 .addr = DDC_ADDR,
459 .flags = I2C_M_RD,
460 .len = 8,
461 .buf = buf,
462 }
463 };
464
465 /* on hw with routers, select right port */
466 if (amdgpu_connector->router.ddc_valid)
467 amdgpu_i2c_router_select_ddc_port(amdgpu_connector);
468
469 if (use_aux) {
470 ret = i2c_transfer(&amdgpu_connector->ddc_bus->aux.ddc, msgs, 2);
471 } else {
472 ret = i2c_transfer(&amdgpu_connector->ddc_bus->adapter, msgs, 2);
473 }
474
475 if (ret != 2)
476 /* Couldn't find an accessible DDC on this connector */
477 return false;
478 /* Probe also for valid EDID header
479 * EDID header starts with:
480 * 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00.
481 * Only the first 6 bytes must be valid as
482 * drm_edid_block_valid() can fix the last 2 bytes */
483 if (drm_edid_header_is_valid(buf) < 6) {
484 /* Couldn't find an accessible EDID on this
485 * connector */
486 return false;
487 }
488 return true;
489 }
490
491 static const struct drm_framebuffer_funcs amdgpu_fb_funcs = {
492 .destroy = drm_gem_fb_destroy,
493 .create_handle = drm_gem_fb_create_handle,
494 };
495
496 uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev)
497 {
498 uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM;
499
500 #if defined(CONFIG_DRM_AMD_DC)
501 if (adev->asic_type >= CHIP_CARRIZO && adev->asic_type < CHIP_RAVEN &&
502 adev->flags & AMD_IS_APU &&
503 amdgpu_device_asic_has_dc_support(adev->asic_type))
504 domain |= AMDGPU_GEM_DOMAIN_GTT;
505 #endif
506
507 return domain;
508 }
509
510 int amdgpu_display_framebuffer_init(struct drm_device *dev,
511 struct amdgpu_framebuffer *rfb,
512 const struct drm_mode_fb_cmd2 *mode_cmd,
513 struct drm_gem_object *obj)
514 {
515 int ret;
516 rfb->base.obj[0] = obj;
517 drm_helper_mode_fill_fb_struct(dev, &rfb->base, mode_cmd);
518 ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs);
519 if (ret) {
520 rfb->base.obj[0] = NULL;
521 return ret;
522 }
523 return 0;
524 }
525
526 struct drm_framebuffer *
527 amdgpu_display_user_framebuffer_create(struct drm_device *dev,
528 struct drm_file *file_priv,
529 const struct drm_mode_fb_cmd2 *mode_cmd)
530 {
531 struct drm_gem_object *obj;
532 struct amdgpu_framebuffer *amdgpu_fb;
533 int ret;
534
535 obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]);
536 if (obj == NULL) {
537 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
538 "can't create framebuffer\n", mode_cmd->handles[0]);
539 return ERR_PTR(-ENOENT);
540 }
541
542 /* Handle is imported dma-buf, so cannot be migrated to VRAM for scanout */
543 if (obj->import_attach) {
544 DRM_DEBUG_KMS("Cannot create framebuffer from imported dma_buf\n");
545 return ERR_PTR(-EINVAL);
546 }
547
548 amdgpu_fb = kzalloc(sizeof(*amdgpu_fb), GFP_KERNEL);
549 if (amdgpu_fb == NULL) {
550 drm_gem_object_put_unlocked(obj);
551 return ERR_PTR(-ENOMEM);
552 }
553
554 ret = amdgpu_display_framebuffer_init(dev, amdgpu_fb, mode_cmd, obj);
555 if (ret) {
556 kfree(amdgpu_fb);
557 drm_gem_object_put_unlocked(obj);
558 return ERR_PTR(ret);
559 }
560
561 return &amdgpu_fb->base;
562 }
563
564 const struct drm_mode_config_funcs amdgpu_mode_funcs = {
565 .fb_create = amdgpu_display_user_framebuffer_create,
566 .output_poll_changed = drm_fb_helper_output_poll_changed,
567 };
568
569 static const struct drm_prop_enum_list amdgpu_underscan_enum_list[] =
570 { { UNDERSCAN_OFF, "off" },
571 { UNDERSCAN_ON, "on" },
572 { UNDERSCAN_AUTO, "auto" },
573 };
574
575 static const struct drm_prop_enum_list amdgpu_audio_enum_list[] =
576 { { AMDGPU_AUDIO_DISABLE, "off" },
577 { AMDGPU_AUDIO_ENABLE, "on" },
578 { AMDGPU_AUDIO_AUTO, "auto" },
579 };
580
581 /* XXX support different dither options? spatial, temporal, both, etc. */
582 static const struct drm_prop_enum_list amdgpu_dither_enum_list[] =
583 { { AMDGPU_FMT_DITHER_DISABLE, "off" },
584 { AMDGPU_FMT_DITHER_ENABLE, "on" },
585 };
586
587 int amdgpu_display_modeset_create_props(struct amdgpu_device *adev)
588 {
589 int sz;
590
591 adev->mode_info.coherent_mode_property =
592 drm_property_create_range(adev->ddev, 0 , "coherent", 0, 1);
593 if (!adev->mode_info.coherent_mode_property)
594 return -ENOMEM;
595
596 adev->mode_info.load_detect_property =
597 drm_property_create_range(adev->ddev, 0, "load detection", 0, 1);
598 if (!adev->mode_info.load_detect_property)
599 return -ENOMEM;
600
601 drm_mode_create_scaling_mode_property(adev->ddev);
602
603 sz = ARRAY_SIZE(amdgpu_underscan_enum_list);
604 adev->mode_info.underscan_property =
605 drm_property_create_enum(adev->ddev, 0,
606 "underscan",
607 amdgpu_underscan_enum_list, sz);
608
609 adev->mode_info.underscan_hborder_property =
610 drm_property_create_range(adev->ddev, 0,
611 "underscan hborder", 0, 128);
612 if (!adev->mode_info.underscan_hborder_property)
613 return -ENOMEM;
614
615 adev->mode_info.underscan_vborder_property =
616 drm_property_create_range(adev->ddev, 0,
617 "underscan vborder", 0, 128);
618 if (!adev->mode_info.underscan_vborder_property)
619 return -ENOMEM;
620
621 sz = ARRAY_SIZE(amdgpu_audio_enum_list);
622 adev->mode_info.audio_property =
623 drm_property_create_enum(adev->ddev, 0,
624 "audio",
625 amdgpu_audio_enum_list, sz);
626
627 sz = ARRAY_SIZE(amdgpu_dither_enum_list);
628 adev->mode_info.dither_property =
629 drm_property_create_enum(adev->ddev, 0,
630 "dither",
631 amdgpu_dither_enum_list, sz);
632
633 if (amdgpu_device_has_dc_support(adev)) {
634 adev->mode_info.max_bpc_property =
635 drm_property_create_range(adev->ddev, 0, "max bpc", 8, 16);
636 if (!adev->mode_info.max_bpc_property)
637 return -ENOMEM;
638 adev->mode_info.abm_level_property =
639 drm_property_create_range(adev->ddev, 0,
640 "abm level", 0, 4);
641 if (!adev->mode_info.abm_level_property)
642 return -ENOMEM;
643 }
644
645 return 0;
646 }
647
648 void amdgpu_display_update_priority(struct amdgpu_device *adev)
649 {
650 /* adjustment options for the display watermarks */
651 if ((amdgpu_disp_priority == 0) || (amdgpu_disp_priority > 2))
652 adev->mode_info.disp_priority = 0;
653 else
654 adev->mode_info.disp_priority = amdgpu_disp_priority;
655
656 }
657
658 static bool amdgpu_display_is_hdtv_mode(const struct drm_display_mode *mode)
659 {
660 /* try and guess if this is a tv or a monitor */
661 if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
662 (mode->vdisplay == 576) || /* 576p */
663 (mode->vdisplay == 720) || /* 720p */
664 (mode->vdisplay == 1080)) /* 1080p */
665 return true;
666 else
667 return false;
668 }
669
670 bool amdgpu_display_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
671 const struct drm_display_mode *mode,
672 struct drm_display_mode *adjusted_mode)
673 {
674 struct drm_device *dev = crtc->dev;
675 struct drm_encoder *encoder;
676 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
677 struct amdgpu_encoder *amdgpu_encoder;
678 struct drm_connector *connector;
679 struct amdgpu_connector *amdgpu_connector;
680 u32 src_v = 1, dst_v = 1;
681 u32 src_h = 1, dst_h = 1;
682
683 amdgpu_crtc->h_border = 0;
684 amdgpu_crtc->v_border = 0;
685
686 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
687 if (encoder->crtc != crtc)
688 continue;
689 amdgpu_encoder = to_amdgpu_encoder(encoder);
690 connector = amdgpu_get_connector_for_encoder(encoder);
691 amdgpu_connector = to_amdgpu_connector(connector);
692
693 /* set scaling */
694 if (amdgpu_encoder->rmx_type == RMX_OFF)
695 amdgpu_crtc->rmx_type = RMX_OFF;
696 else if (mode->hdisplay < amdgpu_encoder->native_mode.hdisplay ||
697 mode->vdisplay < amdgpu_encoder->native_mode.vdisplay)
698 amdgpu_crtc->rmx_type = amdgpu_encoder->rmx_type;
699 else
700 amdgpu_crtc->rmx_type = RMX_OFF;
701 /* copy native mode */
702 memcpy(&amdgpu_crtc->native_mode,
703 &amdgpu_encoder->native_mode,
704 sizeof(struct drm_display_mode));
705 src_v = crtc->mode.vdisplay;
706 dst_v = amdgpu_crtc->native_mode.vdisplay;
707 src_h = crtc->mode.hdisplay;
708 dst_h = amdgpu_crtc->native_mode.hdisplay;
709
710 /* fix up for overscan on hdmi */
711 if ((!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
712 ((amdgpu_encoder->underscan_type == UNDERSCAN_ON) ||
713 ((amdgpu_encoder->underscan_type == UNDERSCAN_AUTO) &&
714 drm_detect_hdmi_monitor(amdgpu_connector_edid(connector)) &&
715 amdgpu_display_is_hdtv_mode(mode)))) {
716 if (amdgpu_encoder->underscan_hborder != 0)
717 amdgpu_crtc->h_border = amdgpu_encoder->underscan_hborder;
718 else
719 amdgpu_crtc->h_border = (mode->hdisplay >> 5) + 16;
720 if (amdgpu_encoder->underscan_vborder != 0)
721 amdgpu_crtc->v_border = amdgpu_encoder->underscan_vborder;
722 else
723 amdgpu_crtc->v_border = (mode->vdisplay >> 5) + 16;
724 amdgpu_crtc->rmx_type = RMX_FULL;
725 src_v = crtc->mode.vdisplay;
726 dst_v = crtc->mode.vdisplay - (amdgpu_crtc->v_border * 2);
727 src_h = crtc->mode.hdisplay;
728 dst_h = crtc->mode.hdisplay - (amdgpu_crtc->h_border * 2);
729 }
730 }
731 if (amdgpu_crtc->rmx_type != RMX_OFF) {
732 fixed20_12 a, b;
733 a.full = dfixed_const(src_v);
734 b.full = dfixed_const(dst_v);
735 amdgpu_crtc->vsc.full = dfixed_div(a, b);
736 a.full = dfixed_const(src_h);
737 b.full = dfixed_const(dst_h);
738 amdgpu_crtc->hsc.full = dfixed_div(a, b);
739 } else {
740 amdgpu_crtc->vsc.full = dfixed_const(1);
741 amdgpu_crtc->hsc.full = dfixed_const(1);
742 }
743 return true;
744 }
745
746 /*
747 * Retrieve current video scanout position of crtc on a given gpu, and
748 * an optional accurate timestamp of when query happened.
749 *
750 * \param dev Device to query.
751 * \param pipe Crtc to query.
752 * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0).
753 * For driver internal use only also supports these flags:
754 *
755 * USE_REAL_VBLANKSTART to use the real start of vblank instead
756 * of a fudged earlier start of vblank.
757 *
758 * GET_DISTANCE_TO_VBLANKSTART to return distance to the
759 * fudged earlier start of vblank in *vpos and the distance
760 * to true start of vblank in *hpos.
761 *
762 * \param *vpos Location where vertical scanout position should be stored.
763 * \param *hpos Location where horizontal scanout position should go.
764 * \param *stime Target location for timestamp taken immediately before
765 * scanout position query. Can be NULL to skip timestamp.
766 * \param *etime Target location for timestamp taken immediately after
767 * scanout position query. Can be NULL to skip timestamp.
768 *
769 * Returns vpos as a positive number while in active scanout area.
770 * Returns vpos as a negative number inside vblank, counting the number
771 * of scanlines to go until end of vblank, e.g., -1 means "one scanline
772 * until start of active scanout / end of vblank."
773 *
774 * \return Flags, or'ed together as follows:
775 *
776 * DRM_SCANOUTPOS_VALID = Query successful.
777 * DRM_SCANOUTPOS_INVBL = Inside vblank.
778 * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
779 * this flag means that returned position may be offset by a constant but
780 * unknown small number of scanlines wrt. real scanout position.
781 *
782 */
783 int amdgpu_display_get_crtc_scanoutpos(struct drm_device *dev,
784 unsigned int pipe, unsigned int flags, int *vpos,
785 int *hpos, ktime_t *stime, ktime_t *etime,
786 const struct drm_display_mode *mode)
787 {
788 u32 vbl = 0, position = 0;
789 int vbl_start, vbl_end, vtotal, ret = 0;
790 bool in_vbl = true;
791
792 struct amdgpu_device *adev = dev->dev_private;
793
794 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
795
796 /* Get optional system timestamp before query. */
797 if (stime)
798 *stime = ktime_get();
799
800 if (amdgpu_display_page_flip_get_scanoutpos(adev, pipe, &vbl, &position) == 0)
801 ret |= DRM_SCANOUTPOS_VALID;
802
803 /* Get optional system timestamp after query. */
804 if (etime)
805 *etime = ktime_get();
806
807 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
808
809 /* Decode into vertical and horizontal scanout position. */
810 *vpos = position & 0x1fff;
811 *hpos = (position >> 16) & 0x1fff;
812
813 /* Valid vblank area boundaries from gpu retrieved? */
814 if (vbl > 0) {
815 /* Yes: Decode. */
816 ret |= DRM_SCANOUTPOS_ACCURATE;
817 vbl_start = vbl & 0x1fff;
818 vbl_end = (vbl >> 16) & 0x1fff;
819 }
820 else {
821 /* No: Fake something reasonable which gives at least ok results. */
822 vbl_start = mode->crtc_vdisplay;
823 vbl_end = 0;
824 }
825
826 /* Called from driver internal vblank counter query code? */
827 if (flags & GET_DISTANCE_TO_VBLANKSTART) {
828 /* Caller wants distance from real vbl_start in *hpos */
829 *hpos = *vpos - vbl_start;
830 }
831
832 /* Fudge vblank to start a few scanlines earlier to handle the
833 * problem that vblank irqs fire a few scanlines before start
834 * of vblank. Some driver internal callers need the true vblank
835 * start to be used and signal this via the USE_REAL_VBLANKSTART flag.
836 *
837 * The cause of the "early" vblank irq is that the irq is triggered
838 * by the line buffer logic when the line buffer read position enters
839 * the vblank, whereas our crtc scanout position naturally lags the
840 * line buffer read position.
841 */
842 if (!(flags & USE_REAL_VBLANKSTART))
843 vbl_start -= adev->mode_info.crtcs[pipe]->lb_vblank_lead_lines;
844
845 /* Test scanout position against vblank region. */
846 if ((*vpos < vbl_start) && (*vpos >= vbl_end))
847 in_vbl = false;
848
849 /* In vblank? */
850 if (in_vbl)
851 ret |= DRM_SCANOUTPOS_IN_VBLANK;
852
853 /* Called from driver internal vblank counter query code? */
854 if (flags & GET_DISTANCE_TO_VBLANKSTART) {
855 /* Caller wants distance from fudged earlier vbl_start */
856 *vpos -= vbl_start;
857 return ret;
858 }
859
860 /* Check if inside vblank area and apply corrective offsets:
861 * vpos will then be >=0 in video scanout area, but negative
862 * within vblank area, counting down the number of lines until
863 * start of scanout.
864 */
865
866 /* Inside "upper part" of vblank area? Apply corrective offset if so: */
867 if (in_vbl && (*vpos >= vbl_start)) {
868 vtotal = mode->crtc_vtotal;
869
870 /* With variable refresh rate displays the vpos can exceed
871 * the vtotal value. Clamp to 0 to return -vbl_end instead
872 * of guessing the remaining number of lines until scanout.
873 */
874 *vpos = (*vpos < vtotal) ? (*vpos - vtotal) : 0;
875 }
876
877 /* Correct for shifted end of vbl at vbl_end. */
878 *vpos = *vpos - vbl_end;
879
880 return ret;
881 }
882
883 int amdgpu_display_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc)
884 {
885 if (crtc < 0 || crtc >= adev->mode_info.num_crtc)
886 return AMDGPU_CRTC_IRQ_NONE;
887
888 switch (crtc) {
889 case 0:
890 return AMDGPU_CRTC_IRQ_VBLANK1;
891 case 1:
892 return AMDGPU_CRTC_IRQ_VBLANK2;
893 case 2:
894 return AMDGPU_CRTC_IRQ_VBLANK3;
895 case 3:
896 return AMDGPU_CRTC_IRQ_VBLANK4;
897 case 4:
898 return AMDGPU_CRTC_IRQ_VBLANK5;
899 case 5:
900 return AMDGPU_CRTC_IRQ_VBLANK6;
901 default:
902 return AMDGPU_CRTC_IRQ_NONE;
903 }
904 }
Linux with added FPC-III support