drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/ktime.h>
  29 #include <linux/pagemap.h>
  30 #include <drm/drmP.h>
  31 #include <drm/amdgpu_drm.h>
  32 #include "amdgpu.h"
  33 #include "amdgpu_display.h"
  34
  35 void amdgpu_gem_object_free(struct drm_gem_object *gobj)
  36 {
  37         struct amdgpu_bo *robj = gem_to_amdgpu_bo(gobj);
  38
  39         if (robj) {
  40                 amdgpu_mn_unregister(robj);
  41                 amdgpu_bo_unref(&robj);
  42         }
  43 }
  44
  45 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
  46                              int alignment, u32 initial_domain,
  47                              u64 flags, enum ttm_bo_type type,
  48                              struct reservation_object *resv,
  49                              struct drm_gem_object **obj)
  50 {
  51         struct amdgpu_bo *bo;
  52         struct amdgpu_bo_param bp;
  53         int r;
  54
  55         memset(&bp, 0, sizeof(bp));
  56         *obj = NULL;
  57
  58         bp.size = size;
  59         bp.byte_align = alignment;
  60         bp.type = type;
  61         bp.resv = resv;
  62         bp.preferred_domain = initial_domain;
  63 retry:
  64         bp.flags = flags;
  65         bp.domain = initial_domain;
  66         r = amdgpu_bo_create(adev, &bp, &bo);
  67         if (r) {
  68                 if (r != -ERESTARTSYS) {
  69                         if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) {
  70                                 flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
  71                                 goto retry;
  72                         }
  73
  74                         if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) {
  75                                 initial_domain |= AMDGPU_GEM_DOMAIN_GTT;
  76                                 goto retry;
  77                         }
  78                         DRM_DEBUG("Failed to allocate GEM object (%ld, %d, %u, %d)\n",
  79                                   size, initial_domain, alignment, r);
  80                 }
  81                 return r;
  82         }
  83         *obj = &bo->gem_base;
  84
  85         return 0;
  86 }
  87
  88 void amdgpu_gem_force_release(struct amdgpu_device *adev)
  89 {
  90         struct drm_device *ddev = adev->ddev;
  91         struct drm_file *file;
  92
  93         mutex_lock(&ddev->filelist_mutex);
  94
  95         list_for_each_entry(file, &ddev->filelist, lhead) {
  96                 struct drm_gem_object *gobj;
  97                 int handle;
  98
  99                 WARN_ONCE(1, "Still active user space clients!\n");
 100                 spin_lock(&file->table_lock);
 101                 idr_for_each_entry(&file->object_idr, gobj, handle) {
 102                         WARN_ONCE(1, "And also active allocations!\n");
 103                         drm_gem_object_put_unlocked(gobj);
 104                 }
 105                 idr_destroy(&file->object_idr);
 106                 spin_unlock(&file->table_lock);
 107         }
 108
 109         mutex_unlock(&ddev->filelist_mutex);
 110 }
 111
 112 /*
 113  * Call from drm_gem_handle_create which appear in both new and open ioctl
 114  * case.
 115  */
 116 int amdgpu_gem_object_open(struct drm_gem_object *obj,
 117                            struct drm_file *file_priv)
 118 {
 119         struct amdgpu_bo *abo = gem_to_amdgpu_bo(obj);
 120         struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
 121         struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
 122         struct amdgpu_vm *vm = &fpriv->vm;
 123         struct amdgpu_bo_va *bo_va;
 124         struct mm_struct *mm;
 125         int r;
 126
 127         mm = amdgpu_ttm_tt_get_usermm(abo->tbo.ttm);
 128         if (mm && mm != current->mm)
 129                 return -EPERM;
 130
 131         if (abo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID &&
 132             abo->tbo.resv != vm->root.base.bo->tbo.resv)
 133                 return -EPERM;
 134
 135         r = amdgpu_bo_reserve(abo, false);
 136         if (r)
 137                 return r;
 138
 139         bo_va = amdgpu_vm_bo_find(vm, abo);
 140         if (!bo_va) {
 141                 bo_va = amdgpu_vm_bo_add(adev, vm, abo);
 142         } else {
 143                 ++bo_va->ref_count;
 144         }
 145         amdgpu_bo_unreserve(abo);
 146         return 0;
 147 }
 148
 149 void amdgpu_gem_object_close(struct drm_gem_object *obj,
 150                              struct drm_file *file_priv)
 151 {
 152         struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
 153         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 154         struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
 155         struct amdgpu_vm *vm = &fpriv->vm;
 156
 157         struct amdgpu_bo_list_entry vm_pd;
 158         struct list_head list, duplicates;
 159         struct ttm_validate_buffer tv;
 160         struct ww_acquire_ctx ticket;
 161         struct amdgpu_bo_va *bo_va;
 162         int r;
 163
 164         INIT_LIST_HEAD(&list);
 165         INIT_LIST_HEAD(&duplicates);
 166
 167         tv.bo = &bo->tbo;
 168         tv.num_shared = 1;
 169         list_add(&tv.head, &list);
 170
 171         amdgpu_vm_get_pd_bo(vm, &list, &vm_pd);
 172
 173         r = ttm_eu_reserve_buffers(&ticket, &list, false, &duplicates);
 174         if (r) {
 175                 dev_err(adev->dev, "leaking bo va because "
 176                         "we fail to reserve bo (%d)\n", r);
 177                 return;
 178         }
 179         bo_va = amdgpu_vm_bo_find(vm, bo);
 180         if (bo_va && --bo_va->ref_count == 0) {
 181                 amdgpu_vm_bo_rmv(adev, bo_va);
 182
 183                 if (amdgpu_vm_ready(vm)) {
 184                         struct dma_fence *fence = NULL;
 185
 186                         r = amdgpu_vm_clear_freed(adev, vm, &fence);
 187                         if (unlikely(r)) {
 188                                 dev_err(adev->dev, "failed to clear page "
 189                                         "tables on GEM object close (%d)\n", r);
 190                         }
 191
 192                         if (fence) {
 193                                 amdgpu_bo_fence(bo, fence, true);
 194                                 dma_fence_put(fence);
 195                         }
 196                 }
 197         }
 198         ttm_eu_backoff_reservation(&ticket, &list);
 199 }
 200
 201 /*
 202  * GEM ioctls.
 203  */
 204 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
 205                             struct drm_file *filp)
 206 {
 207         struct amdgpu_device *adev = dev->dev_private;
 208         struct amdgpu_fpriv *fpriv = filp->driver_priv;
 209         struct amdgpu_vm *vm = &fpriv->vm;
 210         union drm_amdgpu_gem_create *args = data;
 211         uint64_t flags = args->in.domain_flags;
 212         uint64_t size = args->in.bo_size;
 213         struct reservation_object *resv = NULL;
 214         struct drm_gem_object *gobj;
 215         uint32_t handle;
 216         int r;
 217
 218         /* reject invalid gem flags */
 219         if (flags & ~(AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
 220                       AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
 221                       AMDGPU_GEM_CREATE_CPU_GTT_USWC |
 222                       AMDGPU_GEM_CREATE_VRAM_CLEARED |
 223                       AMDGPU_GEM_CREATE_VM_ALWAYS_VALID |
 224                       AMDGPU_GEM_CREATE_EXPLICIT_SYNC))
 225
 226                 return -EINVAL;
 227
 228         /* reject invalid gem domains */
 229         if (args->in.domains & ~AMDGPU_GEM_DOMAIN_MASK)
 230                 return -EINVAL;
 231
 232         /* create a gem object to contain this object in */
 233         if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS |
 234             AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) {
 235                 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) {
 236                         /* if gds bo is created from user space, it must be
 237                          * passed to bo list
 238                          */
 239                         DRM_ERROR("GDS bo cannot be per-vm-bo\n");
 240                         return -EINVAL;
 241                 }
 242                 flags |= AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
 243         }
 244
 245         if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) {
 246                 r = amdgpu_bo_reserve(vm->root.base.bo, false);
 247                 if (r)
 248                         return r;
 249
 250                 resv = vm->root.base.bo->tbo.resv;
 251         }
 252
 253         r = amdgpu_gem_object_create(adev, size, args->in.alignment,
 254                                      (u32)(0xffffffff & args->in.domains),
 255                                      flags, ttm_bo_type_device, resv, &gobj);
 256         if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) {
 257                 if (!r) {
 258                         struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj);
 259
 260                         abo->parent = amdgpu_bo_ref(vm->root.base.bo);
 261                 }
 262                 amdgpu_bo_unreserve(vm->root.base.bo);
 263         }
 264         if (r)
 265                 return r;
 266
 267         r = drm_gem_handle_create(filp, gobj, &handle);
 268         /* drop reference from allocate - handle holds it now */
 269         drm_gem_object_put_unlocked(gobj);
 270         if (r)
 271                 return r;
 272
 273         memset(args, 0, sizeof(*args));
 274         args->out.handle = handle;
 275         return 0;
 276 }
 277
 278 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
 279                              struct drm_file *filp)
 280 {
 281         struct ttm_operation_ctx ctx = { true, false };
 282         struct amdgpu_device *adev = dev->dev_private;
 283         struct drm_amdgpu_gem_userptr *args = data;
 284         struct drm_gem_object *gobj;
 285         struct amdgpu_bo *bo;
 286         uint32_t handle;
 287         int r;
 288
 289         if (offset_in_page(args->addr | args->size))
 290                 return -EINVAL;
 291
 292         /* reject unknown flag values */
 293         if (args->flags & ~(AMDGPU_GEM_USERPTR_READONLY |
 294             AMDGPU_GEM_USERPTR_ANONONLY | AMDGPU_GEM_USERPTR_VALIDATE |
 295             AMDGPU_GEM_USERPTR_REGISTER))
 296                 return -EINVAL;
 297
 298         if (!(args->flags & AMDGPU_GEM_USERPTR_READONLY) &&
 299              !(args->flags & AMDGPU_GEM_USERPTR_REGISTER)) {
 300
 301                 /* if we want to write to it we must install a MMU notifier */
 302                 return -EACCES;
 303         }
 304
 305         /* create a gem object to contain this object in */
 306         r = amdgpu_gem_object_create(adev, args->size, 0, AMDGPU_GEM_DOMAIN_CPU,
 307                                      0, ttm_bo_type_device, NULL, &gobj);
 308         if (r)
 309                 return r;
 310
 311         bo = gem_to_amdgpu_bo(gobj);
 312         bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT;
 313         bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT;
 314         r = amdgpu_ttm_tt_set_userptr(bo->tbo.ttm, args->addr, args->flags);
 315         if (r)
 316                 goto release_object;
 317
 318         if (args->flags & AMDGPU_GEM_USERPTR_REGISTER) {
 319                 r = amdgpu_mn_register(bo, args->addr);
 320                 if (r)
 321                         goto release_object;
 322         }
 323
 324         if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) {
 325                 r = amdgpu_ttm_tt_get_user_pages(bo->tbo.ttm,
 326                                                  bo->tbo.ttm->pages);
 327                 if (r)
 328                         goto release_object;
 329
 330                 r = amdgpu_bo_reserve(bo, true);
 331                 if (r)
 332                         goto free_pages;
 333
 334                 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
 335                 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 336                 amdgpu_bo_unreserve(bo);
 337                 if (r)
 338                         goto free_pages;
 339         }
 340
 341         r = drm_gem_handle_create(filp, gobj, &handle);
 342         /* drop reference from allocate - handle holds it now */
 343         drm_gem_object_put_unlocked(gobj);
 344         if (r)
 345                 return r;
 346
 347         args->handle = handle;
 348         return 0;
 349
 350 free_pages:
 351         release_pages(bo->tbo.ttm->pages, bo->tbo.ttm->num_pages);
 352
 353 release_object:
 354         drm_gem_object_put_unlocked(gobj);
 355
 356         return r;
 357 }
 358
 359 int amdgpu_mode_dumb_mmap(struct drm_file *filp,
 360                           struct drm_device *dev,
 361                           uint32_t handle, uint64_t *offset_p)
 362 {
 363         struct drm_gem_object *gobj;
 364         struct amdgpu_bo *robj;
 365
 366         gobj = drm_gem_object_lookup(filp, handle);
 367         if (gobj == NULL) {
 368                 return -ENOENT;
 369         }
 370         robj = gem_to_amdgpu_bo(gobj);
 371         if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm) ||
 372             (robj->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) {
 373                 drm_gem_object_put_unlocked(gobj);
 374                 return -EPERM;
 375         }
 376         *offset_p = amdgpu_bo_mmap_offset(robj);
 377         drm_gem_object_put_unlocked(gobj);
 378         return 0;
 379 }
 380
 381 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
 382                           struct drm_file *filp)
 383 {
 384         union drm_amdgpu_gem_mmap *args = data;
 385         uint32_t handle = args->in.handle;
 386         memset(args, 0, sizeof(*args));
 387         return amdgpu_mode_dumb_mmap(filp, dev, handle, &args->out.addr_ptr);
 388 }
 389
 390 /**
 391  * amdgpu_gem_timeout - calculate jiffies timeout from absolute value
 392  *
 393  * @timeout_ns: timeout in ns
 394  *
 395  * Calculate the timeout in jiffies from an absolute timeout in ns.
 396  */
 397 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns)
 398 {
 399         unsigned long timeout_jiffies;
 400         ktime_t timeout;
 401
 402         /* clamp timeout if it's to large */
 403         if (((int64_t)timeout_ns) < 0)
 404                 return MAX_SCHEDULE_TIMEOUT;
 405
 406         timeout = ktime_sub(ns_to_ktime(timeout_ns), ktime_get());
 407         if (ktime_to_ns(timeout) < 0)
 408                 return 0;
 409
 410         timeout_jiffies = nsecs_to_jiffies(ktime_to_ns(timeout));
 411         /*  clamp timeout to avoid unsigned-> signed overflow */
 412         if (timeout_jiffies > MAX_SCHEDULE_TIMEOUT )
 413                 return MAX_SCHEDULE_TIMEOUT - 1;
 414
 415         return timeout_jiffies;
 416 }
 417
 418 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
 419                               struct drm_file *filp)
 420 {
 421         union drm_amdgpu_gem_wait_idle *args = data;
 422         struct drm_gem_object *gobj;
 423         struct amdgpu_bo *robj;
 424         uint32_t handle = args->in.handle;
 425         unsigned long timeout = amdgpu_gem_timeout(args->in.timeout);
 426         int r = 0;
 427         long ret;
 428
 429         gobj = drm_gem_object_lookup(filp, handle);
 430         if (gobj == NULL) {
 431                 return -ENOENT;
 432         }
 433         robj = gem_to_amdgpu_bo(gobj);
 434         ret = reservation_object_wait_timeout_rcu(robj->tbo.resv, true, true,
 435                                                   timeout);
 436
 437         /* ret == 0 means not signaled,
 438          * ret > 0 means signaled
 439          * ret < 0 means interrupted before timeout
 440          */
 441         if (ret >= 0) {
 442                 memset(args, 0, sizeof(*args));
 443                 args->out.status = (ret == 0);
 444         } else
 445                 r = ret;
 446
 447         drm_gem_object_put_unlocked(gobj);
 448         return r;
 449 }
 450
 451 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
 452                                 struct drm_file *filp)
 453 {
 454         struct drm_amdgpu_gem_metadata *args = data;
 455         struct drm_gem_object *gobj;
 456         struct amdgpu_bo *robj;
 457         int r = -1;
 458
 459         DRM_DEBUG("%d \n", args->handle);
 460         gobj = drm_gem_object_lookup(filp, args->handle);
 461         if (gobj == NULL)
 462                 return -ENOENT;
 463         robj = gem_to_amdgpu_bo(gobj);
 464
 465         r = amdgpu_bo_reserve(robj, false);
 466         if (unlikely(r != 0))
 467                 goto out;
 468
 469         if (args->op == AMDGPU_GEM_METADATA_OP_GET_METADATA) {
 470                 amdgpu_bo_get_tiling_flags(robj, &args->data.tiling_info);
 471                 r = amdgpu_bo_get_metadata(robj, args->data.data,
 472                                            sizeof(args->data.data),
 473                                            &args->data.data_size_bytes,
 474                                            &args->data.flags);
 475         } else if (args->op == AMDGPU_GEM_METADATA_OP_SET_METADATA) {
 476                 if (args->data.data_size_bytes > sizeof(args->data.data)) {
 477                         r = -EINVAL;
 478                         goto unreserve;
 479                 }
 480                 r = amdgpu_bo_set_tiling_flags(robj, args->data.tiling_info);
 481                 if (!r)
 482                         r = amdgpu_bo_set_metadata(robj, args->data.data,
 483                                                    args->data.data_size_bytes,
 484                                                    args->data.flags);
 485         }
 486
 487 unreserve:
 488         amdgpu_bo_unreserve(robj);
 489 out:
 490         drm_gem_object_put_unlocked(gobj);
 491         return r;
 492 }
 493
 494 /**
 495  * amdgpu_gem_va_update_vm -update the bo_va in its VM
 496  *
 497  * @adev: amdgpu_device pointer
 498  * @vm: vm to update
 499  * @bo_va: bo_va to update
 500  * @operation: map, unmap or clear
 501  *
 502  * Update the bo_va directly after setting its address. Errors are not
 503  * vital here, so they are not reported back to userspace.
 504  */
 505 static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev,
 506                                     struct amdgpu_vm *vm,
 507                                     struct amdgpu_bo_va *bo_va,
 508                                     uint32_t operation)
 509 {
 510         int r;
 511
 512         if (!amdgpu_vm_ready(vm))
 513                 return;
 514
 515         r = amdgpu_vm_clear_freed(adev, vm, NULL);
 516         if (r)
 517                 goto error;
 518
 519         if (operation == AMDGPU_VA_OP_MAP ||
 520             operation == AMDGPU_VA_OP_REPLACE) {
 521                 r = amdgpu_vm_bo_update(adev, bo_va, false);
 522                 if (r)
 523                         goto error;
 524         }
 525
 526         r = amdgpu_vm_update_directories(adev, vm);
 527
 528 error:
 529         if (r && r != -ERESTARTSYS)
 530                 DRM_ERROR("Couldn't update BO_VA (%d)\n", r);
 531 }
 532
 533 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
 534                           struct drm_file *filp)
 535 {
 536         const uint32_t valid_flags = AMDGPU_VM_DELAY_UPDATE |
 537                 AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE |
 538                 AMDGPU_VM_PAGE_EXECUTABLE | AMDGPU_VM_MTYPE_MASK;
 539         const uint32_t prt_flags = AMDGPU_VM_DELAY_UPDATE |
 540                 AMDGPU_VM_PAGE_PRT;
 541
 542         struct drm_amdgpu_gem_va *args = data;
 543         struct drm_gem_object *gobj;
 544         struct amdgpu_device *adev = dev->dev_private;
 545         struct amdgpu_fpriv *fpriv = filp->driver_priv;
 546         struct amdgpu_bo *abo;
 547         struct amdgpu_bo_va *bo_va;
 548         struct amdgpu_bo_list_entry vm_pd;
 549         struct ttm_validate_buffer tv;
 550         struct ww_acquire_ctx ticket;
 551         struct list_head list, duplicates;
 552         uint64_t va_flags;
 553         int r = 0;
 554
 555         if (args->va_address < AMDGPU_VA_RESERVED_SIZE) {
 556                 dev_dbg(&dev->pdev->dev,
 557                         "va_address 0x%LX is in reserved area 0x%LX\n",
 558                         args->va_address, AMDGPU_VA_RESERVED_SIZE);
 559                 return -EINVAL;
 560         }
 561
 562         if (args->va_address >= AMDGPU_GMC_HOLE_START &&
 563             args->va_address < AMDGPU_GMC_HOLE_END) {
 564                 dev_dbg(&dev->pdev->dev,
 565                         "va_address 0x%LX is in VA hole 0x%LX-0x%LX\n",
 566                         args->va_address, AMDGPU_GMC_HOLE_START,
 567                         AMDGPU_GMC_HOLE_END);
 568                 return -EINVAL;
 569         }
 570
 571         args->va_address &= AMDGPU_GMC_HOLE_MASK;
 572
 573         if ((args->flags & ~valid_flags) && (args->flags & ~prt_flags)) {
 574                 dev_dbg(&dev->pdev->dev, "invalid flags combination 0x%08X\n",
 575                         args->flags);
 576                 return -EINVAL;
 577         }
 578
 579         switch (args->operation) {
 580         case AMDGPU_VA_OP_MAP:
 581         case AMDGPU_VA_OP_UNMAP:
 582         case AMDGPU_VA_OP_CLEAR:
 583         case AMDGPU_VA_OP_REPLACE:
 584                 break;
 585         default:
 586                 dev_dbg(&dev->pdev->dev, "unsupported operation %d\n",
 587                         args->operation);
 588                 return -EINVAL;
 589         }
 590
 591         INIT_LIST_HEAD(&list);
 592         INIT_LIST_HEAD(&duplicates);
 593         if ((args->operation != AMDGPU_VA_OP_CLEAR) &&
 594             !(args->flags & AMDGPU_VM_PAGE_PRT)) {
 595                 gobj = drm_gem_object_lookup(filp, args->handle);
 596                 if (gobj == NULL)
 597                         return -ENOENT;
 598                 abo = gem_to_amdgpu_bo(gobj);
 599                 tv.bo = &abo->tbo;
 600                 if (abo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID)
 601                         tv.num_shared = 1;
 602                 else
 603                         tv.num_shared = 0;
 604                 list_add(&tv.head, &list);
 605         } else {
 606                 gobj = NULL;
 607                 abo = NULL;
 608         }
 609
 610         amdgpu_vm_get_pd_bo(&fpriv->vm, &list, &vm_pd);
 611
 612         r = ttm_eu_reserve_buffers(&ticket, &list, true, &duplicates);
 613         if (r)
 614                 goto error_unref;
 615
 616         if (abo) {
 617                 bo_va = amdgpu_vm_bo_find(&fpriv->vm, abo);
 618                 if (!bo_va) {
 619                         r = -ENOENT;
 620                         goto error_backoff;
 621                 }
 622         } else if (args->operation != AMDGPU_VA_OP_CLEAR) {
 623                 bo_va = fpriv->prt_va;
 624         } else {
 625                 bo_va = NULL;
 626         }
 627
 628         switch (args->operation) {
 629         case AMDGPU_VA_OP_MAP:
 630                 r = amdgpu_vm_alloc_pts(adev, bo_va->base.vm, args->va_address,
 631                                         args->map_size);
 632                 if (r)
 633                         goto error_backoff;
 634
 635                 va_flags = amdgpu_gmc_get_pte_flags(adev, args->flags);
 636                 r = amdgpu_vm_bo_map(adev, bo_va, args->va_address,
 637                                      args->offset_in_bo, args->map_size,
 638                                      va_flags);
 639                 break;
 640         case AMDGPU_VA_OP_UNMAP:
 641                 r = amdgpu_vm_bo_unmap(adev, bo_va, args->va_address);
 642                 break;
 643
 644         case AMDGPU_VA_OP_CLEAR:
 645                 r = amdgpu_vm_bo_clear_mappings(adev, &fpriv->vm,
 646                                                 args->va_address,
 647                                                 args->map_size);
 648                 break;
 649         case AMDGPU_VA_OP_REPLACE:
 650                 r = amdgpu_vm_alloc_pts(adev, bo_va->base.vm, args->va_address,
 651                                         args->map_size);
 652                 if (r)
 653                         goto error_backoff;
 654
 655                 va_flags = amdgpu_gmc_get_pte_flags(adev, args->flags);
 656                 r = amdgpu_vm_bo_replace_map(adev, bo_va, args->va_address,
 657                                              args->offset_in_bo, args->map_size,
 658                                              va_flags);
 659                 break;
 660         default:
 661                 break;
 662         }
 663         if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE) && !amdgpu_vm_debug)
 664                 amdgpu_gem_va_update_vm(adev, &fpriv->vm, bo_va,
 665                                         args->operation);
 666
 667 error_backoff:
 668         ttm_eu_backoff_reservation(&ticket, &list);
 669
 670 error_unref:
 671         drm_gem_object_put_unlocked(gobj);
 672         return r;
 673 }
 674
 675 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
 676                         struct drm_file *filp)
 677 {
 678         struct amdgpu_device *adev = dev->dev_private;
 679         struct drm_amdgpu_gem_op *args = data;
 680         struct drm_gem_object *gobj;
 681         struct amdgpu_bo *robj;
 682         int r;
 683
 684         gobj = drm_gem_object_lookup(filp, args->handle);
 685         if (gobj == NULL) {
 686                 return -ENOENT;
 687         }
 688         robj = gem_to_amdgpu_bo(gobj);
 689
 690         r = amdgpu_bo_reserve(robj, false);
 691         if (unlikely(r))
 692                 goto out;
 693
 694         switch (args->op) {
 695         case AMDGPU_GEM_OP_GET_GEM_CREATE_INFO: {
 696                 struct drm_amdgpu_gem_create_in info;
 697                 void __user *out = u64_to_user_ptr(args->value);
 698
 699                 info.bo_size = robj->gem_base.size;
 700                 info.alignment = robj->tbo.mem.page_alignment << PAGE_SHIFT;
 701                 info.domains = robj->preferred_domains;
 702                 info.domain_flags = robj->flags;
 703                 amdgpu_bo_unreserve(robj);
 704                 if (copy_to_user(out, &info, sizeof(info)))
 705                         r = -EFAULT;
 706                 break;
 707         }
 708         case AMDGPU_GEM_OP_SET_PLACEMENT:
 709                 if (robj->prime_shared_count && (args->value & AMDGPU_GEM_DOMAIN_VRAM)) {
 710                         r = -EINVAL;
 711                         amdgpu_bo_unreserve(robj);
 712                         break;
 713                 }
 714                 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm)) {
 715                         r = -EPERM;
 716                         amdgpu_bo_unreserve(robj);
 717                         break;
 718                 }
 719                 robj->preferred_domains = args->value & (AMDGPU_GEM_DOMAIN_VRAM |
 720                                                         AMDGPU_GEM_DOMAIN_GTT |
 721                                                         AMDGPU_GEM_DOMAIN_CPU);
 722                 robj->allowed_domains = robj->preferred_domains;
 723                 if (robj->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM)
 724                         robj->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT;
 725
 726                 if (robj->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID)
 727                         amdgpu_vm_bo_invalidate(adev, robj, true);
 728
 729                 amdgpu_bo_unreserve(robj);
 730                 break;
 731         default:
 732                 amdgpu_bo_unreserve(robj);
 733                 r = -EINVAL;
 734         }
 735
 736 out:
 737         drm_gem_object_put_unlocked(gobj);
 738         return r;
 739 }
 740
 741 int amdgpu_mode_dumb_create(struct drm_file *file_priv,
 742                             struct drm_device *dev,
 743                             struct drm_mode_create_dumb *args)
 744 {
 745         struct amdgpu_device *adev = dev->dev_private;
 746         struct drm_gem_object *gobj;
 747         uint32_t handle;
 748         u32 domain;
 749         int r;
 750
 751         args->pitch = amdgpu_align_pitch(adev, args->width,
 752                                          DIV_ROUND_UP(args->bpp, 8), 0);
 753         args->size = (u64)args->pitch * args->height;
 754         args->size = ALIGN(args->size, PAGE_SIZE);
 755         domain = amdgpu_bo_get_preferred_pin_domain(adev,
 756                                 amdgpu_display_supported_domains(adev));
 757         r = amdgpu_gem_object_create(adev, args->size, 0, domain,
 758                                      AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
 759                                      ttm_bo_type_device, NULL, &gobj);
 760         if (r)
 761                 return -ENOMEM;
 762
 763         r = drm_gem_handle_create(file_priv, gobj, &handle);
 764         /* drop reference from allocate - handle holds it now */
 765         drm_gem_object_put_unlocked(gobj);
 766         if (r) {
 767                 return r;
 768         }
 769         args->handle = handle;
 770         return 0;
 771 }
 772
 773 #if defined(CONFIG_DEBUG_FS)
 774
 775 #define amdgpu_debugfs_gem_bo_print_flag(m, bo, flag)   \
 776         if (bo->flags & (AMDGPU_GEM_CREATE_ ## flag)) { \
 777                 seq_printf((m), " " #flag);             \
 778         }
 779
 780 static int amdgpu_debugfs_gem_bo_info(int id, void *ptr, void *data)
 781 {
 782         struct drm_gem_object *gobj = ptr;
 783         struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj);
 784         struct seq_file *m = data;
 785
 786         struct dma_buf_attachment *attachment;
 787         struct dma_buf *dma_buf;
 788         unsigned domain;
 789         const char *placement;
 790         unsigned pin_count;
 791
 792         domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
 793         switch (domain) {
 794         case AMDGPU_GEM_DOMAIN_VRAM:
 795                 placement = "VRAM";
 796                 break;
 797         case AMDGPU_GEM_DOMAIN_GTT:
 798                 placement = " GTT";
 799                 break;
 800         case AMDGPU_GEM_DOMAIN_CPU:
 801         default:
 802                 placement = " CPU";
 803                 break;
 804         }
 805         seq_printf(m, "\t0x%08x: %12ld byte %s",
 806                    id, amdgpu_bo_size(bo), placement);
 807
 808         pin_count = READ_ONCE(bo->pin_count);
 809         if (pin_count)
 810                 seq_printf(m, " pin count %d", pin_count);
 811
 812         dma_buf = READ_ONCE(bo->gem_base.dma_buf);
 813         attachment = READ_ONCE(bo->gem_base.import_attach);
 814
 815         if (attachment)
 816                 seq_printf(m, " imported from %p", dma_buf);
 817         else if (dma_buf)
 818                 seq_printf(m, " exported as %p", dma_buf);
 819
 820         amdgpu_debugfs_gem_bo_print_flag(m, bo, CPU_ACCESS_REQUIRED);
 821         amdgpu_debugfs_gem_bo_print_flag(m, bo, NO_CPU_ACCESS);
 822         amdgpu_debugfs_gem_bo_print_flag(m, bo, CPU_GTT_USWC);
 823         amdgpu_debugfs_gem_bo_print_flag(m, bo, VRAM_CLEARED);
 824         amdgpu_debugfs_gem_bo_print_flag(m, bo, SHADOW);
 825         amdgpu_debugfs_gem_bo_print_flag(m, bo, VRAM_CONTIGUOUS);
 826         amdgpu_debugfs_gem_bo_print_flag(m, bo, VM_ALWAYS_VALID);
 827         amdgpu_debugfs_gem_bo_print_flag(m, bo, EXPLICIT_SYNC);
 828
 829         seq_printf(m, "\n");
 830
 831         return 0;
 832 }
 833
 834 static int amdgpu_debugfs_gem_info(struct seq_file *m, void *data)
 835 {
 836         struct drm_info_node *node = (struct drm_info_node *)m->private;
 837         struct drm_device *dev = node->minor->dev;
 838         struct drm_file *file;
 839         int r;
 840
 841         r = mutex_lock_interruptible(&dev->filelist_mutex);
 842         if (r)
 843                 return r;
 844
 845         list_for_each_entry(file, &dev->filelist, lhead) {
 846                 struct task_struct *task;
 847
 848                 /*
 849                  * Although we have a valid reference on file->pid, that does
 850                  * not guarantee that the task_struct who called get_pid() is
 851                  * still alive (e.g. get_pid(current) => fork() => exit()).
 852                  * Therefore, we need to protect this ->comm access using RCU.
 853                  */
 854                 rcu_read_lock();
 855                 task = pid_task(file->pid, PIDTYPE_PID);
 856                 seq_printf(m, "pid %8d command %s:\n", pid_nr(file->pid),
 857                            task ? task->comm : "<unknown>");
 858                 rcu_read_unlock();
 859
 860                 spin_lock(&file->table_lock);
 861                 idr_for_each(&file->object_idr, amdgpu_debugfs_gem_bo_info, m);
 862                 spin_unlock(&file->table_lock);
 863         }
 864
 865         mutex_unlock(&dev->filelist_mutex);
 866         return 0;
 867 }
 868
 869 static const struct drm_info_list amdgpu_debugfs_gem_list[] = {
 870         {"amdgpu_gem_info", &amdgpu_debugfs_gem_info, 0, NULL},
 871 };
 872 #endif
 873
 874 int amdgpu_debugfs_gem_init(struct amdgpu_device *adev)
 875 {
 876 #if defined(CONFIG_DEBUG_FS)
 877         return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_gem_list, 1);
 878 #endif
 879         return 0;
 880 }