drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 #ifndef __AMDGPU_GMC_H__
  27 #define __AMDGPU_GMC_H__
  28
  29 #include <linux/types.h>
  30
  31 #include "amdgpu_irq.h"
  32
  33 /* VA hole for 48bit addresses on Vega10 */
  34 #define AMDGPU_GMC_HOLE_START   0x0000800000000000ULL
  35 #define AMDGPU_GMC_HOLE_END     0xffff800000000000ULL
  36
  37 /*
  38  * Hardware is programmed as if the hole doesn't exists with start and end
  39  * address values.
  40  *
  41  * This mask is used to remove the upper 16bits of the VA and so come up with
  42  * the linear addr value.
  43  */
  44 #define AMDGPU_GMC_HOLE_MASK    0x0000ffffffffffffULL
  45
  46 struct firmware;
  47
  48 /*
  49  * VMHUB structures, functions & helpers
  50  */
  51 struct amdgpu_vmhub {
  52         uint32_t        ctx0_ptb_addr_lo32;
  53         uint32_t        ctx0_ptb_addr_hi32;
  54         uint32_t        vm_inv_eng0_req;
  55         uint32_t        vm_inv_eng0_ack;
  56         uint32_t        vm_context0_cntl;
  57         uint32_t        vm_l2_pro_fault_status;
  58         uint32_t        vm_l2_pro_fault_cntl;
  59 };
  60
  61 /*
  62  * GPU MC structures, functions & helpers
  63  */
  64 struct amdgpu_gmc_funcs {
  65         /* flush the vm tlb via mmio */
  66         void (*flush_gpu_tlb)(struct amdgpu_device *adev,
  67                               uint32_t vmid, uint32_t flush_type);
  68         /* flush the vm tlb via ring */
  69         uint64_t (*emit_flush_gpu_tlb)(struct amdgpu_ring *ring, unsigned vmid,
  70                                        uint64_t pd_addr);
  71         /* Change the VMID -> PASID mapping */
  72         void (*emit_pasid_mapping)(struct amdgpu_ring *ring, unsigned vmid,
  73                                    unsigned pasid);
  74         /* write pte/pde updates using the cpu */
  75         int (*set_pte_pde)(struct amdgpu_device *adev,
  76                            void *cpu_pt_addr, /* cpu addr of page table */
  77                            uint32_t gpu_page_idx, /* pte/pde to update */
  78                            uint64_t addr, /* addr to write into pte/pde */
  79                            uint64_t flags); /* access flags */
  80         /* enable/disable PRT support */
  81         void (*set_prt)(struct amdgpu_device *adev, bool enable);
  82         /* set pte flags based per asic */
  83         uint64_t (*get_vm_pte_flags)(struct amdgpu_device *adev,
  84                                      uint32_t flags);
  85         /* get the pde for a given mc addr */
  86         void (*get_vm_pde)(struct amdgpu_device *adev, int level,
  87                            u64 *dst, u64 *flags);
  88 };
  89
  90 struct amdgpu_xgmi {
  91         /* from psp */
  92         u64 node_id;
  93         u64 hive_id;
  94         /* fixed per family */
  95         u64 node_segment_size;
  96         /* physical node (0-3) */
  97         unsigned physical_node_id;
  98         /* number of nodes (0-4) */
  99         unsigned num_physical_nodes;
 100         /* gpu list in the same hive */
 101         struct list_head head;
 102         bool supported;
 103 };
 104
 105 struct amdgpu_gmc {
 106         resource_size_t         aper_size;
 107         resource_size_t         aper_base;
 108         /* for some chips with <= 32MB we need to lie
 109          * about vram size near mc fb location */
 110         u64                     mc_vram_size;
 111         u64                     visible_vram_size;
 112         u64                     agp_size;
 113         u64                     agp_start;
 114         u64                     agp_end;
 115         u64                     gart_size;
 116         u64                     gart_start;
 117         u64                     gart_end;
 118         u64                     vram_start;
 119         u64                     vram_end;
 120         /* FB region , it's same as local vram region in single GPU, in XGMI
 121          * configuration, this region covers all GPUs in the same hive ,
 122          * each GPU in the hive has the same view of this FB region .
 123          * GPU0's vram starts at offset (0 * segment size) ,
 124          * GPU1 starts at offset (1 * segment size), etc.
 125          */
 126         u64                     fb_start;
 127         u64                     fb_end;
 128         unsigned                vram_width;
 129         u64                     real_vram_size;
 130         int                     vram_mtrr;
 131         u64                     mc_mask;
 132         const struct firmware   *fw;    /* MC firmware */
 133         uint32_t                fw_version;
 134         struct amdgpu_irq_src   vm_fault;
 135         uint32_t                vram_type;
 136         uint32_t                srbm_soft_reset;
 137         bool                    prt_warning;
 138         uint64_t                stolen_size;
 139         /* apertures */
 140         u64                     shared_aperture_start;
 141         u64                     shared_aperture_end;
 142         u64                     private_aperture_start;
 143         u64                     private_aperture_end;
 144         /* protects concurrent invalidation */
 145         spinlock_t              invalidate_lock;
 146         bool                    translate_further;
 147         struct kfd_vm_fault_info *vm_fault_info;
 148         atomic_t                vm_fault_info_updated;
 149
 150         const struct amdgpu_gmc_funcs   *gmc_funcs;
 151
 152         struct amdgpu_xgmi xgmi;
 153 };
 154
 155 #define amdgpu_gmc_flush_gpu_tlb(adev, vmid, type) (adev)->gmc.gmc_funcs->flush_gpu_tlb((adev), (vmid), (type))
 156 #define amdgpu_gmc_emit_flush_gpu_tlb(r, vmid, addr) (r)->adev->gmc.gmc_funcs->emit_flush_gpu_tlb((r), (vmid), (addr))
 157 #define amdgpu_gmc_emit_pasid_mapping(r, vmid, pasid) (r)->adev->gmc.gmc_funcs->emit_pasid_mapping((r), (vmid), (pasid))
 158 #define amdgpu_gmc_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gmc.gmc_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
 159 #define amdgpu_gmc_get_vm_pde(adev, level, dst, flags) (adev)->gmc.gmc_funcs->get_vm_pde((adev), (level), (dst), (flags))
 160 #define amdgpu_gmc_get_pte_flags(adev, flags) (adev)->gmc.gmc_funcs->get_vm_pte_flags((adev),(flags))
 161
 162 /**
 163  * amdgpu_gmc_vram_full_visible - Check if full VRAM is visible through the BAR
 164  *
 165  * @adev: amdgpu_device pointer
 166  *
 167  * Returns:
 168  * True if full VRAM is visible through the BAR
 169  */
 170 static inline bool amdgpu_gmc_vram_full_visible(struct amdgpu_gmc *gmc)
 171 {
 172         WARN_ON(gmc->real_vram_size < gmc->visible_vram_size);
 173
 174         return (gmc->real_vram_size == gmc->visible_vram_size);
 175 }
 176
 177 /**
 178  * amdgpu_gmc_sign_extend - sign extend the given gmc address
 179  *
 180  * @addr: address to extend
 181  */
 182 static inline uint64_t amdgpu_gmc_sign_extend(uint64_t addr)
 183 {
 184         if (addr >= AMDGPU_GMC_HOLE_START)
 185                 addr |= AMDGPU_GMC_HOLE_END;
 186
 187         return addr;
 188 }
 189
 190 void amdgpu_gmc_get_pde_for_bo(struct amdgpu_bo *bo, int level,
 191                                uint64_t *addr, uint64_t *flags);
 192 uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo);
 193 uint64_t amdgpu_gmc_agp_addr(struct ttm_buffer_object *bo);
 194 void amdgpu_gmc_vram_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc,
 195                               u64 base);
 196 void amdgpu_gmc_gart_location(struct amdgpu_device *adev,
 197                               struct amdgpu_gmc *mc);
 198 void amdgpu_gmc_agp_location(struct amdgpu_device *adev,
 199                              struct amdgpu_gmc *mc);
 200
 201 #endif