drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #ifndef __AMDGPU_RLC_H__
  25 #define __AMDGPU_RLC_H__
  26
  27 #include "clearstate_defs.h"
  28
  29 struct amdgpu_rlc_funcs {
  30         bool (*is_rlc_enabled)(struct amdgpu_device *adev);
  31         void (*set_safe_mode)(struct amdgpu_device *adev);
  32         void (*unset_safe_mode)(struct amdgpu_device *adev);
  33         int  (*init)(struct amdgpu_device *adev);
  34         u32  (*get_csb_size)(struct amdgpu_device *adev);
  35         void (*get_csb_buffer)(struct amdgpu_device *adev, volatile u32 *buffer);
  36         int  (*get_cp_table_num)(struct amdgpu_device *adev);
  37         int  (*resume)(struct amdgpu_device *adev);
  38         void (*stop)(struct amdgpu_device *adev);
  39         void (*reset)(struct amdgpu_device *adev);
  40         void (*start)(struct amdgpu_device *adev);
  41 };
  42
  43 struct amdgpu_rlc {
  44         /* for power gating */
  45         struct amdgpu_bo        *save_restore_obj;
  46         uint64_t                save_restore_gpu_addr;
  47         volatile uint32_t       *sr_ptr;
  48         const u32               *reg_list;
  49         u32                     reg_list_size;
  50         /* for clear state */
  51         struct amdgpu_bo        *clear_state_obj;
  52         uint64_t                clear_state_gpu_addr;
  53         volatile uint32_t       *cs_ptr;
  54         const struct cs_section_def   *cs_data;
  55         u32                     clear_state_size;
  56         /* for cp tables */
  57         struct amdgpu_bo        *cp_table_obj;
  58         uint64_t                cp_table_gpu_addr;
  59         volatile uint32_t       *cp_table_ptr;
  60         u32                     cp_table_size;
  61
  62         /* safe mode for updating CG/PG state */
  63         bool in_safe_mode;
  64         const struct amdgpu_rlc_funcs *funcs;
  65
  66         /* for firmware data */
  67         u32 save_and_restore_offset;
  68         u32 clear_state_descriptor_offset;
  69         u32 avail_scratch_ram_locations;
  70         u32 reg_restore_list_size;
  71         u32 reg_list_format_start;
  72         u32 reg_list_format_separate_start;
  73         u32 starting_offsets_start;
  74         u32 reg_list_format_size_bytes;
  75         u32 reg_list_size_bytes;
  76         u32 reg_list_format_direct_reg_list_length;
  77         u32 save_restore_list_cntl_size_bytes;
  78         u32 save_restore_list_gpm_size_bytes;
  79         u32 save_restore_list_srm_size_bytes;
  80
  81         u32 *register_list_format;
  82         u32 *register_restore;
  83         u8 *save_restore_list_cntl;
  84         u8 *save_restore_list_gpm;
  85         u8 *save_restore_list_srm;
  86
  87         bool is_rlc_v2_1;
  88 };
  89
  90 void amdgpu_gfx_rlc_enter_safe_mode(struct amdgpu_device *adev);
  91 void amdgpu_gfx_rlc_exit_safe_mode(struct amdgpu_device *adev);
  92 int amdgpu_gfx_rlc_init_sr(struct amdgpu_device *adev, u32 dws);
  93 int amdgpu_gfx_rlc_init_csb(struct amdgpu_device *adev);
  94 int amdgpu_gfx_rlc_init_cpt(struct amdgpu_device *adev);
  95 void amdgpu_gfx_rlc_setup_cp_table(struct amdgpu_device *adev);
  96 void amdgpu_gfx_rlc_fini(struct amdgpu_device *adev);
  97
  98 #endif