drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #ifndef __AMDGPU_SDMA_H__
  25 #define __AMDGPU_SDMA_H__
  26
  27 /* max number of IP instances */
  28 #define AMDGPU_MAX_SDMA_INSTANCES               2
  29
  30 enum amdgpu_sdma_irq {
  31         AMDGPU_SDMA_IRQ_TRAP0 = 0,
  32         AMDGPU_SDMA_IRQ_TRAP1,
  33
  34         AMDGPU_SDMA_IRQ_LAST
  35 };
  36
  37 struct amdgpu_sdma_instance {
  38         /* SDMA firmware */
  39         const struct firmware   *fw;
  40         uint32_t                fw_version;
  41         uint32_t                feature_version;
  42
  43         struct amdgpu_ring      ring;
  44         struct amdgpu_ring      page;
  45         bool                    burst_nop;
  46 };
  47
  48 struct amdgpu_sdma {
  49         struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES];
  50         struct amdgpu_irq_src   trap_irq;
  51         struct amdgpu_irq_src   illegal_inst_irq;
  52         int                     num_instances;
  53         uint32_t                    srbm_soft_reset;
  54         bool                    has_page_queue;
  55 };
  56
  57 /*
  58  * Provided by hw blocks that can move/clear data.  e.g., gfx or sdma
  59  * But currently, we use sdma to move data.
  60  */
  61 struct amdgpu_buffer_funcs {
  62         /* maximum bytes in a single operation */
  63         uint32_t        copy_max_bytes;
  64
  65         /* number of dw to reserve per operation */
  66         unsigned        copy_num_dw;
  67
  68         /* used for buffer migration */
  69         void (*emit_copy_buffer)(struct amdgpu_ib *ib,
  70                                  /* src addr in bytes */
  71                                  uint64_t src_offset,
  72                                  /* dst addr in bytes */
  73                                  uint64_t dst_offset,
  74                                  /* number of byte to transfer */
  75                                  uint32_t byte_count);
  76
  77         /* maximum bytes in a single operation */
  78         uint32_t        fill_max_bytes;
  79
  80         /* number of dw to reserve per operation */
  81         unsigned        fill_num_dw;
  82
  83         /* used for buffer clearing */
  84         void (*emit_fill_buffer)(struct amdgpu_ib *ib,
  85                                  /* value to write to memory */
  86                                  uint32_t src_data,
  87                                  /* dst addr in bytes */
  88                                  uint64_t dst_offset,
  89                                  /* number of byte to fill */
  90                                  uint32_t byte_count);
  91 };
  92
  93 #define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib),  (s), (d), (b))
  94 #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
  95
  96 struct amdgpu_sdma_instance *
  97 amdgpu_sdma_get_instance_from_ring(struct amdgpu_ring *ring);
  98 int amdgpu_sdma_get_index_from_ring(struct amdgpu_ring *ring, uint32_t *index);
  99
 100 #endif