drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h

   1 /*
   2  * Copyright 2012 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #ifndef __AMDGPU_UCODE_H__
  24 #define __AMDGPU_UCODE_H__
  25
  26 struct common_firmware_header {
  27         uint32_t size_bytes; /* size of the entire header+image(s) in bytes */
  28         uint32_t header_size_bytes; /* size of just the header in bytes */
  29         uint16_t header_version_major; /* header version */
  30         uint16_t header_version_minor; /* header version */
  31         uint16_t ip_version_major; /* IP version */
  32         uint16_t ip_version_minor; /* IP version */
  33         uint32_t ucode_version;
  34         uint32_t ucode_size_bytes; /* size of ucode in bytes */
  35         uint32_t ucode_array_offset_bytes; /* payload offset from the start of the header */
  36         uint32_t crc32;  /* crc32 checksum of the payload */
  37 };
  38
  39 /* version_major=1, version_minor=0 */
  40 struct mc_firmware_header_v1_0 {
  41         struct common_firmware_header header;
  42         uint32_t io_debug_size_bytes; /* size of debug array in dwords */
  43         uint32_t io_debug_array_offset_bytes; /* payload offset from the start of the header */
  44 };
  45
  46 /* version_major=1, version_minor=0 */
  47 struct smc_firmware_header_v1_0 {
  48         struct common_firmware_header header;
  49         uint32_t ucode_start_addr;
  50 };
  51
  52 /* version_major=1, version_minor=0 */
  53 struct psp_firmware_header_v1_0 {
  54         struct common_firmware_header header;
  55         uint32_t ucode_feature_version;
  56         uint32_t sos_offset_bytes;
  57         uint32_t sos_size_bytes;
  58 };
  59
  60 /* version_major=1, version_minor=0 */
  61 struct ta_firmware_header_v1_0 {
  62         struct common_firmware_header header;
  63         uint32_t ta_xgmi_ucode_version;
  64         uint32_t ta_xgmi_offset_bytes;
  65         uint32_t ta_xgmi_size_bytes;
  66         uint32_t ta_ras_ucode_version;
  67         uint32_t ta_ras_offset_bytes;
  68         uint32_t ta_ras_size_bytes;
  69 };
  70
  71 /* version_major=1, version_minor=0 */
  72 struct gfx_firmware_header_v1_0 {
  73         struct common_firmware_header header;
  74         uint32_t ucode_feature_version;
  75         uint32_t jt_offset; /* jt location */
  76         uint32_t jt_size;  /* size of jt */
  77 };
  78
  79 /* version_major=1, version_minor=0 */
  80 struct rlc_firmware_header_v1_0 {
  81         struct common_firmware_header header;
  82         uint32_t ucode_feature_version;
  83         uint32_t save_and_restore_offset;
  84         uint32_t clear_state_descriptor_offset;
  85         uint32_t avail_scratch_ram_locations;
  86         uint32_t master_pkt_description_offset;
  87 };
  88
  89 /* version_major=2, version_minor=0 */
  90 struct rlc_firmware_header_v2_0 {
  91         struct common_firmware_header header;
  92         uint32_t ucode_feature_version;
  93         uint32_t jt_offset; /* jt location */
  94         uint32_t jt_size;  /* size of jt */
  95         uint32_t save_and_restore_offset;
  96         uint32_t clear_state_descriptor_offset;
  97         uint32_t avail_scratch_ram_locations;
  98         uint32_t reg_restore_list_size;
  99         uint32_t reg_list_format_start;
 100         uint32_t reg_list_format_separate_start;
 101         uint32_t starting_offsets_start;
 102         uint32_t reg_list_format_size_bytes; /* size of reg list format array in bytes */
 103         uint32_t reg_list_format_array_offset_bytes; /* payload offset from the start of the header */
 104         uint32_t reg_list_size_bytes; /* size of reg list array in bytes */
 105         uint32_t reg_list_array_offset_bytes; /* payload offset from the start of the header */
 106         uint32_t reg_list_format_separate_size_bytes; /* size of reg list format array in bytes */
 107         uint32_t reg_list_format_separate_array_offset_bytes; /* payload offset from the start of the header */
 108         uint32_t reg_list_separate_size_bytes; /* size of reg list array in bytes */
 109         uint32_t reg_list_separate_array_offset_bytes; /* payload offset from the start of the header */
 110 };
 111
 112 /* version_major=2, version_minor=1 */
 113 struct rlc_firmware_header_v2_1 {
 114         struct rlc_firmware_header_v2_0 v2_0;
 115         uint32_t reg_list_format_direct_reg_list_length; /* length of direct reg list format array */
 116         uint32_t save_restore_list_cntl_ucode_ver;
 117         uint32_t save_restore_list_cntl_feature_ver;
 118         uint32_t save_restore_list_cntl_size_bytes;
 119         uint32_t save_restore_list_cntl_offset_bytes;
 120         uint32_t save_restore_list_gpm_ucode_ver;
 121         uint32_t save_restore_list_gpm_feature_ver;
 122         uint32_t save_restore_list_gpm_size_bytes;
 123         uint32_t save_restore_list_gpm_offset_bytes;
 124         uint32_t save_restore_list_srm_ucode_ver;
 125         uint32_t save_restore_list_srm_feature_ver;
 126         uint32_t save_restore_list_srm_size_bytes;
 127         uint32_t save_restore_list_srm_offset_bytes;
 128 };
 129
 130 /* version_major=1, version_minor=0 */
 131 struct sdma_firmware_header_v1_0 {
 132         struct common_firmware_header header;
 133         uint32_t ucode_feature_version;
 134         uint32_t ucode_change_version;
 135         uint32_t jt_offset; /* jt location */
 136         uint32_t jt_size; /* size of jt */
 137 };
 138
 139 /* version_major=1, version_minor=1 */
 140 struct sdma_firmware_header_v1_1 {
 141         struct sdma_firmware_header_v1_0 v1_0;
 142         uint32_t digest_size;
 143 };
 144
 145 /* gpu info payload */
 146 struct gpu_info_firmware_v1_0 {
 147         uint32_t gc_num_se;
 148         uint32_t gc_num_cu_per_sh;
 149         uint32_t gc_num_sh_per_se;
 150         uint32_t gc_num_rb_per_se;
 151         uint32_t gc_num_tccs;
 152         uint32_t gc_num_gprs;
 153         uint32_t gc_num_max_gs_thds;
 154         uint32_t gc_gs_table_depth;
 155         uint32_t gc_gsprim_buff_depth;
 156         uint32_t gc_parameter_cache_depth;
 157         uint32_t gc_double_offchip_lds_buffer;
 158         uint32_t gc_wave_size;
 159         uint32_t gc_max_waves_per_simd;
 160         uint32_t gc_max_scratch_slots_per_cu;
 161         uint32_t gc_lds_size;
 162 };
 163
 164 /* version_major=1, version_minor=0 */
 165 struct gpu_info_firmware_header_v1_0 {
 166         struct common_firmware_header header;
 167         uint16_t version_major; /* version */
 168         uint16_t version_minor; /* version */
 169 };
 170
 171 /* version_major=1, version_minor=0 */
 172 struct dmcu_firmware_header_v1_0 {
 173         struct common_firmware_header header;
 174         uint32_t intv_offset_bytes; /* interrupt vectors offset from end of header, in bytes */
 175         uint32_t intv_size_bytes;  /* size of interrupt vectors, in bytes */
 176 };
 177
 178 /* header is fixed size */
 179 union amdgpu_firmware_header {
 180         struct common_firmware_header common;
 181         struct mc_firmware_header_v1_0 mc;
 182         struct smc_firmware_header_v1_0 smc;
 183         struct psp_firmware_header_v1_0 psp;
 184         struct ta_firmware_header_v1_0 ta;
 185         struct gfx_firmware_header_v1_0 gfx;
 186         struct rlc_firmware_header_v1_0 rlc;
 187         struct rlc_firmware_header_v2_0 rlc_v2_0;
 188         struct rlc_firmware_header_v2_1 rlc_v2_1;
 189         struct sdma_firmware_header_v1_0 sdma;
 190         struct sdma_firmware_header_v1_1 sdma_v1_1;
 191         struct gpu_info_firmware_header_v1_0 gpu_info;
 192         struct dmcu_firmware_header_v1_0 dmcu;
 193         uint8_t raw[0x100];
 194 };
 195
 196 /*
 197  * fw loading support
 198  */
 199 enum AMDGPU_UCODE_ID {
 200         AMDGPU_UCODE_ID_SDMA0 = 0,
 201         AMDGPU_UCODE_ID_SDMA1,
 202         AMDGPU_UCODE_ID_CP_CE,
 203         AMDGPU_UCODE_ID_CP_PFP,
 204         AMDGPU_UCODE_ID_CP_ME,
 205         AMDGPU_UCODE_ID_CP_MEC1,
 206         AMDGPU_UCODE_ID_CP_MEC1_JT,
 207         AMDGPU_UCODE_ID_CP_MEC2,
 208         AMDGPU_UCODE_ID_CP_MEC2_JT,
 209         AMDGPU_UCODE_ID_RLC_G,
 210         AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL,
 211         AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM,
 212         AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM,
 213         AMDGPU_UCODE_ID_STORAGE,
 214         AMDGPU_UCODE_ID_SMC,
 215         AMDGPU_UCODE_ID_UVD,
 216         AMDGPU_UCODE_ID_UVD1,
 217         AMDGPU_UCODE_ID_VCE,
 218         AMDGPU_UCODE_ID_VCN,
 219         AMDGPU_UCODE_ID_DMCU_ERAM,
 220         AMDGPU_UCODE_ID_DMCU_INTV,
 221         AMDGPU_UCODE_ID_MAXIMUM,
 222 };
 223
 224 /* engine firmware status */
 225 enum AMDGPU_UCODE_STATUS {
 226         AMDGPU_UCODE_STATUS_INVALID,
 227         AMDGPU_UCODE_STATUS_NOT_LOADED,
 228         AMDGPU_UCODE_STATUS_LOADED,
 229 };
 230
 231 enum amdgpu_firmware_load_type {
 232         AMDGPU_FW_LOAD_DIRECT = 0,
 233         AMDGPU_FW_LOAD_SMU,
 234         AMDGPU_FW_LOAD_PSP,
 235 };
 236
 237 /* conform to smu_ucode_xfer_cz.h */
 238 #define AMDGPU_SDMA0_UCODE_LOADED       0x00000001
 239 #define AMDGPU_SDMA1_UCODE_LOADED       0x00000002
 240 #define AMDGPU_CPCE_UCODE_LOADED        0x00000004
 241 #define AMDGPU_CPPFP_UCODE_LOADED       0x00000008
 242 #define AMDGPU_CPME_UCODE_LOADED        0x00000010
 243 #define AMDGPU_CPMEC1_UCODE_LOADED      0x00000020
 244 #define AMDGPU_CPMEC2_UCODE_LOADED      0x00000040
 245 #define AMDGPU_CPRLC_UCODE_LOADED       0x00000100
 246
 247 /* amdgpu firmware info */
 248 struct amdgpu_firmware_info {
 249         /* ucode ID */
 250         enum AMDGPU_UCODE_ID ucode_id;
 251         /* request_firmware */
 252         const struct firmware *fw;
 253         /* starting mc address */
 254         uint64_t mc_addr;
 255         /* kernel linear address */
 256         void *kaddr;
 257         /* ucode_size_bytes */
 258         uint32_t ucode_size;
 259         /* starting tmr mc address */
 260         uint32_t tmr_mc_addr_lo;
 261         uint32_t tmr_mc_addr_hi;
 262 };
 263
 264 struct amdgpu_firmware {
 265         struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM];
 266         enum amdgpu_firmware_load_type load_type;
 267         struct amdgpu_bo *fw_buf;
 268         unsigned int fw_size;
 269         unsigned int max_ucodes;
 270         /* firmwares are loaded by psp instead of smu from vega10 */
 271         const struct amdgpu_psp_funcs *funcs;
 272         struct amdgpu_bo *rbuf;
 273         struct mutex mutex;
 274
 275         /* gpu info firmware data pointer */
 276         const struct firmware *gpu_info_fw;
 277
 278         void *fw_buf_ptr;
 279         uint64_t fw_buf_mc;
 280 };
 281
 282 void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr);
 283 void amdgpu_ucode_print_smc_hdr(const struct common_firmware_header *hdr);
 284 void amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header *hdr);
 285 void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr);
 286 void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr);
 287 void amdgpu_ucode_print_gpu_info_hdr(const struct common_firmware_header *hdr);
 288 int amdgpu_ucode_validate(const struct firmware *fw);
 289 bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr,
 290                                 uint16_t hdr_major, uint16_t hdr_minor);
 291
 292 int amdgpu_ucode_init_bo(struct amdgpu_device *adev);
 293 int amdgpu_ucode_create_bo(struct amdgpu_device *adev);
 294 void amdgpu_ucode_free_bo(struct amdgpu_device *adev);
 295
 296 enum amdgpu_firmware_load_type
 297 amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type);
 298
 299 #endif