drivers/gpu/drm/amd/amdgpu/cz_ih.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <drm/drmP.h>
  24 #include "amdgpu.h"
  25 #include "amdgpu_ih.h"
  26 #include "vid.h"
  27
  28 #include "oss/oss_3_0_1_d.h"
  29 #include "oss/oss_3_0_1_sh_mask.h"
  30
  31 #include "bif/bif_5_1_d.h"
  32 #include "bif/bif_5_1_sh_mask.h"
  33
  34 /*
  35  * Interrupts
  36  * Starting with r6xx, interrupts are handled via a ring buffer.
  37  * Ring buffers are areas of GPU accessible memory that the GPU
  38  * writes interrupt vectors into and the host reads vectors out of.
  39  * There is a rptr (read pointer) that determines where the
  40  * host is currently reading, and a wptr (write pointer)
  41  * which determines where the GPU has written.  When the
  42  * pointers are equal, the ring is idle.  When the GPU
  43  * writes vectors to the ring buffer, it increments the
  44  * wptr.  When there is an interrupt, the host then starts
  45  * fetching commands and processing them until the pointers are
  46  * equal again at which point it updates the rptr.
  47  */
  48
  49 static void cz_ih_set_interrupt_funcs(struct amdgpu_device *adev);
  50
  51 /**
  52  * cz_ih_enable_interrupts - Enable the interrupt ring buffer
  53  *
  54  * @adev: amdgpu_device pointer
  55  *
  56  * Enable the interrupt ring buffer (VI).
  57  */
  58 static void cz_ih_enable_interrupts(struct amdgpu_device *adev)
  59 {
  60         u32 ih_cntl = RREG32(mmIH_CNTL);
  61         u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);
  62
  63         ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 1);
  64         ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1);
  65         WREG32(mmIH_CNTL, ih_cntl);
  66         WREG32(mmIH_RB_CNTL, ih_rb_cntl);
  67         adev->irq.ih.enabled = true;
  68 }
  69
  70 /**
  71  * cz_ih_disable_interrupts - Disable the interrupt ring buffer
  72  *
  73  * @adev: amdgpu_device pointer
  74  *
  75  * Disable the interrupt ring buffer (VI).
  76  */
  77 static void cz_ih_disable_interrupts(struct amdgpu_device *adev)
  78 {
  79         u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);
  80         u32 ih_cntl = RREG32(mmIH_CNTL);
  81
  82         ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0);
  83         ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 0);
  84         WREG32(mmIH_RB_CNTL, ih_rb_cntl);
  85         WREG32(mmIH_CNTL, ih_cntl);
  86         /* set rptr, wptr to 0 */
  87         WREG32(mmIH_RB_RPTR, 0);
  88         WREG32(mmIH_RB_WPTR, 0);
  89         adev->irq.ih.enabled = false;
  90         adev->irq.ih.rptr = 0;
  91 }
  92
  93 /**
  94  * cz_ih_irq_init - init and enable the interrupt ring
  95  *
  96  * @adev: amdgpu_device pointer
  97  *
  98  * Allocate a ring buffer for the interrupt controller,
  99  * enable the RLC, disable interrupts, enable the IH
 100  * ring buffer and enable it (VI).
 101  * Called at device load and reume.
 102  * Returns 0 for success, errors for failure.
 103  */
 104 static int cz_ih_irq_init(struct amdgpu_device *adev)
 105 {
 106         struct amdgpu_ih_ring *ih = &adev->irq.ih;
 107         u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
 108         int rb_bufsz;
 109
 110         /* disable irqs */
 111         cz_ih_disable_interrupts(adev);
 112
 113         /* setup interrupt control */
 114         WREG32(mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8);
 115         interrupt_cntl = RREG32(mmINTERRUPT_CNTL);
 116         /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
 117          * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
 118          */
 119         interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);
 120         /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
 121         interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);
 122         WREG32(mmINTERRUPT_CNTL, interrupt_cntl);
 123
 124         /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/
 125         WREG32(mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8);
 126
 127         rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4);
 128         ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 1);
 129         ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
 130         ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);
 131
 132         /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register value is written to memory */
 133         ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1);
 134
 135         /* set the writeback address whether it's enabled or not */
 136         WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr));
 137         WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF);
 138
 139         WREG32(mmIH_RB_CNTL, ih_rb_cntl);
 140
 141         /* set rptr, wptr to 0 */
 142         WREG32(mmIH_RB_RPTR, 0);
 143         WREG32(mmIH_RB_WPTR, 0);
 144
 145         /* Default settings for IH_CNTL (disabled at first) */
 146         ih_cntl = RREG32(mmIH_CNTL);
 147         ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, MC_VMID, 0);
 148
 149         if (adev->irq.msi_enabled)
 150                 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, RPTR_REARM, 1);
 151         WREG32(mmIH_CNTL, ih_cntl);
 152
 153         pci_set_master(adev->pdev);
 154
 155         /* enable interrupts */
 156         cz_ih_enable_interrupts(adev);
 157
 158         return 0;
 159 }
 160
 161 /**
 162  * cz_ih_irq_disable - disable interrupts
 163  *
 164  * @adev: amdgpu_device pointer
 165  *
 166  * Disable interrupts on the hw (VI).
 167  */
 168 static void cz_ih_irq_disable(struct amdgpu_device *adev)
 169 {
 170         cz_ih_disable_interrupts(adev);
 171
 172         /* Wait and acknowledge irq */
 173         mdelay(1);
 174 }
 175
 176 /**
 177  * cz_ih_get_wptr - get the IH ring buffer wptr
 178  *
 179  * @adev: amdgpu_device pointer
 180  *
 181  * Get the IH ring buffer wptr from either the register
 182  * or the writeback memory buffer (VI).  Also check for
 183  * ring buffer overflow and deal with it.
 184  * Used by cz_irq_process(VI).
 185  * Returns the value of the wptr.
 186  */
 187 static u32 cz_ih_get_wptr(struct amdgpu_device *adev,
 188                           struct amdgpu_ih_ring *ih)
 189 {
 190         u32 wptr, tmp;
 191
 192         wptr = le32_to_cpu(*ih->wptr_cpu);
 193
 194         if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) {
 195                 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
 196                 /* When a ring buffer overflow happen start parsing interrupt
 197                  * from the last not overwritten vector (wptr + 16). Hopefully
 198                  * this should allow us to catchup.
 199                  */
 200                 dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
 201                         wptr, ih->rptr, (wptr + 16) & ih->ptr_mask);
 202                 ih->rptr = (wptr + 16) & ih->ptr_mask;
 203                 tmp = RREG32(mmIH_RB_CNTL);
 204                 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
 205                 WREG32(mmIH_RB_CNTL, tmp);
 206         }
 207         return (wptr & ih->ptr_mask);
 208 }
 209
 210 /**
 211  * cz_ih_decode_iv - decode an interrupt vector
 212  *
 213  * @adev: amdgpu_device pointer
 214  *
 215  * Decodes the interrupt vector at the current rptr
 216  * position and also advance the position.
 217  */
 218 static void cz_ih_decode_iv(struct amdgpu_device *adev,
 219                             struct amdgpu_ih_ring *ih,
 220                             struct amdgpu_iv_entry *entry)
 221 {
 222         /* wptr/rptr are in bytes! */
 223         u32 ring_index = ih->rptr >> 2;
 224         uint32_t dw[4];
 225
 226         dw[0] = le32_to_cpu(ih->ring[ring_index + 0]);
 227         dw[1] = le32_to_cpu(ih->ring[ring_index + 1]);
 228         dw[2] = le32_to_cpu(ih->ring[ring_index + 2]);
 229         dw[3] = le32_to_cpu(ih->ring[ring_index + 3]);
 230
 231         entry->client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
 232         entry->src_id = dw[0] & 0xff;
 233         entry->src_data[0] = dw[1] & 0xfffffff;
 234         entry->ring_id = dw[2] & 0xff;
 235         entry->vmid = (dw[2] >> 8) & 0xff;
 236         entry->pasid = (dw[2] >> 16) & 0xffff;
 237
 238         /* wptr/rptr are in bytes! */
 239         ih->rptr += 16;
 240 }
 241
 242 /**
 243  * cz_ih_set_rptr - set the IH ring buffer rptr
 244  *
 245  * @adev: amdgpu_device pointer
 246  *
 247  * Set the IH ring buffer rptr.
 248  */
 249 static void cz_ih_set_rptr(struct amdgpu_device *adev,
 250                            struct amdgpu_ih_ring *ih)
 251 {
 252         WREG32(mmIH_RB_RPTR, ih->rptr);
 253 }
 254
 255 static int cz_ih_early_init(void *handle)
 256 {
 257         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 258         int ret;
 259
 260         ret = amdgpu_irq_add_domain(adev);
 261         if (ret)
 262                 return ret;
 263
 264         cz_ih_set_interrupt_funcs(adev);
 265
 266         return 0;
 267 }
 268
 269 static int cz_ih_sw_init(void *handle)
 270 {
 271         int r;
 272         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 273
 274         r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 64 * 1024, false);
 275         if (r)
 276                 return r;
 277
 278         r = amdgpu_irq_init(adev);
 279
 280         return r;
 281 }
 282
 283 static int cz_ih_sw_fini(void *handle)
 284 {
 285         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 286
 287         amdgpu_irq_fini(adev);
 288         amdgpu_ih_ring_fini(adev, &adev->irq.ih);
 289         amdgpu_irq_remove_domain(adev);
 290
 291         return 0;
 292 }
 293
 294 static int cz_ih_hw_init(void *handle)
 295 {
 296         int r;
 297         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 298
 299         r = cz_ih_irq_init(adev);
 300         if (r)
 301                 return r;
 302
 303         return 0;
 304 }
 305
 306 static int cz_ih_hw_fini(void *handle)
 307 {
 308         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 309
 310         cz_ih_irq_disable(adev);
 311
 312         return 0;
 313 }
 314
 315 static int cz_ih_suspend(void *handle)
 316 {
 317         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 318
 319         return cz_ih_hw_fini(adev);
 320 }
 321
 322 static int cz_ih_resume(void *handle)
 323 {
 324         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 325
 326         return cz_ih_hw_init(adev);
 327 }
 328
 329 static bool cz_ih_is_idle(void *handle)
 330 {
 331         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 332         u32 tmp = RREG32(mmSRBM_STATUS);
 333
 334         if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
 335                 return false;
 336
 337         return true;
 338 }
 339
 340 static int cz_ih_wait_for_idle(void *handle)
 341 {
 342         unsigned i;
 343         u32 tmp;
 344         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 345
 346         for (i = 0; i < adev->usec_timeout; i++) {
 347                 /* read MC_STATUS */
 348                 tmp = RREG32(mmSRBM_STATUS);
 349                 if (!REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
 350                         return 0;
 351                 udelay(1);
 352         }
 353         return -ETIMEDOUT;
 354 }
 355
 356 static int cz_ih_soft_reset(void *handle)
 357 {
 358         u32 srbm_soft_reset = 0;
 359         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 360         u32 tmp = RREG32(mmSRBM_STATUS);
 361
 362         if (tmp & SRBM_STATUS__IH_BUSY_MASK)
 363                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET,
 364                                                 SOFT_RESET_IH, 1);
 365
 366         if (srbm_soft_reset) {
 367                 tmp = RREG32(mmSRBM_SOFT_RESET);
 368                 tmp |= srbm_soft_reset;
 369                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
 370                 WREG32(mmSRBM_SOFT_RESET, tmp);
 371                 tmp = RREG32(mmSRBM_SOFT_RESET);
 372
 373                 udelay(50);
 374
 375                 tmp &= ~srbm_soft_reset;
 376                 WREG32(mmSRBM_SOFT_RESET, tmp);
 377                 tmp = RREG32(mmSRBM_SOFT_RESET);
 378
 379                 /* Wait a little for things to settle down */
 380                 udelay(50);
 381         }
 382
 383         return 0;
 384 }
 385
 386 static int cz_ih_set_clockgating_state(void *handle,
 387                                           enum amd_clockgating_state state)
 388 {
 389         // TODO
 390         return 0;
 391 }
 392
 393 static int cz_ih_set_powergating_state(void *handle,
 394                                           enum amd_powergating_state state)
 395 {
 396         // TODO
 397         return 0;
 398 }
 399
 400 static const struct amd_ip_funcs cz_ih_ip_funcs = {
 401         .name = "cz_ih",
 402         .early_init = cz_ih_early_init,
 403         .late_init = NULL,
 404         .sw_init = cz_ih_sw_init,
 405         .sw_fini = cz_ih_sw_fini,
 406         .hw_init = cz_ih_hw_init,
 407         .hw_fini = cz_ih_hw_fini,
 408         .suspend = cz_ih_suspend,
 409         .resume = cz_ih_resume,
 410         .is_idle = cz_ih_is_idle,
 411         .wait_for_idle = cz_ih_wait_for_idle,
 412         .soft_reset = cz_ih_soft_reset,
 413         .set_clockgating_state = cz_ih_set_clockgating_state,
 414         .set_powergating_state = cz_ih_set_powergating_state,
 415 };
 416
 417 static const struct amdgpu_ih_funcs cz_ih_funcs = {
 418         .get_wptr = cz_ih_get_wptr,
 419         .decode_iv = cz_ih_decode_iv,
 420         .set_rptr = cz_ih_set_rptr
 421 };
 422
 423 static void cz_ih_set_interrupt_funcs(struct amdgpu_device *adev)
 424 {
 425         adev->irq.ih_funcs = &cz_ih_funcs;
 426 }
 427
 428 const struct amdgpu_ip_block_version cz_ih_ip_block =
 429 {
 430         .type = AMD_IP_BLOCK_TYPE_IH,
 431         .major = 3,
 432         .minor = 0,
 433         .rev = 0,
 434         .funcs = &cz_ih_ip_funcs,
 435 };