2 * Copyright 2013 Advanced Micro Devices, Inc.
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5 * copy of this software and associated documentation files (the "Software"),
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #define SMU__NUM_SCLK_DPM_STATE 8
27 #define SMU__NUM_MCLK_DPM_LEVELS 4
28 #define SMU__NUM_LCLK_DPM_LEVELS 8
29 #define SMU__NUM_PCIE_DPM_LEVELS 0 /* ??? */
30 #include "smu7_fusion.h"
33 #define SUMO_MAX_HARDWARE_POWERLEVELS 5
35 #define SUMO_MAX_NUMBER_VOLTAGES 4
37 struct sumo_vid_mapping_entry
{
42 struct sumo_vid_mapping_table
{
44 struct sumo_vid_mapping_entry entries
[SUMO_MAX_NUMBER_VOLTAGES
];
47 struct sumo_sclk_voltage_mapping_entry
{
53 struct sumo_sclk_voltage_mapping_table
{
54 u32 num_max_dpm_entries
;
55 struct sumo_sclk_voltage_mapping_entry entries
[SUMO_MAX_HARDWARE_POWERLEVELS
];
58 #define TRINITY_AT_DFLT 30
60 #define KV_NUM_NBPSTATES 4
62 enum kv_pt_config_reg_type
{
65 KV_CONFIGREG_DIDT_IND
,
70 struct kv_pt_config_reg
{
75 enum kv_pt_config_reg_type type
;
78 struct kv_lcac_config_values
{
84 struct kv_lcac_config_reg
{
108 struct kv_pl levels
[SUMO_MAX_HARDWARE_POWERLEVELS
];
110 bool need_dfs_bypass
;
120 u32 dentist_vco_freq
;
122 u32 nbp_memory_clock
[KV_NUM_NBPSTATES
];
123 u32 nbp_n_clock
[KV_NUM_NBPSTATES
];
124 u16 bootup_nb_voltage_index
;
127 struct sumo_sclk_voltage_mapping_table sclk_voltage_mapping_table
;
128 struct sumo_vid_mapping_table vid_mapping_table
;
129 u32 uma_channel_number
;
132 struct kv_power_info
{
133 u32 at
[SUMO_MAX_HARDWARE_POWERLEVELS
];
135 struct kv_sys_info sys_info
;
136 struct kv_pl boot_pl
;
137 bool enable_nb_ps_policy
;
138 bool disable_nb_ps3_in_battery
;
151 u8 graphics_dpm_level_count
;
157 SMU7_Fusion_GraphicsLevel graphics_level
[SMU__NUM_SCLK_DPM_STATE
];
158 SMU7_Fusion_ACPILevel acpi_level
;
159 SMU7_Fusion_UvdLevel uvd_level
[SMU7_MAX_LEVELS_UVD
];
160 SMU7_Fusion_ExtClkLevel vce_level
[SMU7_MAX_LEVELS_VCE
];
161 SMU7_Fusion_ExtClkLevel acp_level
[SMU7_MAX_LEVELS_ACP
];
162 SMU7_Fusion_ExtClkLevel samu_level
[SMU7_MAX_LEVELS_SAMU
];
171 u8 graphics_boot_level
;
172 u8 graphics_interval
;
173 u8 graphics_therm_throttle_enable
;
174 u8 graphics_voltage_change_enable
;
175 u8 graphics_clk_slow_enable
;
176 u8 graphics_clk_slow_divider
;
178 u32 low_sclk_interrupt_t
;
179 bool uvd_power_gated
;
180 bool vce_power_gated
;
181 bool acp_power_gated
;
182 bool samu_power_gated
;
187 bool enable_auto_thermal_throttling
;
191 bool caps_power_containment
;
192 bool caps_sq_ramping
;
193 bool caps_db_ramping
;
194 bool caps_td_ramping
;
195 bool caps_tcp_ramping
;
196 bool caps_sclk_throttle_low_notification
;
203 bool caps_stable_p_state
;
204 bool caps_enable_dfs_bypass
;
206 struct amdgpu_ps current_rps
;
207 struct kv_ps current_ps
;
208 struct amdgpu_ps requested_rps
;
209 struct kv_ps requested_ps
;
212 /* XXX are these ok? */
213 #define KV_TEMP_RANGE_MIN (90 * 1000)
214 #define KV_TEMP_RANGE_MAX (120 * 1000)
217 int amdgpu_kv_notify_message_to_smu(struct amdgpu_device
*adev
, u32 id
);
218 int amdgpu_kv_dpm_get_enable_mask(struct amdgpu_device
*adev
, u32
*enable_mask
);
219 int amdgpu_kv_send_msg_to_smc_with_parameter(struct amdgpu_device
*adev
,
220 PPSMC_Msg msg
, u32 parameter
);
221 int amdgpu_kv_read_smc_sram_dword(struct amdgpu_device
*adev
, u32 smc_address
,
222 u32
*value
, u32 limit
);
223 int amdgpu_kv_smc_dpm_enable(struct amdgpu_device
*adev
, bool enable
);
224 int amdgpu_kv_smc_bapm_enable(struct amdgpu_device
*adev
, bool enable
);
225 int amdgpu_kv_copy_bytes_to_smc(struct amdgpu_device
*adev
,
226 u32 smc_start_address
,
227 const u8
*src
, u32 byte_count
, u32 limit
);