drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include "amdgpu.h"
  24 #include "amdgpu_atombios.h"
  25 #include "nbio_v6_1.h"
  26
  27 #include "nbio/nbio_6_1_default.h"
  28 #include "nbio/nbio_6_1_offset.h"
  29 #include "nbio/nbio_6_1_sh_mask.h"
  30 #include "nbio/nbio_6_1_smn.h"
  31 #include "vega10_enum.h"
  32
  33 static u32 nbio_v6_1_get_rev_id(struct amdgpu_device *adev)
  34 {
  35         u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
  36
  37         tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
  38         tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
  39
  40         return tmp;
  41 }
  42
  43 static void nbio_v6_1_mc_access_enable(struct amdgpu_device *adev, bool enable)
  44 {
  45         if (enable)
  46                 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN,
  47                              BIF_FB_EN__FB_READ_EN_MASK |
  48                              BIF_FB_EN__FB_WRITE_EN_MASK);
  49         else
  50                 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0);
  51 }
  52
  53 static void nbio_v6_1_hdp_flush(struct amdgpu_device *adev,
  54                                 struct amdgpu_ring *ring)
  55 {
  56         if (!ring || !ring->funcs->emit_wreg)
  57                 WREG32_SOC15_NO_KIQ(NBIO, 0,
  58                                     mmBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL,
  59                                     0);
  60         else
  61                 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
  62                         NBIO, 0, mmBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL), 0);
  63 }
  64
  65 static u32 nbio_v6_1_get_memsize(struct amdgpu_device *adev)
  66 {
  67         return RREG32_SOC15(NBIO, 0, mmRCC_PF_0_0_RCC_CONFIG_MEMSIZE);
  68 }
  69
  70 static void nbio_v6_1_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
  71                         bool use_doorbell, int doorbell_index, int doorbell_size)
  72 {
  73         u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) :
  74                         SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE);
  75
  76         u32 doorbell_range = RREG32(reg);
  77
  78         if (use_doorbell) {
  79                 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index);
  80                 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, doorbell_size);
  81         } else
  82                 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0);
  83
  84         WREG32(reg, doorbell_range);
  85
  86 }
  87
  88 static void nbio_v6_1_enable_doorbell_aperture(struct amdgpu_device *adev,
  89                                                bool enable)
  90 {
  91         WREG32_FIELD15(NBIO, 0, RCC_PF_0_0_RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, enable ? 1 : 0);
  92 }
  93
  94 static void nbio_v6_1_enable_doorbell_selfring_aperture(struct amdgpu_device *adev,
  95                                                         bool enable)
  96 {
  97         u32 tmp = 0;
  98
  99         if (enable) {
 100                 tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_EN, 1) |
 101                       REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_MODE, 1) |
 102                       REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_SIZE, 0);
 103
 104                 WREG32_SOC15(NBIO, 0, mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW,
 105                              lower_32_bits(adev->doorbell.base));
 106                 WREG32_SOC15(NBIO, 0, mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH,
 107                              upper_32_bits(adev->doorbell.base));
 108         }
 109
 110         WREG32_SOC15(NBIO, 0, mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, tmp);
 111 }
 112
 113
 114 static void nbio_v6_1_ih_doorbell_range(struct amdgpu_device *adev,
 115                                         bool use_doorbell, int doorbell_index)
 116 {
 117         u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0 , mmBIF_IH_DOORBELL_RANGE);
 118
 119         if (use_doorbell) {
 120                 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index);
 121                 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 2);
 122         } else
 123                 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 0);
 124
 125         WREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE, ih_doorbell_range);
 126 }
 127
 128 static void nbio_v6_1_ih_control(struct amdgpu_device *adev)
 129 {
 130         u32 interrupt_cntl;
 131
 132         /* setup interrupt control */
 133         WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8);
 134         interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL);
 135         /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
 136          * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
 137          */
 138         interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);
 139         /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
 140         interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);
 141         WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl);
 142 }
 143
 144 static void nbio_v6_1_update_medium_grain_clock_gating(struct amdgpu_device *adev,
 145                                                        bool enable)
 146 {
 147         uint32_t def, data;
 148
 149         def = data = RREG32_PCIE(smnCPM_CONTROL);
 150         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG)) {
 151                 data |= (CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK |
 152                          CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK |
 153                          CPM_CONTROL__TXCLK_PERM_GATE_ENABLE_MASK |
 154                          CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK |
 155                          CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK |
 156                          CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK |
 157                          CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK);
 158         } else {
 159                 data &= ~(CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK |
 160                           CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK |
 161                           CPM_CONTROL__TXCLK_PERM_GATE_ENABLE_MASK |
 162                           CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK |
 163                           CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK |
 164                           CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK |
 165                           CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK);
 166         }
 167
 168         if (def != data)
 169                 WREG32_PCIE(smnCPM_CONTROL, data);
 170 }
 171
 172 static void nbio_v6_1_update_medium_grain_light_sleep(struct amdgpu_device *adev,
 173                                                       bool enable)
 174 {
 175         uint32_t def, data;
 176
 177         def = data = RREG32_PCIE(smnPCIE_CNTL2);
 178         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) {
 179                 data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
 180                          PCIE_CNTL2__MST_MEM_LS_EN_MASK |
 181                          PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
 182         } else {
 183                 data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
 184                           PCIE_CNTL2__MST_MEM_LS_EN_MASK |
 185                           PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
 186         }
 187
 188         if (def != data)
 189                 WREG32_PCIE(smnPCIE_CNTL2, data);
 190 }
 191
 192 static void nbio_v6_1_get_clockgating_state(struct amdgpu_device *adev,
 193                                             u32 *flags)
 194 {
 195         int data;
 196
 197         /* AMD_CG_SUPPORT_BIF_MGCG */
 198         data = RREG32_PCIE(smnCPM_CONTROL);
 199         if (data & CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK)
 200                 *flags |= AMD_CG_SUPPORT_BIF_MGCG;
 201
 202         /* AMD_CG_SUPPORT_BIF_LS */
 203         data = RREG32_PCIE(smnPCIE_CNTL2);
 204         if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK)
 205                 *flags |= AMD_CG_SUPPORT_BIF_LS;
 206 }
 207
 208 static u32 nbio_v6_1_get_hdp_flush_req_offset(struct amdgpu_device *adev)
 209 {
 210         return SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_GPU_HDP_FLUSH_REQ);
 211 }
 212
 213 static u32 nbio_v6_1_get_hdp_flush_done_offset(struct amdgpu_device *adev)
 214 {
 215         return SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_GPU_HDP_FLUSH_DONE);
 216 }
 217
 218 static u32 nbio_v6_1_get_pcie_index_offset(struct amdgpu_device *adev)
 219 {
 220         return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2);
 221 }
 222
 223 static u32 nbio_v6_1_get_pcie_data_offset(struct amdgpu_device *adev)
 224 {
 225         return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2);
 226 }
 227
 228 static const struct nbio_hdp_flush_reg nbio_v6_1_hdp_flush_reg = {
 229         .ref_and_mask_cp0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK,
 230         .ref_and_mask_cp1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK,
 231         .ref_and_mask_cp2 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK,
 232         .ref_and_mask_cp3 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3_MASK,
 233         .ref_and_mask_cp4 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4_MASK,
 234         .ref_and_mask_cp5 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5_MASK,
 235         .ref_and_mask_cp6 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6_MASK,
 236         .ref_and_mask_cp7 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7_MASK,
 237         .ref_and_mask_cp8 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8_MASK,
 238         .ref_and_mask_cp9 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9_MASK,
 239         .ref_and_mask_sdma0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK,
 240         .ref_and_mask_sdma1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK
 241 };
 242
 243 static void nbio_v6_1_detect_hw_virt(struct amdgpu_device *adev)
 244 {
 245         uint32_t reg;
 246
 247         reg = RREG32_SOC15(NBIO, 0, mmRCC_PF_0_0_RCC_IOV_FUNC_IDENTIFIER);
 248         if (reg & 1)
 249                 adev->virt.caps |= AMDGPU_SRIOV_CAPS_IS_VF;
 250
 251         if (reg & 0x80000000)
 252                 adev->virt.caps |= AMDGPU_SRIOV_CAPS_ENABLE_IOV;
 253
 254         if (!reg) {
 255                 if (is_virtual_machine())       /* passthrough mode exclus sriov mod */
 256                         adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE;
 257         }
 258 }
 259
 260 static void nbio_v6_1_init_registers(struct amdgpu_device *adev)
 261 {
 262         uint32_t def, data;
 263
 264         def = data = RREG32_PCIE(smnPCIE_CONFIG_CNTL);
 265         data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1);
 266         data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1);
 267
 268         if (def != data)
 269                 WREG32_PCIE(smnPCIE_CONFIG_CNTL, data);
 270
 271         def = data = RREG32_PCIE(smnPCIE_CI_CNTL);
 272         data = REG_SET_FIELD(data, PCIE_CI_CNTL, CI_SLV_ORDERING_DIS, 1);
 273
 274         if (def != data)
 275                 WREG32_PCIE(smnPCIE_CI_CNTL, data);
 276 }
 277
 278 const struct amdgpu_nbio_funcs nbio_v6_1_funcs = {
 279         .hdp_flush_reg = &nbio_v6_1_hdp_flush_reg,
 280         .get_hdp_flush_req_offset = nbio_v6_1_get_hdp_flush_req_offset,
 281         .get_hdp_flush_done_offset = nbio_v6_1_get_hdp_flush_done_offset,
 282         .get_pcie_index_offset = nbio_v6_1_get_pcie_index_offset,
 283         .get_pcie_data_offset = nbio_v6_1_get_pcie_data_offset,
 284         .get_rev_id = nbio_v6_1_get_rev_id,
 285         .mc_access_enable = nbio_v6_1_mc_access_enable,
 286         .hdp_flush = nbio_v6_1_hdp_flush,
 287         .get_memsize = nbio_v6_1_get_memsize,
 288         .sdma_doorbell_range = nbio_v6_1_sdma_doorbell_range,
 289         .enable_doorbell_aperture = nbio_v6_1_enable_doorbell_aperture,
 290         .enable_doorbell_selfring_aperture = nbio_v6_1_enable_doorbell_selfring_aperture,
 291         .ih_doorbell_range = nbio_v6_1_ih_doorbell_range,
 292         .update_medium_grain_clock_gating = nbio_v6_1_update_medium_grain_clock_gating,
 293         .update_medium_grain_light_sleep = nbio_v6_1_update_medium_grain_light_sleep,
 294         .get_clockgating_state = nbio_v6_1_get_clockgating_state,
 295         .ih_control = nbio_v6_1_ih_control,
 296         .init_registers = nbio_v6_1_init_registers,
 297         .detect_hw_virt = nbio_v6_1_detect_hw_virt,
 298 };