drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include "amdgpu.h"
  24 #include "amdgpu_atombios.h"
  25 #include "nbio_v7_4.h"
  26
  27 #include "nbio/nbio_7_4_offset.h"
  28 #include "nbio/nbio_7_4_sh_mask.h"
  29 #include "nbio/nbio_7_4_0_smn.h"
  30
  31 #define smnNBIF_MGCG_CTRL_LCLK  0x1013a21c
  32
  33 static u32 nbio_v7_4_get_rev_id(struct amdgpu_device *adev)
  34 {
  35         u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
  36
  37         tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
  38         tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
  39
  40         return tmp;
  41 }
  42
  43 static void nbio_v7_4_mc_access_enable(struct amdgpu_device *adev, bool enable)
  44 {
  45         if (enable)
  46                 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN,
  47                         BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
  48         else
  49                 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0);
  50 }
  51
  52 static void nbio_v7_4_hdp_flush(struct amdgpu_device *adev,
  53                                 struct amdgpu_ring *ring)
  54 {
  55         if (!ring || !ring->funcs->emit_wreg)
  56                 WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
  57         else
  58                 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
  59                         NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL), 0);
  60 }
  61
  62 static u32 nbio_v7_4_get_memsize(struct amdgpu_device *adev)
  63 {
  64         return RREG32_SOC15(NBIO, 0, mmRCC_CONFIG_MEMSIZE);
  65 }
  66
  67 static void nbio_v7_4_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
  68                         bool use_doorbell, int doorbell_index, int doorbell_size)
  69 {
  70         u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) :
  71                         SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE);
  72
  73         u32 doorbell_range = RREG32(reg);
  74
  75         if (use_doorbell) {
  76                 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index);
  77                 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, doorbell_size);
  78         } else
  79                 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0);
  80
  81         WREG32(reg, doorbell_range);
  82 }
  83
  84 static void nbio_v7_4_enable_doorbell_aperture(struct amdgpu_device *adev,
  85                                                bool enable)
  86 {
  87         WREG32_FIELD15(NBIO, 0, RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, enable ? 1 : 0);
  88 }
  89
  90 static void nbio_v7_4_enable_doorbell_selfring_aperture(struct amdgpu_device *adev,
  91                                                         bool enable)
  92 {
  93         u32 tmp = 0;
  94
  95         if (enable) {
  96                 tmp = REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_EN, 1) |
  97                       REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_MODE, 1) |
  98                       REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_SIZE, 0);
  99
 100                 WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_BASE_LOW,
 101                              lower_32_bits(adev->doorbell.base));
 102                 WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_BASE_HIGH,
 103                              upper_32_bits(adev->doorbell.base));
 104         }
 105
 106         WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_CNTL, tmp);
 107 }
 108
 109 static void nbio_v7_4_ih_doorbell_range(struct amdgpu_device *adev,
 110                                         bool use_doorbell, int doorbell_index)
 111 {
 112         u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0 , mmBIF_IH_DOORBELL_RANGE);
 113
 114         if (use_doorbell) {
 115                 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index);
 116                 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 2);
 117         } else
 118                 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 0);
 119
 120         WREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE, ih_doorbell_range);
 121 }
 122
 123
 124 static void nbio_v7_4_update_medium_grain_clock_gating(struct amdgpu_device *adev,
 125                                                        bool enable)
 126 {
 127         //TODO: Add support for v7.4
 128 }
 129
 130 static void nbio_v7_4_update_medium_grain_light_sleep(struct amdgpu_device *adev,
 131                                                       bool enable)
 132 {
 133         uint32_t def, data;
 134
 135         def = data = RREG32_PCIE(smnPCIE_CNTL2);
 136         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) {
 137                 data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
 138                          PCIE_CNTL2__MST_MEM_LS_EN_MASK |
 139                          PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
 140         } else {
 141                 data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
 142                           PCIE_CNTL2__MST_MEM_LS_EN_MASK |
 143                           PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
 144         }
 145
 146         if (def != data)
 147                 WREG32_PCIE(smnPCIE_CNTL2, data);
 148 }
 149
 150 static void nbio_v7_4_get_clockgating_state(struct amdgpu_device *adev,
 151                                             u32 *flags)
 152 {
 153         int data;
 154
 155         /* AMD_CG_SUPPORT_BIF_MGCG */
 156         data = RREG32_PCIE(smnCPM_CONTROL);
 157         if (data & CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK)
 158                 *flags |= AMD_CG_SUPPORT_BIF_MGCG;
 159
 160         /* AMD_CG_SUPPORT_BIF_LS */
 161         data = RREG32_PCIE(smnPCIE_CNTL2);
 162         if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK)
 163                 *flags |= AMD_CG_SUPPORT_BIF_LS;
 164 }
 165
 166 static void nbio_v7_4_ih_control(struct amdgpu_device *adev)
 167 {
 168         u32 interrupt_cntl;
 169
 170         /* setup interrupt control */
 171         WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8);
 172         interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL);
 173         /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
 174          * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
 175          */
 176         interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);
 177         /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
 178         interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);
 179         WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl);
 180 }
 181
 182 static u32 nbio_v7_4_get_hdp_flush_req_offset(struct amdgpu_device *adev)
 183 {
 184         return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_REQ);
 185 }
 186
 187 static u32 nbio_v7_4_get_hdp_flush_done_offset(struct amdgpu_device *adev)
 188 {
 189         return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_DONE);
 190 }
 191
 192 static u32 nbio_v7_4_get_pcie_index_offset(struct amdgpu_device *adev)
 193 {
 194         return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2);
 195 }
 196
 197 static u32 nbio_v7_4_get_pcie_data_offset(struct amdgpu_device *adev)
 198 {
 199         return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2);
 200 }
 201
 202 static const struct nbio_hdp_flush_reg nbio_v7_4_hdp_flush_reg = {
 203         .ref_and_mask_cp0 = GPU_HDP_FLUSH_DONE__CP0_MASK,
 204         .ref_and_mask_cp1 = GPU_HDP_FLUSH_DONE__CP1_MASK,
 205         .ref_and_mask_cp2 = GPU_HDP_FLUSH_DONE__CP2_MASK,
 206         .ref_and_mask_cp3 = GPU_HDP_FLUSH_DONE__CP3_MASK,
 207         .ref_and_mask_cp4 = GPU_HDP_FLUSH_DONE__CP4_MASK,
 208         .ref_and_mask_cp5 = GPU_HDP_FLUSH_DONE__CP5_MASK,
 209         .ref_and_mask_cp6 = GPU_HDP_FLUSH_DONE__CP6_MASK,
 210         .ref_and_mask_cp7 = GPU_HDP_FLUSH_DONE__CP7_MASK,
 211         .ref_and_mask_cp8 = GPU_HDP_FLUSH_DONE__CP8_MASK,
 212         .ref_and_mask_cp9 = GPU_HDP_FLUSH_DONE__CP9_MASK,
 213         .ref_and_mask_sdma0 = GPU_HDP_FLUSH_DONE__SDMA0_MASK,
 214         .ref_and_mask_sdma1 = GPU_HDP_FLUSH_DONE__SDMA1_MASK,
 215 };
 216
 217 static void nbio_v7_4_detect_hw_virt(struct amdgpu_device *adev)
 218 {
 219         uint32_t reg;
 220
 221         reg = RREG32_SOC15(NBIO, 0, mmRCC_IOV_FUNC_IDENTIFIER);
 222         if (reg & 1)
 223                 adev->virt.caps |= AMDGPU_SRIOV_CAPS_IS_VF;
 224
 225         if (reg & 0x80000000)
 226                 adev->virt.caps |= AMDGPU_SRIOV_CAPS_ENABLE_IOV;
 227
 228         if (!reg) {
 229                 if (is_virtual_machine())       /* passthrough mode exclus sriov mod */
 230                         adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE;
 231         }
 232 }
 233
 234 static void nbio_v7_4_init_registers(struct amdgpu_device *adev)
 235 {
 236         uint32_t def, data;
 237
 238         def = data = RREG32_PCIE(smnPCIE_CI_CNTL);
 239         data = REG_SET_FIELD(data, PCIE_CI_CNTL, CI_SLV_ORDERING_DIS, 1);
 240
 241         if (def != data)
 242                 WREG32_PCIE(smnPCIE_CI_CNTL, data);
 243 }
 244
 245 const struct amdgpu_nbio_funcs nbio_v7_4_funcs = {
 246         .hdp_flush_reg = &nbio_v7_4_hdp_flush_reg,
 247         .get_hdp_flush_req_offset = nbio_v7_4_get_hdp_flush_req_offset,
 248         .get_hdp_flush_done_offset = nbio_v7_4_get_hdp_flush_done_offset,
 249         .get_pcie_index_offset = nbio_v7_4_get_pcie_index_offset,
 250         .get_pcie_data_offset = nbio_v7_4_get_pcie_data_offset,
 251         .get_rev_id = nbio_v7_4_get_rev_id,
 252         .mc_access_enable = nbio_v7_4_mc_access_enable,
 253         .hdp_flush = nbio_v7_4_hdp_flush,
 254         .get_memsize = nbio_v7_4_get_memsize,
 255         .sdma_doorbell_range = nbio_v7_4_sdma_doorbell_range,
 256         .enable_doorbell_aperture = nbio_v7_4_enable_doorbell_aperture,
 257         .enable_doorbell_selfring_aperture = nbio_v7_4_enable_doorbell_selfring_aperture,
 258         .ih_doorbell_range = nbio_v7_4_ih_doorbell_range,
 259         .update_medium_grain_clock_gating = nbio_v7_4_update_medium_grain_clock_gating,
 260         .update_medium_grain_light_sleep = nbio_v7_4_update_medium_grain_light_sleep,
 261         .get_clockgating_state = nbio_v7_4_get_clockgating_state,
 262         .ih_control = nbio_v7_4_ih_control,
 263         .init_registers = nbio_v7_4_init_registers,
 264         .detect_hw_virt = nbio_v7_4_detect_hw_virt,
 265 };