drivers/gpu/drm/amd/amdgpu/psp_v10_0.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Author: Huang Rui
  23  *
  24  */
  25
  26 #include <linux/firmware.h>
  27 #include "amdgpu.h"
  28 #include "amdgpu_psp.h"
  29 #include "amdgpu_ucode.h"
  30 #include "soc15_common.h"
  31 #include "psp_v10_0.h"
  32
  33 #include "mp/mp_10_0_offset.h"
  34 #include "gc/gc_9_1_offset.h"
  35 #include "sdma0/sdma0_4_1_offset.h"
  36
  37 MODULE_FIRMWARE("amdgpu/raven_asd.bin");
  38 MODULE_FIRMWARE("amdgpu/picasso_asd.bin");
  39 MODULE_FIRMWARE("amdgpu/raven2_asd.bin");
  40
  41 static int psp_v10_0_init_microcode(struct psp_context *psp)
  42 {
  43         struct amdgpu_device *adev = psp->adev;
  44         const char *chip_name;
  45         char fw_name[30];
  46         int err = 0;
  47         const struct psp_firmware_header_v1_0 *hdr;
  48
  49         DRM_DEBUG("\n");
  50
  51         switch (adev->asic_type) {
  52         case CHIP_RAVEN:
  53                 if (adev->rev_id >= 0x8)
  54                         chip_name = "raven2";
  55                 else if (adev->pdev->device == 0x15d8)
  56                         chip_name = "picasso";
  57                 else
  58                         chip_name = "raven";
  59                 break;
  60         default: BUG();
  61         }
  62
  63         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name);
  64         err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev);
  65         if (err)
  66                 goto out;
  67
  68         err = amdgpu_ucode_validate(adev->psp.asd_fw);
  69         if (err)
  70                 goto out;
  71
  72         hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data;
  73         adev->psp.asd_fw_version = le32_to_cpu(hdr->header.ucode_version);
  74         adev->psp.asd_feature_version = le32_to_cpu(hdr->ucode_feature_version);
  75         adev->psp.asd_ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes);
  76         adev->psp.asd_start_addr = (uint8_t *)hdr +
  77                                 le32_to_cpu(hdr->header.ucode_array_offset_bytes);
  78
  79         return 0;
  80 out:
  81         if (err) {
  82                 dev_err(adev->dev,
  83                         "psp v10.0: Failed to load firmware \"%s\"\n",
  84                         fw_name);
  85                 release_firmware(adev->psp.asd_fw);
  86                 adev->psp.asd_fw = NULL;
  87         }
  88
  89         return err;
  90 }
  91
  92 static int psp_v10_0_ring_init(struct psp_context *psp,
  93                                enum psp_ring_type ring_type)
  94 {
  95         int ret = 0;
  96         struct psp_ring *ring;
  97         struct amdgpu_device *adev = psp->adev;
  98
  99         ring = &psp->km_ring;
 100
 101         ring->ring_type = ring_type;
 102
 103         /* allocate 4k Page of Local Frame Buffer memory for ring */
 104         ring->ring_size = 0x1000;
 105         ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
 106                                       AMDGPU_GEM_DOMAIN_VRAM,
 107                                       &adev->firmware.rbuf,
 108                                       &ring->ring_mem_mc_addr,
 109                                       (void **)&ring->ring_mem);
 110         if (ret) {
 111                 ring->ring_size = 0;
 112                 return ret;
 113         }
 114
 115         return 0;
 116 }
 117
 118 static int psp_v10_0_ring_create(struct psp_context *psp,
 119                                  enum psp_ring_type ring_type)
 120 {
 121         int ret = 0;
 122         unsigned int psp_ring_reg = 0;
 123         struct psp_ring *ring = &psp->km_ring;
 124         struct amdgpu_device *adev = psp->adev;
 125
 126         /* Write low address of the ring to C2PMSG_69 */
 127         psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
 128         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
 129         /* Write high address of the ring to C2PMSG_70 */
 130         psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
 131         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
 132         /* Write size of ring to C2PMSG_71 */
 133         psp_ring_reg = ring->ring_size;
 134         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
 135         /* Write the ring initialization command to C2PMSG_64 */
 136         psp_ring_reg = ring_type;
 137         psp_ring_reg = psp_ring_reg << 16;
 138         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
 139
 140         /* There might be handshake issue with hardware which needs delay */
 141         mdelay(20);
 142
 143         /* Wait for response flag (bit 31) in C2PMSG_64 */
 144         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
 145                            0x80000000, 0x8000FFFF, false);
 146
 147         return ret;
 148 }
 149
 150 static int psp_v10_0_ring_stop(struct psp_context *psp,
 151                                enum psp_ring_type ring_type)
 152 {
 153         int ret = 0;
 154         unsigned int psp_ring_reg = 0;
 155         struct amdgpu_device *adev = psp->adev;
 156
 157         /* Write the ring destroy command to C2PMSG_64 */
 158         psp_ring_reg = 3 << 16;
 159         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
 160
 161         /* There might be handshake issue with hardware which needs delay */
 162         mdelay(20);
 163
 164         /* Wait for response flag (bit 31) in C2PMSG_64 */
 165         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
 166                            0x80000000, 0x80000000, false);
 167
 168         return ret;
 169 }
 170
 171 static int psp_v10_0_ring_destroy(struct psp_context *psp,
 172                                   enum psp_ring_type ring_type)
 173 {
 174         int ret = 0;
 175         struct psp_ring *ring = &psp->km_ring;
 176         struct amdgpu_device *adev = psp->adev;
 177
 178         ret = psp_v10_0_ring_stop(psp, ring_type);
 179         if (ret)
 180                 DRM_ERROR("Fail to stop psp ring\n");
 181
 182         amdgpu_bo_free_kernel(&adev->firmware.rbuf,
 183                               &ring->ring_mem_mc_addr,
 184                               (void **)&ring->ring_mem);
 185
 186         return ret;
 187 }
 188
 189 static int psp_v10_0_cmd_submit(struct psp_context *psp,
 190                                 struct amdgpu_firmware_info *ucode,
 191                                 uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
 192                                 int index)
 193 {
 194         unsigned int psp_write_ptr_reg = 0;
 195         struct psp_gfx_rb_frame * write_frame = psp->km_ring.ring_mem;
 196         struct psp_ring *ring = &psp->km_ring;
 197         struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
 198         struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
 199                 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
 200         struct amdgpu_device *adev = psp->adev;
 201         uint32_t ring_size_dw = ring->ring_size / 4;
 202         uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
 203
 204         /* KM (GPCOM) prepare write pointer */
 205         psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
 206
 207         /* Update KM RB frame pointer to new frame */
 208         if ((psp_write_ptr_reg % ring_size_dw) == 0)
 209                 write_frame = ring_buffer_start;
 210         else
 211                 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw);
 212         /* Check invalid write_frame ptr address */
 213         if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) {
 214                 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
 215                           ring_buffer_start, ring_buffer_end, write_frame);
 216                 DRM_ERROR("write_frame is pointing to address out of bounds\n");
 217                 return -EINVAL;
 218         }
 219
 220         /* Initialize KM RB frame */
 221         memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
 222
 223         /* Update KM RB frame */
 224         write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
 225         write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
 226         write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
 227         write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
 228         write_frame->fence_value = index;
 229
 230         /* Update the write Pointer in DWORDs */
 231         psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
 232         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg);
 233
 234         return 0;
 235 }
 236
 237 static int
 238 psp_v10_0_sram_map(struct amdgpu_device *adev,
 239                    unsigned int *sram_offset, unsigned int *sram_addr_reg_offset,
 240                    unsigned int *sram_data_reg_offset,
 241                    enum AMDGPU_UCODE_ID ucode_id)
 242 {
 243         int ret = 0;
 244
 245         switch(ucode_id) {
 246 /* TODO: needs to confirm */
 247 #if 0
 248         case AMDGPU_UCODE_ID_SMC:
 249                 *sram_offset = 0;
 250                 *sram_addr_reg_offset = 0;
 251                 *sram_data_reg_offset = 0;
 252                 break;
 253 #endif
 254
 255         case AMDGPU_UCODE_ID_CP_CE:
 256                 *sram_offset = 0x0;
 257                 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR);
 258                 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA);
 259                 break;
 260
 261         case AMDGPU_UCODE_ID_CP_PFP:
 262                 *sram_offset = 0x0;
 263                 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR);
 264                 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA);
 265                 break;
 266
 267         case AMDGPU_UCODE_ID_CP_ME:
 268                 *sram_offset = 0x0;
 269                 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR);
 270                 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA);
 271                 break;
 272
 273         case AMDGPU_UCODE_ID_CP_MEC1:
 274                 *sram_offset = 0x10000;
 275                 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR);
 276                 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA);
 277                 break;
 278
 279         case AMDGPU_UCODE_ID_CP_MEC2:
 280                 *sram_offset = 0x10000;
 281                 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR);
 282                 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA);
 283                 break;
 284
 285         case AMDGPU_UCODE_ID_RLC_G:
 286                 *sram_offset = 0x2000;
 287                 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR);
 288                 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA);
 289                 break;
 290
 291         case AMDGPU_UCODE_ID_SDMA0:
 292                 *sram_offset = 0x0;
 293                 *sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR);
 294                 *sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA);
 295                 break;
 296
 297 /* TODO: needs to confirm */
 298 #if 0
 299         case AMDGPU_UCODE_ID_SDMA1:
 300                 *sram_offset = ;
 301                 *sram_addr_reg_offset = ;
 302                 break;
 303
 304         case AMDGPU_UCODE_ID_UVD:
 305                 *sram_offset = ;
 306                 *sram_addr_reg_offset = ;
 307                 break;
 308
 309         case AMDGPU_UCODE_ID_VCE:
 310                 *sram_offset = ;
 311                 *sram_addr_reg_offset = ;
 312                 break;
 313 #endif
 314
 315         case AMDGPU_UCODE_ID_MAXIMUM:
 316         default:
 317                 ret = -EINVAL;
 318                 break;
 319         }
 320
 321         return ret;
 322 }
 323
 324 static bool psp_v10_0_compare_sram_data(struct psp_context *psp,
 325                                         struct amdgpu_firmware_info *ucode,
 326                                         enum AMDGPU_UCODE_ID ucode_type)
 327 {
 328         int err = 0;
 329         unsigned int fw_sram_reg_val = 0;
 330         unsigned int fw_sram_addr_reg_offset = 0;
 331         unsigned int fw_sram_data_reg_offset = 0;
 332         unsigned int ucode_size;
 333         uint32_t *ucode_mem = NULL;
 334         struct amdgpu_device *adev = psp->adev;
 335
 336         err = psp_v10_0_sram_map(adev, &fw_sram_reg_val, &fw_sram_addr_reg_offset,
 337                                 &fw_sram_data_reg_offset, ucode_type);
 338         if (err)
 339                 return false;
 340
 341         WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val);
 342
 343         ucode_size = ucode->ucode_size;
 344         ucode_mem = (uint32_t *)ucode->kaddr;
 345         while (!ucode_size) {
 346                 fw_sram_reg_val = RREG32(fw_sram_data_reg_offset);
 347
 348                 if (*ucode_mem != fw_sram_reg_val)
 349                         return false;
 350
 351                 ucode_mem++;
 352                 /* 4 bytes */
 353                 ucode_size -= 4;
 354         }
 355
 356         return true;
 357 }
 358
 359
 360 static int psp_v10_0_mode1_reset(struct psp_context *psp)
 361 {
 362         DRM_INFO("psp mode 1 reset not supported now! \n");
 363         return -EINVAL;
 364 }
 365
 366 static const struct psp_funcs psp_v10_0_funcs = {
 367         .init_microcode = psp_v10_0_init_microcode,
 368         .ring_init = psp_v10_0_ring_init,
 369         .ring_create = psp_v10_0_ring_create,
 370         .ring_stop = psp_v10_0_ring_stop,
 371         .ring_destroy = psp_v10_0_ring_destroy,
 372         .cmd_submit = psp_v10_0_cmd_submit,
 373         .compare_sram_data = psp_v10_0_compare_sram_data,
 374         .mode1_reset = psp_v10_0_mode1_reset,
 375 };
 376
 377 void psp_v10_0_set_psp_funcs(struct psp_context *psp)
 378 {
 379         psp->funcs = &psp_v10_0_funcs;
 380 }