drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include "amdgpu.h"
  24 #include "soc15.h"
  25
  26 #include "soc15_common.h"
  27 #include "soc15_hw_ip.h"
  28 #include "vega10_ip_offset.h"
  29
  30 int vega10_reg_base_init(struct amdgpu_device *adev)
  31 {
  32         /* HW has more IP blocks,  only initialized the blocke beend by our driver  */
  33         uint32_t i;
  34         for (i = 0 ; i < MAX_INSTANCE ; ++i) {
  35                 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
  36                 adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i]));
  37                 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i]));
  38                 adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i]));
  39                 adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));
  40                 adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i]));
  41                 adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i]));
  42                 adev->reg_offset[UVD_HWIP][i] = (uint32_t *)(&(UVD_BASE.instance[i]));
  43                 adev->reg_offset[VCE_HWIP][i] = (uint32_t *)(&(VCE_BASE.instance[i]));
  44                 adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(VCN_BASE.instance[i]));
  45                 adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i]));
  46                 adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DCE_BASE.instance[i]));
  47                 adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i]));
  48                 adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(SDMA0_BASE.instance[i]));
  49                 adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(SDMA1_BASE.instance[i]));
  50                 adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i]));
  51                 adev->reg_offset[PWR_HWIP][i] = (uint32_t *)(&(PWR_BASE.instance[i]));
  52                 adev->reg_offset[NBIF_HWIP][i] = (uint32_t *)(&(NBIF_BASE.instance[i]));
  53                 adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i]));
  54                 adev->reg_offset[CLK_HWIP][i] = (uint32_t *)(&(CLK_BASE.instance[i]));
  55         }
  56         return 0;
  57 }
  58
  59 void vega10_doorbell_index_init(struct amdgpu_device *adev)
  60 {
  61         adev->doorbell_index.kiq = AMDGPU_DOORBELL64_KIQ;
  62         adev->doorbell_index.mec_ring0 = AMDGPU_DOORBELL64_MEC_RING0;
  63         adev->doorbell_index.mec_ring1 = AMDGPU_DOORBELL64_MEC_RING1;
  64         adev->doorbell_index.mec_ring2 = AMDGPU_DOORBELL64_MEC_RING2;
  65         adev->doorbell_index.mec_ring3 = AMDGPU_DOORBELL64_MEC_RING3;
  66         adev->doorbell_index.mec_ring4 = AMDGPU_DOORBELL64_MEC_RING4;
  67         adev->doorbell_index.mec_ring5 = AMDGPU_DOORBELL64_MEC_RING5;
  68         adev->doorbell_index.mec_ring6 = AMDGPU_DOORBELL64_MEC_RING6;
  69         adev->doorbell_index.mec_ring7 = AMDGPU_DOORBELL64_MEC_RING7;
  70         adev->doorbell_index.userqueue_start = AMDGPU_DOORBELL64_USERQUEUE_START;
  71         adev->doorbell_index.userqueue_end = AMDGPU_DOORBELL64_USERQUEUE_END;
  72         adev->doorbell_index.gfx_ring0 = AMDGPU_DOORBELL64_GFX_RING0;
  73         adev->doorbell_index.sdma_engine[0] = AMDGPU_DOORBELL64_sDMA_ENGINE0;
  74         adev->doorbell_index.sdma_engine[1] = AMDGPU_DOORBELL64_sDMA_ENGINE1;
  75         adev->doorbell_index.ih = AMDGPU_DOORBELL64_IH;
  76         adev->doorbell_index.uvd_vce.uvd_ring0_1 = AMDGPU_DOORBELL64_UVD_RING0_1;
  77         adev->doorbell_index.uvd_vce.uvd_ring2_3 = AMDGPU_DOORBELL64_UVD_RING2_3;
  78         adev->doorbell_index.uvd_vce.uvd_ring4_5 = AMDGPU_DOORBELL64_UVD_RING4_5;
  79         adev->doorbell_index.uvd_vce.uvd_ring6_7 = AMDGPU_DOORBELL64_UVD_RING6_7;
  80         adev->doorbell_index.uvd_vce.vce_ring0_1 = AMDGPU_DOORBELL64_VCE_RING0_1;
  81         adev->doorbell_index.uvd_vce.vce_ring2_3 = AMDGPU_DOORBELL64_VCE_RING2_3;
  82         adev->doorbell_index.uvd_vce.vce_ring4_5 = AMDGPU_DOORBELL64_VCE_RING4_5;
  83         adev->doorbell_index.uvd_vce.vce_ring6_7 = AMDGPU_DOORBELL64_VCE_RING6_7;
  84
  85         adev->doorbell_index.first_non_cp = AMDGPU_DOORBELL64_FIRST_NON_CP;
  86         adev->doorbell_index.last_non_cp = AMDGPU_DOORBELL64_LAST_NON_CP;
  87
  88         /* In unit of dword doorbell */
  89         adev->doorbell_index.max_assignment = AMDGPU_DOORBELL64_MAX_ASSIGNMENT << 1;
  90         adev->doorbell_index.sdma_doorbell_range = 4;
  91 }
  92