2 * Copyright (C) 2016 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 #ifndef __VEGA10_SDMA_PKT_OPEN_H_
24 #define __VEGA10_SDMA_PKT_OPEN_H_
27 #define SDMA_OP_COPY 1
28 #define SDMA_OP_WRITE 2
29 #define SDMA_OP_INDIRECT 4
30 #define SDMA_OP_FENCE 5
31 #define SDMA_OP_TRAP 6
33 #define SDMA_OP_POLL_REGMEM 8
34 #define SDMA_OP_COND_EXE 9
35 #define SDMA_OP_ATOMIC 10
36 #define SDMA_OP_CONST_FILL 11
37 #define SDMA_OP_PTEPDE 12
38 #define SDMA_OP_TIMESTAMP 13
39 #define SDMA_OP_SRBM_WRITE 14
40 #define SDMA_OP_PRE_EXE 15
41 #define SDMA_OP_DUMMY_TRAP 16
42 #define SDMA_SUBOP_TIMESTAMP_SET 0
43 #define SDMA_SUBOP_TIMESTAMP_GET 1
44 #define SDMA_SUBOP_TIMESTAMP_GET_GLOBAL 2
45 #define SDMA_SUBOP_COPY_LINEAR 0
46 #define SDMA_SUBOP_COPY_LINEAR_SUB_WIND 4
47 #define SDMA_SUBOP_COPY_TILED 1
48 #define SDMA_SUBOP_COPY_TILED_SUB_WIND 5
49 #define SDMA_SUBOP_COPY_T2T_SUB_WIND 6
50 #define SDMA_SUBOP_COPY_SOA 3
51 #define SDMA_SUBOP_COPY_DIRTY_PAGE 7
52 #define SDMA_SUBOP_COPY_LINEAR_PHY 8
53 #define SDMA_SUBOP_WRITE_LINEAR 0
54 #define SDMA_SUBOP_WRITE_TILED 1
55 #define SDMA_SUBOP_PTEPDE_GEN 0
56 #define SDMA_SUBOP_PTEPDE_COPY 1
57 #define SDMA_SUBOP_PTEPDE_RMW 2
58 #define SDMA_SUBOP_PTEPDE_COPY_BACKWARDS 3
59 #define SDMA_SUBOP_DATA_FILL_MULTI 1
60 #define SDMA_SUBOP_POLL_REG_WRITE_MEM 1
61 #define SDMA_SUBOP_POLL_DBIT_WRITE_MEM 2
62 #define SDMA_SUBOP_POLL_MEM_VERIFY 3
63 #define HEADER_AGENT_DISPATCH 4
64 #define HEADER_BARRIER 5
65 #define SDMA_OP_AQL_COPY 0
66 #define SDMA_OP_AQL_BARRIER_OR 0
68 /*define for op field*/
69 #define SDMA_PKT_HEADER_op_offset 0
70 #define SDMA_PKT_HEADER_op_mask 0x000000FF
71 #define SDMA_PKT_HEADER_op_shift 0
72 #define SDMA_PKT_HEADER_OP(x) (((x) & SDMA_PKT_HEADER_op_mask) << SDMA_PKT_HEADER_op_shift)
74 /*define for sub_op field*/
75 #define SDMA_PKT_HEADER_sub_op_offset 0
76 #define SDMA_PKT_HEADER_sub_op_mask 0x000000FF
77 #define SDMA_PKT_HEADER_sub_op_shift 8
78 #define SDMA_PKT_HEADER_SUB_OP(x) (((x) & SDMA_PKT_HEADER_sub_op_mask) << SDMA_PKT_HEADER_sub_op_shift)
82 ** Definitions for SDMA_PKT_COPY_LINEAR packet
85 /*define for HEADER word*/
86 /*define for op field*/
87 #define SDMA_PKT_COPY_LINEAR_HEADER_op_offset 0
88 #define SDMA_PKT_COPY_LINEAR_HEADER_op_mask 0x000000FF
89 #define SDMA_PKT_COPY_LINEAR_HEADER_op_shift 0
90 #define SDMA_PKT_COPY_LINEAR_HEADER_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_op_mask) << SDMA_PKT_COPY_LINEAR_HEADER_op_shift)
92 /*define for sub_op field*/
93 #define SDMA_PKT_COPY_LINEAR_HEADER_sub_op_offset 0
94 #define SDMA_PKT_COPY_LINEAR_HEADER_sub_op_mask 0x000000FF
95 #define SDMA_PKT_COPY_LINEAR_HEADER_sub_op_shift 8
96 #define SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_sub_op_mask) << SDMA_PKT_COPY_LINEAR_HEADER_sub_op_shift)
98 /*define for encrypt field*/
99 #define SDMA_PKT_COPY_LINEAR_HEADER_encrypt_offset 0
100 #define SDMA_PKT_COPY_LINEAR_HEADER_encrypt_mask 0x00000001
101 #define SDMA_PKT_COPY_LINEAR_HEADER_encrypt_shift 16
102 #define SDMA_PKT_COPY_LINEAR_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_encrypt_mask) << SDMA_PKT_COPY_LINEAR_HEADER_encrypt_shift)
104 /*define for tmz field*/
105 #define SDMA_PKT_COPY_LINEAR_HEADER_tmz_offset 0
106 #define SDMA_PKT_COPY_LINEAR_HEADER_tmz_mask 0x00000001
107 #define SDMA_PKT_COPY_LINEAR_HEADER_tmz_shift 18
108 #define SDMA_PKT_COPY_LINEAR_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_tmz_mask) << SDMA_PKT_COPY_LINEAR_HEADER_tmz_shift)
110 /*define for broadcast field*/
111 #define SDMA_PKT_COPY_LINEAR_HEADER_broadcast_offset 0
112 #define SDMA_PKT_COPY_LINEAR_HEADER_broadcast_mask 0x00000001
113 #define SDMA_PKT_COPY_LINEAR_HEADER_broadcast_shift 27
114 #define SDMA_PKT_COPY_LINEAR_HEADER_BROADCAST(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_broadcast_mask) << SDMA_PKT_COPY_LINEAR_HEADER_broadcast_shift)
116 /*define for COUNT word*/
117 /*define for count field*/
118 #define SDMA_PKT_COPY_LINEAR_COUNT_count_offset 1
119 #define SDMA_PKT_COPY_LINEAR_COUNT_count_mask 0x003FFFFF
120 #define SDMA_PKT_COPY_LINEAR_COUNT_count_shift 0
121 #define SDMA_PKT_COPY_LINEAR_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_LINEAR_COUNT_count_mask) << SDMA_PKT_COPY_LINEAR_COUNT_count_shift)
123 /*define for PARAMETER word*/
124 /*define for dst_sw field*/
125 #define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset 2
126 #define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask 0x00000003
127 #define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift 16
128 #define SDMA_PKT_COPY_LINEAR_PARAMETER_DST_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask) << SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift)
130 /*define for src_sw field*/
131 #define SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_offset 2
132 #define SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_mask 0x00000003
133 #define SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_shift 24
134 #define SDMA_PKT_COPY_LINEAR_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_shift)
136 /*define for SRC_ADDR_LO word*/
137 /*define for src_addr_31_0 field*/
138 #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset 3
139 #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF
140 #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift 0
141 #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift)
143 /*define for SRC_ADDR_HI word*/
144 /*define for src_addr_63_32 field*/
145 #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset 4
146 #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF
147 #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift 0
148 #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift)
150 /*define for DST_ADDR_LO word*/
151 /*define for dst_addr_31_0 field*/
152 #define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset 5
153 #define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF
154 #define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift 0
155 #define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift)
157 /*define for DST_ADDR_HI word*/
158 /*define for dst_addr_63_32 field*/
159 #define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset 6
160 #define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF
161 #define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift 0
162 #define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift)
166 ** Definitions for SDMA_PKT_COPY_DIRTY_PAGE packet
169 /*define for HEADER word*/
170 /*define for op field*/
171 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_offset 0
172 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_mask 0x000000FF
173 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_shift 0
174 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_OP(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_mask) << SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_shift)
176 /*define for sub_op field*/
177 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_offset 0
178 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_mask 0x000000FF
179 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_shift 8
180 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_mask) << SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_shift)
182 /*define for tmz field*/
183 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_offset 0
184 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_mask 0x00000001
185 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_shift 18
186 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_mask) << SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_shift)
188 /*define for all field*/
189 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_offset 0
190 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_mask 0x00000001
191 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_shift 31
192 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_ALL(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_mask) << SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_shift)
194 /*define for COUNT word*/
195 /*define for count field*/
196 #define SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_offset 1
197 #define SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_mask 0x003FFFFF
198 #define SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_shift 0
199 #define SDMA_PKT_COPY_DIRTY_PAGE_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_mask) << SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_shift)
201 /*define for PARAMETER word*/
202 /*define for dst_sw field*/
203 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_offset 2
204 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_mask 0x00000003
205 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_shift 16
206 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SW(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_shift)
208 /*define for dst_gcc field*/
209 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_offset 2
210 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_mask 0x00000001
211 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_shift 19
212 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_GCC(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_shift)
214 /*define for dst_sys field*/
215 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_offset 2
216 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_mask 0x00000001
217 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_shift 20
218 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SYS(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_shift)
220 /*define for dst_snoop field*/
221 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_offset 2
222 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_mask 0x00000001
223 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_shift 22
224 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SNOOP(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_shift)
226 /*define for dst_gpa field*/
227 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_offset 2
228 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_mask 0x00000001
229 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_shift 23
230 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_GPA(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_shift)
232 /*define for src_sw field*/
233 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_offset 2
234 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_mask 0x00000003
235 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_shift 24
236 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_shift)
238 /*define for src_sys field*/
239 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_offset 2
240 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_mask 0x00000001
241 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_shift 28
242 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SYS(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_shift)
244 /*define for src_snoop field*/
245 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_offset 2
246 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_mask 0x00000001
247 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_shift 30
248 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SNOOP(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_shift)
250 /*define for src_gpa field*/
251 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_offset 2
252 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_mask 0x00000001
253 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_shift 31
254 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_GPA(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_shift)
256 /*define for SRC_ADDR_LO word*/
257 /*define for src_addr_31_0 field*/
258 #define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_offset 3
259 #define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF
260 #define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_shift 0
261 #define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_shift)
263 /*define for SRC_ADDR_HI word*/
264 /*define for src_addr_63_32 field*/
265 #define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_offset 4
266 #define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF
267 #define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_shift 0
268 #define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_shift)
270 /*define for DST_ADDR_LO word*/
271 /*define for dst_addr_31_0 field*/
272 #define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_offset 5
273 #define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF
274 #define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_shift 0
275 #define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_shift)
277 /*define for DST_ADDR_HI word*/
278 /*define for dst_addr_63_32 field*/
279 #define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_offset 6
280 #define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF
281 #define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_shift 0
282 #define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_shift)
286 ** Definitions for SDMA_PKT_COPY_PHYSICAL_LINEAR packet
289 /*define for HEADER word*/
290 /*define for op field*/
291 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_offset 0
292 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_mask 0x000000FF
293 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_shift 0
294 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_OP(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_shift)
296 /*define for sub_op field*/
297 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_offset 0
298 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_mask 0x000000FF
299 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_shift 8
300 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_shift)
302 /*define for tmz field*/
303 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_offset 0
304 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_mask 0x00000001
305 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_shift 18
306 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_shift)
308 /*define for COUNT word*/
309 /*define for count field*/
310 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_offset 1
311 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_mask 0x003FFFFF
312 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_shift 0
313 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_shift)
315 /*define for PARAMETER word*/
316 /*define for dst_sw field*/
317 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_offset 2
318 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_mask 0x00000003
319 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_shift 16
320 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SW(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_shift)
322 /*define for dst_gcc field*/
323 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_offset 2
324 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_mask 0x00000001
325 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_shift 19
326 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_GCC(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_shift)
328 /*define for dst_sys field*/
329 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_offset 2
330 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_mask 0x00000001
331 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_shift 20
332 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SYS(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_shift)
334 /*define for dst_log field*/
335 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_offset 2
336 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_mask 0x00000001
337 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_shift 21
338 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_LOG(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_shift)
340 /*define for dst_snoop field*/
341 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_offset 2
342 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_mask 0x00000001
343 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_shift 22
344 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SNOOP(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_shift)
346 /*define for dst_gpa field*/
347 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_offset 2
348 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_mask 0x00000001
349 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_shift 23
350 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_GPA(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_shift)
352 /*define for src_sw field*/
353 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_offset 2
354 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_mask 0x00000003
355 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_shift 24
356 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_shift)
358 /*define for src_gcc field*/
359 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_offset 2
360 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_mask 0x00000001
361 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_shift 27
362 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_GCC(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_shift)
364 /*define for src_sys field*/
365 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_offset 2
366 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_mask 0x00000001
367 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_shift 28
368 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SYS(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_shift)
370 /*define for src_snoop field*/
371 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_offset 2
372 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_mask 0x00000001
373 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_shift 30
374 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SNOOP(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_shift)
376 /*define for src_gpa field*/
377 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_offset 2
378 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_mask 0x00000001
379 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_shift 31
380 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_GPA(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_shift)
382 /*define for SRC_ADDR_LO word*/
383 /*define for src_addr_31_0 field*/
384 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset 3
385 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF
386 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift 0
387 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift)
389 /*define for SRC_ADDR_HI word*/
390 /*define for src_addr_63_32 field*/
391 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset 4
392 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF
393 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift 0
394 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift)
396 /*define for DST_ADDR_LO word*/
397 /*define for dst_addr_31_0 field*/
398 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset 5
399 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF
400 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift 0
401 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift)
403 /*define for DST_ADDR_HI word*/
404 /*define for dst_addr_63_32 field*/
405 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset 6
406 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF
407 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift 0
408 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift)
412 ** Definitions for SDMA_PKT_COPY_BROADCAST_LINEAR packet
415 /*define for HEADER word*/
416 /*define for op field*/
417 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_offset 0
418 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_mask 0x000000FF
419 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_shift 0
420 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_OP(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_shift)
422 /*define for sub_op field*/
423 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_offset 0
424 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_mask 0x000000FF
425 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_shift 8
426 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_shift)
428 /*define for encrypt field*/
429 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_offset 0
430 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_mask 0x00000001
431 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_shift 16
432 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_shift)
434 /*define for tmz field*/
435 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_offset 0
436 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_mask 0x00000001
437 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_shift 18
438 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_shift)
440 /*define for broadcast field*/
441 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_offset 0
442 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_mask 0x00000001
443 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_shift 27
444 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_BROADCAST(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_shift)
446 /*define for COUNT word*/
447 /*define for count field*/
448 #define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_offset 1
449 #define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_mask 0x003FFFFF
450 #define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_shift 0
451 #define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_shift)
453 /*define for PARAMETER word*/
454 /*define for dst2_sw field*/
455 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_offset 2
456 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_mask 0x00000003
457 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_shift 8
458 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST2_SW(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_shift)
460 /*define for dst1_sw field*/
461 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_offset 2
462 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_mask 0x00000003
463 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_shift 16
464 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST1_SW(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_shift)
466 /*define for src_sw field*/
467 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_offset 2
468 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_mask 0x00000003
469 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_shift 24
470 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_shift)
472 /*define for SRC_ADDR_LO word*/
473 /*define for src_addr_31_0 field*/
474 #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset 3
475 #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF
476 #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift 0
477 #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift)
479 /*define for SRC_ADDR_HI word*/
480 /*define for src_addr_63_32 field*/
481 #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset 4
482 #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF
483 #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift 0
484 #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift)
486 /*define for DST1_ADDR_LO word*/
487 /*define for dst1_addr_31_0 field*/
488 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_offset 5
489 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_mask 0xFFFFFFFF
490 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_shift 0
491 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_DST1_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_shift)
493 /*define for DST1_ADDR_HI word*/
494 /*define for dst1_addr_63_32 field*/
495 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_offset 6
496 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_mask 0xFFFFFFFF
497 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_shift 0
498 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_DST1_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_shift)
500 /*define for DST2_ADDR_LO word*/
501 /*define for dst2_addr_31_0 field*/
502 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_offset 7
503 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_mask 0xFFFFFFFF
504 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_shift 0
505 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_DST2_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_shift)
507 /*define for DST2_ADDR_HI word*/
508 /*define for dst2_addr_63_32 field*/
509 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_offset 8
510 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_mask 0xFFFFFFFF
511 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_shift 0
512 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_DST2_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_shift)
516 ** Definitions for SDMA_PKT_COPY_LINEAR_SUBWIN packet
519 /*define for HEADER word*/
520 /*define for op field*/
521 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_offset 0
522 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_mask 0x000000FF
523 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_shift 0
524 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_shift)
526 /*define for sub_op field*/
527 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_offset 0
528 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_mask 0x000000FF
529 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_shift 8
530 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_shift)
532 /*define for tmz field*/
533 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_offset 0
534 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_mask 0x00000001
535 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_shift 18
536 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_shift)
538 /*define for elementsize field*/
539 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_offset 0
540 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_mask 0x00000007
541 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_shift 29
542 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_ELEMENTSIZE(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_shift)
544 /*define for SRC_ADDR_LO word*/
545 /*define for src_addr_31_0 field*/
546 #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_offset 1
547 #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF
548 #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_shift 0
549 #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_shift)
551 /*define for SRC_ADDR_HI word*/
552 /*define for src_addr_63_32 field*/
553 #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_offset 2
554 #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF
555 #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_shift 0
556 #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_shift)
558 /*define for DW_3 word*/
559 /*define for src_x field*/
560 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_offset 3
561 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_mask 0x00003FFF
562 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_shift 0
563 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_SRC_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_shift)
565 /*define for src_y field*/
566 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_offset 3
567 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_mask 0x00003FFF
568 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_shift 16
569 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_SRC_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_shift)
571 /*define for DW_4 word*/
572 /*define for src_z field*/
573 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_offset 4
574 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_mask 0x000007FF
575 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_shift 0
576 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_SRC_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_shift)
578 /*define for src_pitch field*/
579 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_offset 4
580 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_mask 0x0007FFFF
581 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_shift 13
582 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_SRC_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_shift)
584 /*define for DW_5 word*/
585 /*define for src_slice_pitch field*/
586 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_offset 5
587 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_mask 0x0FFFFFFF
588 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_shift 0
589 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_SRC_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_shift)
591 /*define for DST_ADDR_LO word*/
592 /*define for dst_addr_31_0 field*/
593 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_offset 6
594 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF
595 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_shift 0
596 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_shift)
598 /*define for DST_ADDR_HI word*/
599 /*define for dst_addr_63_32 field*/
600 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_offset 7
601 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF
602 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_shift 0
603 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_shift)
605 /*define for DW_8 word*/
606 /*define for dst_x field*/
607 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_offset 8
608 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_mask 0x00003FFF
609 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_shift 0
610 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_DST_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_shift)
612 /*define for dst_y field*/
613 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_offset 8
614 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_mask 0x00003FFF
615 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_shift 16
616 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_DST_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_shift)
618 /*define for DW_9 word*/
619 /*define for dst_z field*/
620 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_offset 9
621 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_mask 0x000007FF
622 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_shift 0
623 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_DST_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_shift)
625 /*define for dst_pitch field*/
626 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_offset 9
627 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_mask 0x0007FFFF
628 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_shift 13
629 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_DST_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_shift)
631 /*define for DW_10 word*/
632 /*define for dst_slice_pitch field*/
633 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_offset 10
634 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_mask 0x0FFFFFFF
635 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_shift 0
636 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_DST_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_shift)
638 /*define for DW_11 word*/
639 /*define for rect_x field*/
640 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_offset 11
641 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_mask 0x00003FFF
642 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_shift 0
643 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_RECT_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_shift)
645 /*define for rect_y field*/
646 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_offset 11
647 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_mask 0x00003FFF
648 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_shift 16
649 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_RECT_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_shift)
651 /*define for DW_12 word*/
652 /*define for rect_z field*/
653 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_offset 12
654 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_mask 0x000007FF
655 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_shift 0
656 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_RECT_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_shift)
658 /*define for dst_sw field*/
659 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_offset 12
660 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_mask 0x00000003
661 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_shift 16
662 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_DST_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_shift)
664 /*define for src_sw field*/
665 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_offset 12
666 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_mask 0x00000003
667 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_shift 24
668 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_SRC_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_shift)
672 ** Definitions for SDMA_PKT_COPY_TILED packet
675 /*define for HEADER word*/
676 /*define for op field*/
677 #define SDMA_PKT_COPY_TILED_HEADER_op_offset 0
678 #define SDMA_PKT_COPY_TILED_HEADER_op_mask 0x000000FF
679 #define SDMA_PKT_COPY_TILED_HEADER_op_shift 0
680 #define SDMA_PKT_COPY_TILED_HEADER_OP(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_op_mask) << SDMA_PKT_COPY_TILED_HEADER_op_shift)
682 /*define for sub_op field*/
683 #define SDMA_PKT_COPY_TILED_HEADER_sub_op_offset 0
684 #define SDMA_PKT_COPY_TILED_HEADER_sub_op_mask 0x000000FF
685 #define SDMA_PKT_COPY_TILED_HEADER_sub_op_shift 8
686 #define SDMA_PKT_COPY_TILED_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_sub_op_mask) << SDMA_PKT_COPY_TILED_HEADER_sub_op_shift)
688 /*define for encrypt field*/
689 #define SDMA_PKT_COPY_TILED_HEADER_encrypt_offset 0
690 #define SDMA_PKT_COPY_TILED_HEADER_encrypt_mask 0x00000001
691 #define SDMA_PKT_COPY_TILED_HEADER_encrypt_shift 16
692 #define SDMA_PKT_COPY_TILED_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_encrypt_mask) << SDMA_PKT_COPY_TILED_HEADER_encrypt_shift)
694 /*define for tmz field*/
695 #define SDMA_PKT_COPY_TILED_HEADER_tmz_offset 0
696 #define SDMA_PKT_COPY_TILED_HEADER_tmz_mask 0x00000001
697 #define SDMA_PKT_COPY_TILED_HEADER_tmz_shift 18
698 #define SDMA_PKT_COPY_TILED_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_tmz_mask) << SDMA_PKT_COPY_TILED_HEADER_tmz_shift)
700 /*define for mip_max field*/
701 #define SDMA_PKT_COPY_TILED_HEADER_mip_max_offset 0
702 #define SDMA_PKT_COPY_TILED_HEADER_mip_max_mask 0x0000000F
703 #define SDMA_PKT_COPY_TILED_HEADER_mip_max_shift 20
704 #define SDMA_PKT_COPY_TILED_HEADER_MIP_MAX(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_mip_max_mask) << SDMA_PKT_COPY_TILED_HEADER_mip_max_shift)
706 /*define for detile field*/
707 #define SDMA_PKT_COPY_TILED_HEADER_detile_offset 0
708 #define SDMA_PKT_COPY_TILED_HEADER_detile_mask 0x00000001
709 #define SDMA_PKT_COPY_TILED_HEADER_detile_shift 31
710 #define SDMA_PKT_COPY_TILED_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_detile_mask) << SDMA_PKT_COPY_TILED_HEADER_detile_shift)
712 /*define for TILED_ADDR_LO word*/
713 /*define for tiled_addr_31_0 field*/
714 #define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_offset 1
715 #define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_mask 0xFFFFFFFF
716 #define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_shift 0
717 #define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_TILED_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_mask) << SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_shift)
719 /*define for TILED_ADDR_HI word*/
720 /*define for tiled_addr_63_32 field*/
721 #define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_offset 2
722 #define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_mask 0xFFFFFFFF
723 #define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_shift 0
724 #define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_TILED_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_mask) << SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_shift)
726 /*define for DW_3 word*/
727 /*define for width field*/
728 #define SDMA_PKT_COPY_TILED_DW_3_width_offset 3
729 #define SDMA_PKT_COPY_TILED_DW_3_width_mask 0x00003FFF
730 #define SDMA_PKT_COPY_TILED_DW_3_width_shift 0
731 #define SDMA_PKT_COPY_TILED_DW_3_WIDTH(x) (((x) & SDMA_PKT_COPY_TILED_DW_3_width_mask) << SDMA_PKT_COPY_TILED_DW_3_width_shift)
733 /*define for DW_4 word*/
734 /*define for height field*/
735 #define SDMA_PKT_COPY_TILED_DW_4_height_offset 4
736 #define SDMA_PKT_COPY_TILED_DW_4_height_mask 0x00003FFF
737 #define SDMA_PKT_COPY_TILED_DW_4_height_shift 0
738 #define SDMA_PKT_COPY_TILED_DW_4_HEIGHT(x) (((x) & SDMA_PKT_COPY_TILED_DW_4_height_mask) << SDMA_PKT_COPY_TILED_DW_4_height_shift)
740 /*define for depth field*/
741 #define SDMA_PKT_COPY_TILED_DW_4_depth_offset 4
742 #define SDMA_PKT_COPY_TILED_DW_4_depth_mask 0x000007FF
743 #define SDMA_PKT_COPY_TILED_DW_4_depth_shift 16
744 #define SDMA_PKT_COPY_TILED_DW_4_DEPTH(x) (((x) & SDMA_PKT_COPY_TILED_DW_4_depth_mask) << SDMA_PKT_COPY_TILED_DW_4_depth_shift)
746 /*define for DW_5 word*/
747 /*define for element_size field*/
748 #define SDMA_PKT_COPY_TILED_DW_5_element_size_offset 5
749 #define SDMA_PKT_COPY_TILED_DW_5_element_size_mask 0x00000007
750 #define SDMA_PKT_COPY_TILED_DW_5_element_size_shift 0
751 #define SDMA_PKT_COPY_TILED_DW_5_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_element_size_mask) << SDMA_PKT_COPY_TILED_DW_5_element_size_shift)
753 /*define for swizzle_mode field*/
754 #define SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_offset 5
755 #define SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_mask 0x0000001F
756 #define SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_shift 3
757 #define SDMA_PKT_COPY_TILED_DW_5_SWIZZLE_MODE(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_mask) << SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_shift)
759 /*define for dimension field*/
760 #define SDMA_PKT_COPY_TILED_DW_5_dimension_offset 5
761 #define SDMA_PKT_COPY_TILED_DW_5_dimension_mask 0x00000003
762 #define SDMA_PKT_COPY_TILED_DW_5_dimension_shift 9
763 #define SDMA_PKT_COPY_TILED_DW_5_DIMENSION(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_dimension_mask) << SDMA_PKT_COPY_TILED_DW_5_dimension_shift)
765 /*define for epitch field*/
766 #define SDMA_PKT_COPY_TILED_DW_5_epitch_offset 5
767 #define SDMA_PKT_COPY_TILED_DW_5_epitch_mask 0x0000FFFF
768 #define SDMA_PKT_COPY_TILED_DW_5_epitch_shift 16
769 #define SDMA_PKT_COPY_TILED_DW_5_EPITCH(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_epitch_mask) << SDMA_PKT_COPY_TILED_DW_5_epitch_shift)
771 /*define for DW_6 word*/
772 /*define for x field*/
773 #define SDMA_PKT_COPY_TILED_DW_6_x_offset 6
774 #define SDMA_PKT_COPY_TILED_DW_6_x_mask 0x00003FFF
775 #define SDMA_PKT_COPY_TILED_DW_6_x_shift 0
776 #define SDMA_PKT_COPY_TILED_DW_6_X(x) (((x) & SDMA_PKT_COPY_TILED_DW_6_x_mask) << SDMA_PKT_COPY_TILED_DW_6_x_shift)
778 /*define for y field*/
779 #define SDMA_PKT_COPY_TILED_DW_6_y_offset 6
780 #define SDMA_PKT_COPY_TILED_DW_6_y_mask 0x00003FFF
781 #define SDMA_PKT_COPY_TILED_DW_6_y_shift 16
782 #define SDMA_PKT_COPY_TILED_DW_6_Y(x) (((x) & SDMA_PKT_COPY_TILED_DW_6_y_mask) << SDMA_PKT_COPY_TILED_DW_6_y_shift)
784 /*define for DW_7 word*/
785 /*define for z field*/
786 #define SDMA_PKT_COPY_TILED_DW_7_z_offset 7
787 #define SDMA_PKT_COPY_TILED_DW_7_z_mask 0x000007FF
788 #define SDMA_PKT_COPY_TILED_DW_7_z_shift 0
789 #define SDMA_PKT_COPY_TILED_DW_7_Z(x) (((x) & SDMA_PKT_COPY_TILED_DW_7_z_mask) << SDMA_PKT_COPY_TILED_DW_7_z_shift)
791 /*define for linear_sw field*/
792 #define SDMA_PKT_COPY_TILED_DW_7_linear_sw_offset 7
793 #define SDMA_PKT_COPY_TILED_DW_7_linear_sw_mask 0x00000003
794 #define SDMA_PKT_COPY_TILED_DW_7_linear_sw_shift 16
795 #define SDMA_PKT_COPY_TILED_DW_7_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_TILED_DW_7_linear_sw_mask) << SDMA_PKT_COPY_TILED_DW_7_linear_sw_shift)
797 /*define for tile_sw field*/
798 #define SDMA_PKT_COPY_TILED_DW_7_tile_sw_offset 7
799 #define SDMA_PKT_COPY_TILED_DW_7_tile_sw_mask 0x00000003
800 #define SDMA_PKT_COPY_TILED_DW_7_tile_sw_shift 24
801 #define SDMA_PKT_COPY_TILED_DW_7_TILE_SW(x) (((x) & SDMA_PKT_COPY_TILED_DW_7_tile_sw_mask) << SDMA_PKT_COPY_TILED_DW_7_tile_sw_shift)
803 /*define for LINEAR_ADDR_LO word*/
804 /*define for linear_addr_31_0 field*/
805 #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_offset 8
806 #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF
807 #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_shift 0
808 #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_shift)
810 /*define for LINEAR_ADDR_HI word*/
811 /*define for linear_addr_63_32 field*/
812 #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_offset 9
813 #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF
814 #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_shift 0
815 #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_shift)
817 /*define for LINEAR_PITCH word*/
818 /*define for linear_pitch field*/
819 #define SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_offset 10
820 #define SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_mask 0x0007FFFF
821 #define SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_shift 0
822 #define SDMA_PKT_COPY_TILED_LINEAR_PITCH_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_mask) << SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_shift)
824 /*define for LINEAR_SLICE_PITCH word*/
825 /*define for linear_slice_pitch field*/
826 #define SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_offset 11
827 #define SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_mask 0xFFFFFFFF
828 #define SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_shift 0
829 #define SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_LINEAR_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_mask) << SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_shift)
831 /*define for COUNT word*/
832 /*define for count field*/
833 #define SDMA_PKT_COPY_TILED_COUNT_count_offset 12
834 #define SDMA_PKT_COPY_TILED_COUNT_count_mask 0x000FFFFF
835 #define SDMA_PKT_COPY_TILED_COUNT_count_shift 0
836 #define SDMA_PKT_COPY_TILED_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_TILED_COUNT_count_mask) << SDMA_PKT_COPY_TILED_COUNT_count_shift)
840 ** Definitions for SDMA_PKT_COPY_L2T_BROADCAST packet
843 /*define for HEADER word*/
844 /*define for op field*/
845 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_offset 0
846 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_mask 0x000000FF
847 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_shift 0
848 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_OP(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_shift)
850 /*define for sub_op field*/
851 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_offset 0
852 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_mask 0x000000FF
853 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_shift 8
854 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_shift)
856 /*define for encrypt field*/
857 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_offset 0
858 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_mask 0x00000001
859 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_shift 16
860 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_shift)
862 /*define for tmz field*/
863 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_offset 0
864 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_mask 0x00000001
865 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_shift 18
866 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_shift)
868 /*define for mip_max field*/
869 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_mip_max_offset 0
870 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_mip_max_mask 0x0000000F
871 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_mip_max_shift 20
872 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_MIP_MAX(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_mip_max_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_mip_max_shift)
874 /*define for videocopy field*/
875 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_offset 0
876 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_mask 0x00000001
877 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_shift 26
878 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_VIDEOCOPY(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_shift)
880 /*define for broadcast field*/
881 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_offset 0
882 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_mask 0x00000001
883 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_shift 27
884 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_BROADCAST(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_shift)
886 /*define for TILED_ADDR_LO_0 word*/
887 /*define for tiled_addr0_31_0 field*/
888 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_offset 1
889 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_mask 0xFFFFFFFF
890 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_shift 0
891 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_TILED_ADDR0_31_0(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_shift)
893 /*define for TILED_ADDR_HI_0 word*/
894 /*define for tiled_addr0_63_32 field*/
895 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_offset 2
896 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_mask 0xFFFFFFFF
897 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_shift 0
898 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_TILED_ADDR0_63_32(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_shift)
900 /*define for TILED_ADDR_LO_1 word*/
901 /*define for tiled_addr1_31_0 field*/
902 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_offset 3
903 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_mask 0xFFFFFFFF
904 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_shift 0
905 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_TILED_ADDR1_31_0(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_shift)
907 /*define for TILED_ADDR_HI_1 word*/
908 /*define for tiled_addr1_63_32 field*/
909 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_offset 4
910 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_mask 0xFFFFFFFF
911 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_shift 0
912 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_TILED_ADDR1_63_32(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_shift)
914 /*define for DW_5 word*/
915 /*define for width field*/
916 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_offset 5
917 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_mask 0x00003FFF
918 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_shift 0
919 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_WIDTH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_shift)
921 /*define for DW_6 word*/
922 /*define for height field*/
923 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_offset 6
924 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_mask 0x00003FFF
925 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_shift 0
926 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_HEIGHT(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_shift)
928 /*define for depth field*/
929 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_offset 6
930 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_mask 0x000007FF
931 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_shift 16
932 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_DEPTH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_shift)
934 /*define for DW_7 word*/
935 /*define for element_size field*/
936 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_offset 7
937 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_mask 0x00000007
938 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_shift 0
939 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_shift)
941 /*define for swizzle_mode field*/
942 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_offset 7
943 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_mask 0x0000001F
944 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_shift 3
945 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_SWIZZLE_MODE(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_shift)
947 /*define for dimension field*/
948 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_offset 7
949 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_mask 0x00000003
950 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_shift 9
951 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_DIMENSION(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_shift)
953 /*define for epitch field*/
954 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_epitch_offset 7
955 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_epitch_mask 0x0000FFFF
956 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_epitch_shift 16
957 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_EPITCH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_epitch_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_epitch_shift)
959 /*define for DW_8 word*/
960 /*define for x field*/
961 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_offset 8
962 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_mask 0x00003FFF
963 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_shift 0
964 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_X(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_shift)
966 /*define for y field*/
967 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_offset 8
968 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_mask 0x00003FFF
969 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_shift 16
970 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_Y(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_shift)
972 /*define for DW_9 word*/
973 /*define for z field*/
974 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_offset 9
975 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_mask 0x000007FF
976 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_shift 0
977 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_Z(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_shift)
979 /*define for DW_10 word*/
980 /*define for dst2_sw field*/
981 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_offset 10
982 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_mask 0x00000003
983 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_shift 8
984 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_DST2_SW(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_shift)
986 /*define for linear_sw field*/
987 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_offset 10
988 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_mask 0x00000003
989 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_shift 16
990 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_shift)
992 /*define for tile_sw field*/
993 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_offset 10
994 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_mask 0x00000003
995 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_shift 24
996 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_TILE_SW(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_shift)
998 /*define for LINEAR_ADDR_LO word*/
999 /*define for linear_addr_31_0 field*/
1000 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_offset 11
1001 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF
1002 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_shift 0
1003 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_shift)
1005 /*define for LINEAR_ADDR_HI word*/
1006 /*define for linear_addr_63_32 field*/
1007 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_offset 12
1008 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF
1009 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_shift 0
1010 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_shift)
1012 /*define for LINEAR_PITCH word*/
1013 /*define for linear_pitch field*/
1014 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_offset 13
1015 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_mask 0x0007FFFF
1016 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_shift 0
1017 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_shift)
1019 /*define for LINEAR_SLICE_PITCH word*/
1020 /*define for linear_slice_pitch field*/
1021 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_offset 14
1022 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_mask 0xFFFFFFFF
1023 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_shift 0
1024 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_LINEAR_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_shift)
1026 /*define for COUNT word*/
1027 /*define for count field*/
1028 #define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_offset 15
1029 #define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_mask 0x000FFFFF
1030 #define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_shift 0
1031 #define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_mask) << SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_shift)
1035 ** Definitions for SDMA_PKT_COPY_T2T packet
1038 /*define for HEADER word*/
1039 /*define for op field*/
1040 #define SDMA_PKT_COPY_T2T_HEADER_op_offset 0
1041 #define SDMA_PKT_COPY_T2T_HEADER_op_mask 0x000000FF
1042 #define SDMA_PKT_COPY_T2T_HEADER_op_shift 0
1043 #define SDMA_PKT_COPY_T2T_HEADER_OP(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_op_mask) << SDMA_PKT_COPY_T2T_HEADER_op_shift)
1045 /*define for sub_op field*/
1046 #define SDMA_PKT_COPY_T2T_HEADER_sub_op_offset 0
1047 #define SDMA_PKT_COPY_T2T_HEADER_sub_op_mask 0x000000FF
1048 #define SDMA_PKT_COPY_T2T_HEADER_sub_op_shift 8
1049 #define SDMA_PKT_COPY_T2T_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_sub_op_mask) << SDMA_PKT_COPY_T2T_HEADER_sub_op_shift)
1051 /*define for tmz field*/
1052 #define SDMA_PKT_COPY_T2T_HEADER_tmz_offset 0
1053 #define SDMA_PKT_COPY_T2T_HEADER_tmz_mask 0x00000001
1054 #define SDMA_PKT_COPY_T2T_HEADER_tmz_shift 18
1055 #define SDMA_PKT_COPY_T2T_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_tmz_mask) << SDMA_PKT_COPY_T2T_HEADER_tmz_shift)
1057 /*define for mip_max field*/
1058 #define SDMA_PKT_COPY_T2T_HEADER_mip_max_offset 0
1059 #define SDMA_PKT_COPY_T2T_HEADER_mip_max_mask 0x0000000F
1060 #define SDMA_PKT_COPY_T2T_HEADER_mip_max_shift 20
1061 #define SDMA_PKT_COPY_T2T_HEADER_MIP_MAX(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_mip_max_mask) << SDMA_PKT_COPY_T2T_HEADER_mip_max_shift)
1063 /*define for SRC_ADDR_LO word*/
1064 /*define for src_addr_31_0 field*/
1065 #define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_offset 1
1066 #define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF
1067 #define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_shift 0
1068 #define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_shift)
1070 /*define for SRC_ADDR_HI word*/
1071 /*define for src_addr_63_32 field*/
1072 #define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_offset 2
1073 #define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF
1074 #define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_shift 0
1075 #define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_shift)
1077 /*define for DW_3 word*/
1078 /*define for src_x field*/
1079 #define SDMA_PKT_COPY_T2T_DW_3_src_x_offset 3
1080 #define SDMA_PKT_COPY_T2T_DW_3_src_x_mask 0x00003FFF
1081 #define SDMA_PKT_COPY_T2T_DW_3_src_x_shift 0
1082 #define SDMA_PKT_COPY_T2T_DW_3_SRC_X(x) (((x) & SDMA_PKT_COPY_T2T_DW_3_src_x_mask) << SDMA_PKT_COPY_T2T_DW_3_src_x_shift)
1084 /*define for src_y field*/
1085 #define SDMA_PKT_COPY_T2T_DW_3_src_y_offset 3
1086 #define SDMA_PKT_COPY_T2T_DW_3_src_y_mask 0x00003FFF
1087 #define SDMA_PKT_COPY_T2T_DW_3_src_y_shift 16
1088 #define SDMA_PKT_COPY_T2T_DW_3_SRC_Y(x) (((x) & SDMA_PKT_COPY_T2T_DW_3_src_y_mask) << SDMA_PKT_COPY_T2T_DW_3_src_y_shift)
1090 /*define for DW_4 word*/
1091 /*define for src_z field*/
1092 #define SDMA_PKT_COPY_T2T_DW_4_src_z_offset 4
1093 #define SDMA_PKT_COPY_T2T_DW_4_src_z_mask 0x000007FF
1094 #define SDMA_PKT_COPY_T2T_DW_4_src_z_shift 0
1095 #define SDMA_PKT_COPY_T2T_DW_4_SRC_Z(x) (((x) & SDMA_PKT_COPY_T2T_DW_4_src_z_mask) << SDMA_PKT_COPY_T2T_DW_4_src_z_shift)
1097 /*define for src_width field*/
1098 #define SDMA_PKT_COPY_T2T_DW_4_src_width_offset 4
1099 #define SDMA_PKT_COPY_T2T_DW_4_src_width_mask 0x00003FFF
1100 #define SDMA_PKT_COPY_T2T_DW_4_src_width_shift 16
1101 #define SDMA_PKT_COPY_T2T_DW_4_SRC_WIDTH(x) (((x) & SDMA_PKT_COPY_T2T_DW_4_src_width_mask) << SDMA_PKT_COPY_T2T_DW_4_src_width_shift)
1103 /*define for DW_5 word*/
1104 /*define for src_height field*/
1105 #define SDMA_PKT_COPY_T2T_DW_5_src_height_offset 5
1106 #define SDMA_PKT_COPY_T2T_DW_5_src_height_mask 0x00003FFF
1107 #define SDMA_PKT_COPY_T2T_DW_5_src_height_shift 0
1108 #define SDMA_PKT_COPY_T2T_DW_5_SRC_HEIGHT(x) (((x) & SDMA_PKT_COPY_T2T_DW_5_src_height_mask) << SDMA_PKT_COPY_T2T_DW_5_src_height_shift)
1110 /*define for src_depth field*/
1111 #define SDMA_PKT_COPY_T2T_DW_5_src_depth_offset 5
1112 #define SDMA_PKT_COPY_T2T_DW_5_src_depth_mask 0x000007FF
1113 #define SDMA_PKT_COPY_T2T_DW_5_src_depth_shift 16
1114 #define SDMA_PKT_COPY_T2T_DW_5_SRC_DEPTH(x) (((x) & SDMA_PKT_COPY_T2T_DW_5_src_depth_mask) << SDMA_PKT_COPY_T2T_DW_5_src_depth_shift)
1116 /*define for DW_6 word*/
1117 /*define for src_element_size field*/
1118 #define SDMA_PKT_COPY_T2T_DW_6_src_element_size_offset 6
1119 #define SDMA_PKT_COPY_T2T_DW_6_src_element_size_mask 0x00000007
1120 #define SDMA_PKT_COPY_T2T_DW_6_src_element_size_shift 0
1121 #define SDMA_PKT_COPY_T2T_DW_6_SRC_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_element_size_mask) << SDMA_PKT_COPY_T2T_DW_6_src_element_size_shift)
1123 /*define for src_swizzle_mode field*/
1124 #define SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_offset 6
1125 #define SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_mask 0x0000001F
1126 #define SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_shift 3
1127 #define SDMA_PKT_COPY_T2T_DW_6_SRC_SWIZZLE_MODE(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_mask) << SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_shift)
1129 /*define for src_dimension field*/
1130 #define SDMA_PKT_COPY_T2T_DW_6_src_dimension_offset 6
1131 #define SDMA_PKT_COPY_T2T_DW_6_src_dimension_mask 0x00000003
1132 #define SDMA_PKT_COPY_T2T_DW_6_src_dimension_shift 9
1133 #define SDMA_PKT_COPY_T2T_DW_6_SRC_DIMENSION(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_dimension_mask) << SDMA_PKT_COPY_T2T_DW_6_src_dimension_shift)
1135 /*define for src_epitch field*/
1136 #define SDMA_PKT_COPY_T2T_DW_6_src_epitch_offset 6
1137 #define SDMA_PKT_COPY_T2T_DW_6_src_epitch_mask 0x0000FFFF
1138 #define SDMA_PKT_COPY_T2T_DW_6_src_epitch_shift 16
1139 #define SDMA_PKT_COPY_T2T_DW_6_SRC_EPITCH(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_epitch_mask) << SDMA_PKT_COPY_T2T_DW_6_src_epitch_shift)
1141 /*define for DST_ADDR_LO word*/
1142 /*define for dst_addr_31_0 field*/
1143 #define SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_offset 7
1144 #define SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF
1145 #define SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_shift 0
1146 #define SDMA_PKT_COPY_T2T_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_shift)
1148 /*define for DST_ADDR_HI word*/
1149 /*define for dst_addr_63_32 field*/
1150 #define SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_offset 8
1151 #define SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF
1152 #define SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_shift 0
1153 #define SDMA_PKT_COPY_T2T_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_shift)
1155 /*define for DW_9 word*/
1156 /*define for dst_x field*/
1157 #define SDMA_PKT_COPY_T2T_DW_9_dst_x_offset 9
1158 #define SDMA_PKT_COPY_T2T_DW_9_dst_x_mask 0x00003FFF
1159 #define SDMA_PKT_COPY_T2T_DW_9_dst_x_shift 0
1160 #define SDMA_PKT_COPY_T2T_DW_9_DST_X(x) (((x) & SDMA_PKT_COPY_T2T_DW_9_dst_x_mask) << SDMA_PKT_COPY_T2T_DW_9_dst_x_shift)
1162 /*define for dst_y field*/
1163 #define SDMA_PKT_COPY_T2T_DW_9_dst_y_offset 9
1164 #define SDMA_PKT_COPY_T2T_DW_9_dst_y_mask 0x00003FFF
1165 #define SDMA_PKT_COPY_T2T_DW_9_dst_y_shift 16
1166 #define SDMA_PKT_COPY_T2T_DW_9_DST_Y(x) (((x) & SDMA_PKT_COPY_T2T_DW_9_dst_y_mask) << SDMA_PKT_COPY_T2T_DW_9_dst_y_shift)
1168 /*define for DW_10 word*/
1169 /*define for dst_z field*/
1170 #define SDMA_PKT_COPY_T2T_DW_10_dst_z_offset 10
1171 #define SDMA_PKT_COPY_T2T_DW_10_dst_z_mask 0x000007FF
1172 #define SDMA_PKT_COPY_T2T_DW_10_dst_z_shift 0
1173 #define SDMA_PKT_COPY_T2T_DW_10_DST_Z(x) (((x) & SDMA_PKT_COPY_T2T_DW_10_dst_z_mask) << SDMA_PKT_COPY_T2T_DW_10_dst_z_shift)
1175 /*define for dst_width field*/
1176 #define SDMA_PKT_COPY_T2T_DW_10_dst_width_offset 10
1177 #define SDMA_PKT_COPY_T2T_DW_10_dst_width_mask 0x00003FFF
1178 #define SDMA_PKT_COPY_T2T_DW_10_dst_width_shift 16
1179 #define SDMA_PKT_COPY_T2T_DW_10_DST_WIDTH(x) (((x) & SDMA_PKT_COPY_T2T_DW_10_dst_width_mask) << SDMA_PKT_COPY_T2T_DW_10_dst_width_shift)
1181 /*define for DW_11 word*/
1182 /*define for dst_height field*/
1183 #define SDMA_PKT_COPY_T2T_DW_11_dst_height_offset 11
1184 #define SDMA_PKT_COPY_T2T_DW_11_dst_height_mask 0x00003FFF
1185 #define SDMA_PKT_COPY_T2T_DW_11_dst_height_shift 0
1186 #define SDMA_PKT_COPY_T2T_DW_11_DST_HEIGHT(x) (((x) & SDMA_PKT_COPY_T2T_DW_11_dst_height_mask) << SDMA_PKT_COPY_T2T_DW_11_dst_height_shift)
1188 /*define for dst_depth field*/
1189 #define SDMA_PKT_COPY_T2T_DW_11_dst_depth_offset 11
1190 #define SDMA_PKT_COPY_T2T_DW_11_dst_depth_mask 0x000007FF
1191 #define SDMA_PKT_COPY_T2T_DW_11_dst_depth_shift 16
1192 #define SDMA_PKT_COPY_T2T_DW_11_DST_DEPTH(x) (((x) & SDMA_PKT_COPY_T2T_DW_11_dst_depth_mask) << SDMA_PKT_COPY_T2T_DW_11_dst_depth_shift)
1194 /*define for DW_12 word*/
1195 /*define for dst_element_size field*/
1196 #define SDMA_PKT_COPY_T2T_DW_12_dst_element_size_offset 12
1197 #define SDMA_PKT_COPY_T2T_DW_12_dst_element_size_mask 0x00000007
1198 #define SDMA_PKT_COPY_T2T_DW_12_dst_element_size_shift 0
1199 #define SDMA_PKT_COPY_T2T_DW_12_DST_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_element_size_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_element_size_shift)
1201 /*define for dst_swizzle_mode field*/
1202 #define SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_offset 12
1203 #define SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_mask 0x0000001F
1204 #define SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_shift 3
1205 #define SDMA_PKT_COPY_T2T_DW_12_DST_SWIZZLE_MODE(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_shift)
1207 /*define for dst_dimension field*/
1208 #define SDMA_PKT_COPY_T2T_DW_12_dst_dimension_offset 12
1209 #define SDMA_PKT_COPY_T2T_DW_12_dst_dimension_mask 0x00000003
1210 #define SDMA_PKT_COPY_T2T_DW_12_dst_dimension_shift 9
1211 #define SDMA_PKT_COPY_T2T_DW_12_DST_DIMENSION(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_dimension_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_dimension_shift)
1213 /*define for dst_epitch field*/
1214 #define SDMA_PKT_COPY_T2T_DW_12_dst_epitch_offset 12
1215 #define SDMA_PKT_COPY_T2T_DW_12_dst_epitch_mask 0x0000FFFF
1216 #define SDMA_PKT_COPY_T2T_DW_12_dst_epitch_shift 16
1217 #define SDMA_PKT_COPY_T2T_DW_12_DST_EPITCH(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_epitch_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_epitch_shift)
1219 /*define for DW_13 word*/
1220 /*define for rect_x field*/
1221 #define SDMA_PKT_COPY_T2T_DW_13_rect_x_offset 13
1222 #define SDMA_PKT_COPY_T2T_DW_13_rect_x_mask 0x00003FFF
1223 #define SDMA_PKT_COPY_T2T_DW_13_rect_x_shift 0
1224 #define SDMA_PKT_COPY_T2T_DW_13_RECT_X(x) (((x) & SDMA_PKT_COPY_T2T_DW_13_rect_x_mask) << SDMA_PKT_COPY_T2T_DW_13_rect_x_shift)
1226 /*define for rect_y field*/
1227 #define SDMA_PKT_COPY_T2T_DW_13_rect_y_offset 13
1228 #define SDMA_PKT_COPY_T2T_DW_13_rect_y_mask 0x00003FFF
1229 #define SDMA_PKT_COPY_T2T_DW_13_rect_y_shift 16
1230 #define SDMA_PKT_COPY_T2T_DW_13_RECT_Y(x) (((x) & SDMA_PKT_COPY_T2T_DW_13_rect_y_mask) << SDMA_PKT_COPY_T2T_DW_13_rect_y_shift)
1232 /*define for DW_14 word*/
1233 /*define for rect_z field*/
1234 #define SDMA_PKT_COPY_T2T_DW_14_rect_z_offset 14
1235 #define SDMA_PKT_COPY_T2T_DW_14_rect_z_mask 0x000007FF
1236 #define SDMA_PKT_COPY_T2T_DW_14_rect_z_shift 0
1237 #define SDMA_PKT_COPY_T2T_DW_14_RECT_Z(x) (((x) & SDMA_PKT_COPY_T2T_DW_14_rect_z_mask) << SDMA_PKT_COPY_T2T_DW_14_rect_z_shift)
1239 /*define for dst_sw field*/
1240 #define SDMA_PKT_COPY_T2T_DW_14_dst_sw_offset 14
1241 #define SDMA_PKT_COPY_T2T_DW_14_dst_sw_mask 0x00000003
1242 #define SDMA_PKT_COPY_T2T_DW_14_dst_sw_shift 16
1243 #define SDMA_PKT_COPY_T2T_DW_14_DST_SW(x) (((x) & SDMA_PKT_COPY_T2T_DW_14_dst_sw_mask) << SDMA_PKT_COPY_T2T_DW_14_dst_sw_shift)
1245 /*define for src_sw field*/
1246 #define SDMA_PKT_COPY_T2T_DW_14_src_sw_offset 14
1247 #define SDMA_PKT_COPY_T2T_DW_14_src_sw_mask 0x00000003
1248 #define SDMA_PKT_COPY_T2T_DW_14_src_sw_shift 24
1249 #define SDMA_PKT_COPY_T2T_DW_14_SRC_SW(x) (((x) & SDMA_PKT_COPY_T2T_DW_14_src_sw_mask) << SDMA_PKT_COPY_T2T_DW_14_src_sw_shift)
1253 ** Definitions for SDMA_PKT_COPY_TILED_SUBWIN packet
1256 /*define for HEADER word*/
1257 /*define for op field*/
1258 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_offset 0
1259 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_mask 0x000000FF
1260 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_shift 0
1261 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_OP(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_shift)
1263 /*define for sub_op field*/
1264 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_offset 0
1265 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_mask 0x000000FF
1266 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_shift 8
1267 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_shift)
1269 /*define for tmz field*/
1270 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_offset 0
1271 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_mask 0x00000001
1272 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_shift 18
1273 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_shift)
1275 /*define for mip_max field*/
1276 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_max_offset 0
1277 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_max_mask 0x0000000F
1278 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_max_shift 20
1279 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_MIP_MAX(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_max_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_max_shift)
1281 /*define for mip_id field*/
1282 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_id_offset 0
1283 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_id_mask 0x0000000F
1284 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_id_shift 24
1285 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_MIP_ID(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_id_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_id_shift)
1287 /*define for detile field*/
1288 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_offset 0
1289 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_mask 0x00000001
1290 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_shift 31
1291 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_shift)
1293 /*define for TILED_ADDR_LO word*/
1294 /*define for tiled_addr_31_0 field*/
1295 #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_offset 1
1296 #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_mask 0xFFFFFFFF
1297 #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_shift 0
1298 #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_TILED_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_shift)
1300 /*define for TILED_ADDR_HI word*/
1301 /*define for tiled_addr_63_32 field*/
1302 #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_offset 2
1303 #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_mask 0xFFFFFFFF
1304 #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_shift 0
1305 #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_TILED_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_shift)
1307 /*define for DW_3 word*/
1308 /*define for tiled_x field*/
1309 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_offset 3
1310 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_mask 0x00003FFF
1311 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_shift 0
1312 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_TILED_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_shift)
1314 /*define for tiled_y field*/
1315 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_offset 3
1316 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_mask 0x00003FFF
1317 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_shift 16
1318 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_TILED_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_shift)
1320 /*define for DW_4 word*/
1321 /*define for tiled_z field*/
1322 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_offset 4
1323 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_mask 0x000007FF
1324 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_shift 0
1325 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_TILED_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_shift)
1327 /*define for width field*/
1328 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_offset 4
1329 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_mask 0x00003FFF
1330 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_shift 16
1331 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_WIDTH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_shift)
1333 /*define for DW_5 word*/
1334 /*define for height field*/
1335 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_offset 5
1336 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_mask 0x00003FFF
1337 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_shift 0
1338 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_HEIGHT(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_shift)
1340 /*define for depth field*/
1341 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_offset 5
1342 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_mask 0x000007FF
1343 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_shift 16
1344 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_DEPTH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_shift)
1346 /*define for DW_6 word*/
1347 /*define for element_size field*/
1348 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_offset 6
1349 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_mask 0x00000007
1350 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_shift 0
1351 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_shift)
1353 /*define for swizzle_mode field*/
1354 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_offset 6
1355 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_mask 0x0000001F
1356 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_shift 3
1357 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_SWIZZLE_MODE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_shift)
1359 /*define for dimension field*/
1360 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_offset 6
1361 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_mask 0x00000003
1362 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_shift 9
1363 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_DIMENSION(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_shift)
1365 /*define for epitch field*/
1366 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_epitch_offset 6
1367 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_epitch_mask 0x0000FFFF
1368 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_epitch_shift 16
1369 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_EPITCH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_epitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_epitch_shift)
1371 /*define for LINEAR_ADDR_LO word*/
1372 /*define for linear_addr_31_0 field*/
1373 #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_offset 7
1374 #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF
1375 #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_shift 0
1376 #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_shift)
1378 /*define for LINEAR_ADDR_HI word*/
1379 /*define for linear_addr_63_32 field*/
1380 #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_offset 8
1381 #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF
1382 #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_shift 0
1383 #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_shift)
1385 /*define for DW_9 word*/
1386 /*define for linear_x field*/
1387 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_offset 9
1388 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_mask 0x00003FFF
1389 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_shift 0
1390 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_LINEAR_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_shift)
1392 /*define for linear_y field*/
1393 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_offset 9
1394 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_mask 0x00003FFF
1395 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_shift 16
1396 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_LINEAR_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_shift)
1398 /*define for DW_10 word*/
1399 /*define for linear_z field*/
1400 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_offset 10
1401 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_mask 0x000007FF
1402 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_shift 0
1403 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_LINEAR_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_shift)
1405 /*define for linear_pitch field*/
1406 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_offset 10
1407 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_mask 0x00003FFF
1408 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_shift 16
1409 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_shift)
1411 /*define for DW_11 word*/
1412 /*define for linear_slice_pitch field*/
1413 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_offset 11
1414 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_mask 0x0FFFFFFF
1415 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_shift 0
1416 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_LINEAR_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_shift)
1418 /*define for DW_12 word*/
1419 /*define for rect_x field*/
1420 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_offset 12
1421 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_mask 0x00003FFF
1422 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_shift 0
1423 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_RECT_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_shift)
1425 /*define for rect_y field*/
1426 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_offset 12
1427 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_mask 0x00003FFF
1428 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_shift 16
1429 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_RECT_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_shift)
1431 /*define for DW_13 word*/
1432 /*define for rect_z field*/
1433 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_offset 13
1434 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_mask 0x000007FF
1435 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_shift 0
1436 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_RECT_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_shift)
1438 /*define for linear_sw field*/
1439 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_offset 13
1440 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_mask 0x00000003
1441 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_shift 16
1442 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_shift)
1444 /*define for tile_sw field*/
1445 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_offset 13
1446 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_mask 0x00000003
1447 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_shift 24
1448 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_TILE_SW(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_shift)
1452 ** Definitions for SDMA_PKT_COPY_STRUCT packet
1455 /*define for HEADER word*/
1456 /*define for op field*/
1457 #define SDMA_PKT_COPY_STRUCT_HEADER_op_offset 0
1458 #define SDMA_PKT_COPY_STRUCT_HEADER_op_mask 0x000000FF
1459 #define SDMA_PKT_COPY_STRUCT_HEADER_op_shift 0
1460 #define SDMA_PKT_COPY_STRUCT_HEADER_OP(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_op_mask) << SDMA_PKT_COPY_STRUCT_HEADER_op_shift)
1462 /*define for sub_op field*/
1463 #define SDMA_PKT_COPY_STRUCT_HEADER_sub_op_offset 0
1464 #define SDMA_PKT_COPY_STRUCT_HEADER_sub_op_mask 0x000000FF
1465 #define SDMA_PKT_COPY_STRUCT_HEADER_sub_op_shift 8
1466 #define SDMA_PKT_COPY_STRUCT_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_sub_op_mask) << SDMA_PKT_COPY_STRUCT_HEADER_sub_op_shift)
1468 /*define for tmz field*/
1469 #define SDMA_PKT_COPY_STRUCT_HEADER_tmz_offset 0
1470 #define SDMA_PKT_COPY_STRUCT_HEADER_tmz_mask 0x00000001
1471 #define SDMA_PKT_COPY_STRUCT_HEADER_tmz_shift 18
1472 #define SDMA_PKT_COPY_STRUCT_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_tmz_mask) << SDMA_PKT_COPY_STRUCT_HEADER_tmz_shift)
1474 /*define for detile field*/
1475 #define SDMA_PKT_COPY_STRUCT_HEADER_detile_offset 0
1476 #define SDMA_PKT_COPY_STRUCT_HEADER_detile_mask 0x00000001
1477 #define SDMA_PKT_COPY_STRUCT_HEADER_detile_shift 31
1478 #define SDMA_PKT_COPY_STRUCT_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_detile_mask) << SDMA_PKT_COPY_STRUCT_HEADER_detile_shift)
1480 /*define for SB_ADDR_LO word*/
1481 /*define for sb_addr_31_0 field*/
1482 #define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_offset 1
1483 #define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_mask 0xFFFFFFFF
1484 #define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_shift 0
1485 #define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_SB_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_mask) << SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_shift)
1487 /*define for SB_ADDR_HI word*/
1488 /*define for sb_addr_63_32 field*/
1489 #define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_offset 2
1490 #define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_mask 0xFFFFFFFF
1491 #define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_shift 0
1492 #define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_SB_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_mask) << SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_shift)
1494 /*define for START_INDEX word*/
1495 /*define for start_index field*/
1496 #define SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_offset 3
1497 #define SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_mask 0xFFFFFFFF
1498 #define SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_shift 0
1499 #define SDMA_PKT_COPY_STRUCT_START_INDEX_START_INDEX(x) (((x) & SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_mask) << SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_shift)
1501 /*define for COUNT word*/
1502 /*define for count field*/
1503 #define SDMA_PKT_COPY_STRUCT_COUNT_count_offset 4
1504 #define SDMA_PKT_COPY_STRUCT_COUNT_count_mask 0xFFFFFFFF
1505 #define SDMA_PKT_COPY_STRUCT_COUNT_count_shift 0
1506 #define SDMA_PKT_COPY_STRUCT_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_STRUCT_COUNT_count_mask) << SDMA_PKT_COPY_STRUCT_COUNT_count_shift)
1508 /*define for DW_5 word*/
1509 /*define for stride field*/
1510 #define SDMA_PKT_COPY_STRUCT_DW_5_stride_offset 5
1511 #define SDMA_PKT_COPY_STRUCT_DW_5_stride_mask 0x000007FF
1512 #define SDMA_PKT_COPY_STRUCT_DW_5_stride_shift 0
1513 #define SDMA_PKT_COPY_STRUCT_DW_5_STRIDE(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_stride_mask) << SDMA_PKT_COPY_STRUCT_DW_5_stride_shift)
1515 /*define for linear_sw field*/
1516 #define SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_offset 5
1517 #define SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_mask 0x00000003
1518 #define SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_shift 16
1519 #define SDMA_PKT_COPY_STRUCT_DW_5_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_mask) << SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_shift)
1521 /*define for struct_sw field*/
1522 #define SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_offset 5
1523 #define SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_mask 0x00000003
1524 #define SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_shift 24
1525 #define SDMA_PKT_COPY_STRUCT_DW_5_STRUCT_SW(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_mask) << SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_shift)
1527 /*define for LINEAR_ADDR_LO word*/
1528 /*define for linear_addr_31_0 field*/
1529 #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_offset 6
1530 #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF
1531 #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_shift 0
1532 #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_shift)
1534 /*define for LINEAR_ADDR_HI word*/
1535 /*define for linear_addr_63_32 field*/
1536 #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_offset 7
1537 #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF
1538 #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_shift 0
1539 #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_shift)
1543 ** Definitions for SDMA_PKT_WRITE_UNTILED packet
1546 /*define for HEADER word*/
1547 /*define for op field*/
1548 #define SDMA_PKT_WRITE_UNTILED_HEADER_op_offset 0
1549 #define SDMA_PKT_WRITE_UNTILED_HEADER_op_mask 0x000000FF
1550 #define SDMA_PKT_WRITE_UNTILED_HEADER_op_shift 0
1551 #define SDMA_PKT_WRITE_UNTILED_HEADER_OP(x) (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_op_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_op_shift)
1553 /*define for sub_op field*/
1554 #define SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_offset 0
1555 #define SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_mask 0x000000FF
1556 #define SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_shift 8
1557 #define SDMA_PKT_WRITE_UNTILED_HEADER_SUB_OP(x) (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_shift)
1559 /*define for encrypt field*/
1560 #define SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_offset 0
1561 #define SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_mask 0x00000001
1562 #define SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_shift 16
1563 #define SDMA_PKT_WRITE_UNTILED_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_shift)
1565 /*define for tmz field*/
1566 #define SDMA_PKT_WRITE_UNTILED_HEADER_tmz_offset 0
1567 #define SDMA_PKT_WRITE_UNTILED_HEADER_tmz_mask 0x00000001
1568 #define SDMA_PKT_WRITE_UNTILED_HEADER_tmz_shift 18
1569 #define SDMA_PKT_WRITE_UNTILED_HEADER_TMZ(x) (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_tmz_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_tmz_shift)
1571 /*define for DST_ADDR_LO word*/
1572 /*define for dst_addr_31_0 field*/
1573 #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_offset 1
1574 #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF
1575 #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_shift 0
1576 #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_shift)
1578 /*define for DST_ADDR_HI word*/
1579 /*define for dst_addr_63_32 field*/
1580 #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_offset 2
1581 #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF
1582 #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_shift 0
1583 #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_shift)
1585 /*define for DW_3 word*/
1586 /*define for count field*/
1587 #define SDMA_PKT_WRITE_UNTILED_DW_3_count_offset 3
1588 #define SDMA_PKT_WRITE_UNTILED_DW_3_count_mask 0x000FFFFF
1589 #define SDMA_PKT_WRITE_UNTILED_DW_3_count_shift 0
1590 #define SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(x) (((x) & SDMA_PKT_WRITE_UNTILED_DW_3_count_mask) << SDMA_PKT_WRITE_UNTILED_DW_3_count_shift)
1592 /*define for sw field*/
1593 #define SDMA_PKT_WRITE_UNTILED_DW_3_sw_offset 3
1594 #define SDMA_PKT_WRITE_UNTILED_DW_3_sw_mask 0x00000003
1595 #define SDMA_PKT_WRITE_UNTILED_DW_3_sw_shift 24
1596 #define SDMA_PKT_WRITE_UNTILED_DW_3_SW(x) (((x) & SDMA_PKT_WRITE_UNTILED_DW_3_sw_mask) << SDMA_PKT_WRITE_UNTILED_DW_3_sw_shift)
1598 /*define for DATA0 word*/
1599 /*define for data0 field*/
1600 #define SDMA_PKT_WRITE_UNTILED_DATA0_data0_offset 4
1601 #define SDMA_PKT_WRITE_UNTILED_DATA0_data0_mask 0xFFFFFFFF
1602 #define SDMA_PKT_WRITE_UNTILED_DATA0_data0_shift 0
1603 #define SDMA_PKT_WRITE_UNTILED_DATA0_DATA0(x) (((x) & SDMA_PKT_WRITE_UNTILED_DATA0_data0_mask) << SDMA_PKT_WRITE_UNTILED_DATA0_data0_shift)
1607 ** Definitions for SDMA_PKT_WRITE_TILED packet
1610 /*define for HEADER word*/
1611 /*define for op field*/
1612 #define SDMA_PKT_WRITE_TILED_HEADER_op_offset 0
1613 #define SDMA_PKT_WRITE_TILED_HEADER_op_mask 0x000000FF
1614 #define SDMA_PKT_WRITE_TILED_HEADER_op_shift 0
1615 #define SDMA_PKT_WRITE_TILED_HEADER_OP(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_op_mask) << SDMA_PKT_WRITE_TILED_HEADER_op_shift)
1617 /*define for sub_op field*/
1618 #define SDMA_PKT_WRITE_TILED_HEADER_sub_op_offset 0
1619 #define SDMA_PKT_WRITE_TILED_HEADER_sub_op_mask 0x000000FF
1620 #define SDMA_PKT_WRITE_TILED_HEADER_sub_op_shift 8
1621 #define SDMA_PKT_WRITE_TILED_HEADER_SUB_OP(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_sub_op_mask) << SDMA_PKT_WRITE_TILED_HEADER_sub_op_shift)
1623 /*define for encrypt field*/
1624 #define SDMA_PKT_WRITE_TILED_HEADER_encrypt_offset 0
1625 #define SDMA_PKT_WRITE_TILED_HEADER_encrypt_mask 0x00000001
1626 #define SDMA_PKT_WRITE_TILED_HEADER_encrypt_shift 16
1627 #define SDMA_PKT_WRITE_TILED_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_encrypt_mask) << SDMA_PKT_WRITE_TILED_HEADER_encrypt_shift)
1629 /*define for tmz field*/
1630 #define SDMA_PKT_WRITE_TILED_HEADER_tmz_offset 0
1631 #define SDMA_PKT_WRITE_TILED_HEADER_tmz_mask 0x00000001
1632 #define SDMA_PKT_WRITE_TILED_HEADER_tmz_shift 18
1633 #define SDMA_PKT_WRITE_TILED_HEADER_TMZ(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_tmz_mask) << SDMA_PKT_WRITE_TILED_HEADER_tmz_shift)
1635 /*define for mip_max field*/
1636 #define SDMA_PKT_WRITE_TILED_HEADER_mip_max_offset 0
1637 #define SDMA_PKT_WRITE_TILED_HEADER_mip_max_mask 0x0000000F
1638 #define SDMA_PKT_WRITE_TILED_HEADER_mip_max_shift 20
1639 #define SDMA_PKT_WRITE_TILED_HEADER_MIP_MAX(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_mip_max_mask) << SDMA_PKT_WRITE_TILED_HEADER_mip_max_shift)
1641 /*define for DST_ADDR_LO word*/
1642 /*define for dst_addr_31_0 field*/
1643 #define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_offset 1
1644 #define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF
1645 #define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_shift 0
1646 #define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_shift)
1648 /*define for DST_ADDR_HI word*/
1649 /*define for dst_addr_63_32 field*/
1650 #define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_offset 2
1651 #define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF
1652 #define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_shift 0
1653 #define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_shift)
1655 /*define for DW_3 word*/
1656 /*define for width field*/
1657 #define SDMA_PKT_WRITE_TILED_DW_3_width_offset 3
1658 #define SDMA_PKT_WRITE_TILED_DW_3_width_mask 0x00003FFF
1659 #define SDMA_PKT_WRITE_TILED_DW_3_width_shift 0
1660 #define SDMA_PKT_WRITE_TILED_DW_3_WIDTH(x) (((x) & SDMA_PKT_WRITE_TILED_DW_3_width_mask) << SDMA_PKT_WRITE_TILED_DW_3_width_shift)
1662 /*define for DW_4 word*/
1663 /*define for height field*/
1664 #define SDMA_PKT_WRITE_TILED_DW_4_height_offset 4
1665 #define SDMA_PKT_WRITE_TILED_DW_4_height_mask 0x00003FFF
1666 #define SDMA_PKT_WRITE_TILED_DW_4_height_shift 0
1667 #define SDMA_PKT_WRITE_TILED_DW_4_HEIGHT(x) (((x) & SDMA_PKT_WRITE_TILED_DW_4_height_mask) << SDMA_PKT_WRITE_TILED_DW_4_height_shift)
1669 /*define for depth field*/
1670 #define SDMA_PKT_WRITE_TILED_DW_4_depth_offset 4
1671 #define SDMA_PKT_WRITE_TILED_DW_4_depth_mask 0x000007FF
1672 #define SDMA_PKT_WRITE_TILED_DW_4_depth_shift 16
1673 #define SDMA_PKT_WRITE_TILED_DW_4_DEPTH(x) (((x) & SDMA_PKT_WRITE_TILED_DW_4_depth_mask) << SDMA_PKT_WRITE_TILED_DW_4_depth_shift)
1675 /*define for DW_5 word*/
1676 /*define for element_size field*/
1677 #define SDMA_PKT_WRITE_TILED_DW_5_element_size_offset 5
1678 #define SDMA_PKT_WRITE_TILED_DW_5_element_size_mask 0x00000007
1679 #define SDMA_PKT_WRITE_TILED_DW_5_element_size_shift 0
1680 #define SDMA_PKT_WRITE_TILED_DW_5_ELEMENT_SIZE(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_element_size_mask) << SDMA_PKT_WRITE_TILED_DW_5_element_size_shift)
1682 /*define for swizzle_mode field*/
1683 #define SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_offset 5
1684 #define SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_mask 0x0000001F
1685 #define SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_shift 3
1686 #define SDMA_PKT_WRITE_TILED_DW_5_SWIZZLE_MODE(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_mask) << SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_shift)
1688 /*define for dimension field*/
1689 #define SDMA_PKT_WRITE_TILED_DW_5_dimension_offset 5
1690 #define SDMA_PKT_WRITE_TILED_DW_5_dimension_mask 0x00000003
1691 #define SDMA_PKT_WRITE_TILED_DW_5_dimension_shift 9
1692 #define SDMA_PKT_WRITE_TILED_DW_5_DIMENSION(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_dimension_mask) << SDMA_PKT_WRITE_TILED_DW_5_dimension_shift)
1694 /*define for epitch field*/
1695 #define SDMA_PKT_WRITE_TILED_DW_5_epitch_offset 5
1696 #define SDMA_PKT_WRITE_TILED_DW_5_epitch_mask 0x0000FFFF
1697 #define SDMA_PKT_WRITE_TILED_DW_5_epitch_shift 16
1698 #define SDMA_PKT_WRITE_TILED_DW_5_EPITCH(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_epitch_mask) << SDMA_PKT_WRITE_TILED_DW_5_epitch_shift)
1700 /*define for DW_6 word*/
1701 /*define for x field*/
1702 #define SDMA_PKT_WRITE_TILED_DW_6_x_offset 6
1703 #define SDMA_PKT_WRITE_TILED_DW_6_x_mask 0x00003FFF
1704 #define SDMA_PKT_WRITE_TILED_DW_6_x_shift 0
1705 #define SDMA_PKT_WRITE_TILED_DW_6_X(x) (((x) & SDMA_PKT_WRITE_TILED_DW_6_x_mask) << SDMA_PKT_WRITE_TILED_DW_6_x_shift)
1707 /*define for y field*/
1708 #define SDMA_PKT_WRITE_TILED_DW_6_y_offset 6
1709 #define SDMA_PKT_WRITE_TILED_DW_6_y_mask 0x00003FFF
1710 #define SDMA_PKT_WRITE_TILED_DW_6_y_shift 16
1711 #define SDMA_PKT_WRITE_TILED_DW_6_Y(x) (((x) & SDMA_PKT_WRITE_TILED_DW_6_y_mask) << SDMA_PKT_WRITE_TILED_DW_6_y_shift)
1713 /*define for DW_7 word*/
1714 /*define for z field*/
1715 #define SDMA_PKT_WRITE_TILED_DW_7_z_offset 7
1716 #define SDMA_PKT_WRITE_TILED_DW_7_z_mask 0x000007FF
1717 #define SDMA_PKT_WRITE_TILED_DW_7_z_shift 0
1718 #define SDMA_PKT_WRITE_TILED_DW_7_Z(x) (((x) & SDMA_PKT_WRITE_TILED_DW_7_z_mask) << SDMA_PKT_WRITE_TILED_DW_7_z_shift)
1720 /*define for sw field*/
1721 #define SDMA_PKT_WRITE_TILED_DW_7_sw_offset 7
1722 #define SDMA_PKT_WRITE_TILED_DW_7_sw_mask 0x00000003
1723 #define SDMA_PKT_WRITE_TILED_DW_7_sw_shift 24
1724 #define SDMA_PKT_WRITE_TILED_DW_7_SW(x) (((x) & SDMA_PKT_WRITE_TILED_DW_7_sw_mask) << SDMA_PKT_WRITE_TILED_DW_7_sw_shift)
1726 /*define for COUNT word*/
1727 /*define for count field*/
1728 #define SDMA_PKT_WRITE_TILED_COUNT_count_offset 8
1729 #define SDMA_PKT_WRITE_TILED_COUNT_count_mask 0x000FFFFF
1730 #define SDMA_PKT_WRITE_TILED_COUNT_count_shift 0
1731 #define SDMA_PKT_WRITE_TILED_COUNT_COUNT(x) (((x) & SDMA_PKT_WRITE_TILED_COUNT_count_mask) << SDMA_PKT_WRITE_TILED_COUNT_count_shift)
1733 /*define for DATA0 word*/
1734 /*define for data0 field*/
1735 #define SDMA_PKT_WRITE_TILED_DATA0_data0_offset 9
1736 #define SDMA_PKT_WRITE_TILED_DATA0_data0_mask 0xFFFFFFFF
1737 #define SDMA_PKT_WRITE_TILED_DATA0_data0_shift 0
1738 #define SDMA_PKT_WRITE_TILED_DATA0_DATA0(x) (((x) & SDMA_PKT_WRITE_TILED_DATA0_data0_mask) << SDMA_PKT_WRITE_TILED_DATA0_data0_shift)
1742 ** Definitions for SDMA_PKT_PTEPDE_COPY packet
1745 /*define for HEADER word*/
1746 /*define for op field*/
1747 #define SDMA_PKT_PTEPDE_COPY_HEADER_op_offset 0
1748 #define SDMA_PKT_PTEPDE_COPY_HEADER_op_mask 0x000000FF
1749 #define SDMA_PKT_PTEPDE_COPY_HEADER_op_shift 0
1750 #define SDMA_PKT_PTEPDE_COPY_HEADER_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_HEADER_op_mask) << SDMA_PKT_PTEPDE_COPY_HEADER_op_shift)
1752 /*define for sub_op field*/
1753 #define SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_offset 0
1754 #define SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_mask 0x000000FF
1755 #define SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_shift 8
1756 #define SDMA_PKT_PTEPDE_COPY_HEADER_SUB_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_mask) << SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_shift)
1758 /*define for ptepde_op field*/
1759 #define SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_offset 0
1760 #define SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_mask 0x00000001
1761 #define SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_shift 31
1762 #define SDMA_PKT_PTEPDE_COPY_HEADER_PTEPDE_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_mask) << SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_shift)
1764 /*define for SRC_ADDR_LO word*/
1765 /*define for src_addr_31_0 field*/
1766 #define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_offset 1
1767 #define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF
1768 #define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_shift 0
1769 #define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_shift)
1771 /*define for SRC_ADDR_HI word*/
1772 /*define for src_addr_63_32 field*/
1773 #define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_offset 2
1774 #define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF
1775 #define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_shift 0
1776 #define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_shift)
1778 /*define for DST_ADDR_LO word*/
1779 /*define for dst_addr_31_0 field*/
1780 #define SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_offset 3
1781 #define SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF
1782 #define SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_shift 0
1783 #define SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_shift)
1785 /*define for DST_ADDR_HI word*/
1786 /*define for dst_addr_63_32 field*/
1787 #define SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_offset 4
1788 #define SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF
1789 #define SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_shift 0
1790 #define SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_shift)
1792 /*define for MASK_DW0 word*/
1793 /*define for mask_dw0 field*/
1794 #define SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_offset 5
1795 #define SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_mask 0xFFFFFFFF
1796 #define SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_shift 0
1797 #define SDMA_PKT_PTEPDE_COPY_MASK_DW0_MASK_DW0(x) (((x) & SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_mask) << SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_shift)
1799 /*define for MASK_DW1 word*/
1800 /*define for mask_dw1 field*/
1801 #define SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_offset 6
1802 #define SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_mask 0xFFFFFFFF
1803 #define SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_shift 0
1804 #define SDMA_PKT_PTEPDE_COPY_MASK_DW1_MASK_DW1(x) (((x) & SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_mask) << SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_shift)
1806 /*define for COUNT word*/
1807 /*define for count field*/
1808 #define SDMA_PKT_PTEPDE_COPY_COUNT_count_offset 7
1809 #define SDMA_PKT_PTEPDE_COPY_COUNT_count_mask 0x0007FFFF
1810 #define SDMA_PKT_PTEPDE_COPY_COUNT_count_shift 0
1811 #define SDMA_PKT_PTEPDE_COPY_COUNT_COUNT(x) (((x) & SDMA_PKT_PTEPDE_COPY_COUNT_count_mask) << SDMA_PKT_PTEPDE_COPY_COUNT_count_shift)
1815 ** Definitions for SDMA_PKT_PTEPDE_COPY_BACKWARDS packet
1818 /*define for HEADER word*/
1819 /*define for op field*/
1820 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_offset 0
1821 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_mask 0x000000FF
1822 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_shift 0
1823 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_shift)
1825 /*define for sub_op field*/
1826 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_offset 0
1827 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_mask 0x000000FF
1828 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_shift 8
1829 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_SUB_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_shift)
1831 /*define for pte_size field*/
1832 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_offset 0
1833 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_mask 0x00000003
1834 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_shift 28
1835 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_PTE_SIZE(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_shift)
1837 /*define for direction field*/
1838 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_offset 0
1839 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_mask 0x00000001
1840 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_shift 30
1841 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_DIRECTION(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_shift)
1843 /*define for ptepde_op field*/
1844 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_offset 0
1845 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_mask 0x00000001
1846 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_shift 31
1847 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_PTEPDE_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_shift)
1849 /*define for SRC_ADDR_LO word*/
1850 /*define for src_addr_31_0 field*/
1851 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_offset 1
1852 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF
1853 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_shift 0
1854 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_shift)
1856 /*define for SRC_ADDR_HI word*/
1857 /*define for src_addr_63_32 field*/
1858 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_offset 2
1859 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF
1860 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_shift 0
1861 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_shift)
1863 /*define for DST_ADDR_LO word*/
1864 /*define for dst_addr_31_0 field*/
1865 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_offset 3
1866 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF
1867 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_shift 0
1868 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_shift)
1870 /*define for DST_ADDR_HI word*/
1871 /*define for dst_addr_63_32 field*/
1872 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_offset 4
1873 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF
1874 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_shift 0
1875 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_shift)
1877 /*define for MASK_BIT_FOR_DW word*/
1878 /*define for mask_first_xfer field*/
1879 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_offset 5
1880 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_mask 0x000000FF
1881 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_shift 0
1882 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_MASK_FIRST_XFER(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_shift)
1884 /*define for mask_last_xfer field*/
1885 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_offset 5
1886 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_mask 0x000000FF
1887 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_shift 8
1888 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_MASK_LAST_XFER(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_shift)
1890 /*define for COUNT_IN_32B_XFER word*/
1891 /*define for count field*/
1892 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_offset 6
1893 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_mask 0x0001FFFF
1894 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_shift 0
1895 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_COUNT(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_shift)
1899 ** Definitions for SDMA_PKT_PTEPDE_RMW packet
1902 /*define for HEADER word*/
1903 /*define for op field*/
1904 #define SDMA_PKT_PTEPDE_RMW_HEADER_op_offset 0
1905 #define SDMA_PKT_PTEPDE_RMW_HEADER_op_mask 0x000000FF
1906 #define SDMA_PKT_PTEPDE_RMW_HEADER_op_shift 0
1907 #define SDMA_PKT_PTEPDE_RMW_HEADER_OP(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_op_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_op_shift)
1909 /*define for sub_op field*/
1910 #define SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_offset 0
1911 #define SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_mask 0x000000FF
1912 #define SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_shift 8
1913 #define SDMA_PKT_PTEPDE_RMW_HEADER_SUB_OP(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_shift)
1915 /*define for gcc field*/
1916 #define SDMA_PKT_PTEPDE_RMW_HEADER_gcc_offset 0
1917 #define SDMA_PKT_PTEPDE_RMW_HEADER_gcc_mask 0x00000001
1918 #define SDMA_PKT_PTEPDE_RMW_HEADER_gcc_shift 19
1919 #define SDMA_PKT_PTEPDE_RMW_HEADER_GCC(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_gcc_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_gcc_shift)
1921 /*define for sys field*/
1922 #define SDMA_PKT_PTEPDE_RMW_HEADER_sys_offset 0
1923 #define SDMA_PKT_PTEPDE_RMW_HEADER_sys_mask 0x00000001
1924 #define SDMA_PKT_PTEPDE_RMW_HEADER_sys_shift 20
1925 #define SDMA_PKT_PTEPDE_RMW_HEADER_SYS(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_sys_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_sys_shift)
1927 /*define for snp field*/
1928 #define SDMA_PKT_PTEPDE_RMW_HEADER_snp_offset 0
1929 #define SDMA_PKT_PTEPDE_RMW_HEADER_snp_mask 0x00000001
1930 #define SDMA_PKT_PTEPDE_RMW_HEADER_snp_shift 22
1931 #define SDMA_PKT_PTEPDE_RMW_HEADER_SNP(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_snp_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_snp_shift)
1933 /*define for gpa field*/
1934 #define SDMA_PKT_PTEPDE_RMW_HEADER_gpa_offset 0
1935 #define SDMA_PKT_PTEPDE_RMW_HEADER_gpa_mask 0x00000001
1936 #define SDMA_PKT_PTEPDE_RMW_HEADER_gpa_shift 23
1937 #define SDMA_PKT_PTEPDE_RMW_HEADER_GPA(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_gpa_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_gpa_shift)
1939 /*define for ADDR_LO word*/
1940 /*define for addr_31_0 field*/
1941 #define SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_offset 1
1942 #define SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_mask 0xFFFFFFFF
1943 #define SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_shift 0
1944 #define SDMA_PKT_PTEPDE_RMW_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_mask) << SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_shift)
1946 /*define for ADDR_HI word*/
1947 /*define for addr_63_32 field*/
1948 #define SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_offset 2
1949 #define SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_mask 0xFFFFFFFF
1950 #define SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_shift 0
1951 #define SDMA_PKT_PTEPDE_RMW_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_mask) << SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_shift)
1953 /*define for MASK_LO word*/
1954 /*define for mask_31_0 field*/
1955 #define SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_offset 3
1956 #define SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_mask 0xFFFFFFFF
1957 #define SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_shift 0
1958 #define SDMA_PKT_PTEPDE_RMW_MASK_LO_MASK_31_0(x) (((x) & SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_mask) << SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_shift)
1960 /*define for MASK_HI word*/
1961 /*define for mask_63_32 field*/
1962 #define SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_offset 4
1963 #define SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_mask 0xFFFFFFFF
1964 #define SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_shift 0
1965 #define SDMA_PKT_PTEPDE_RMW_MASK_HI_MASK_63_32(x) (((x) & SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_mask) << SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_shift)
1967 /*define for VALUE_LO word*/
1968 /*define for value_31_0 field*/
1969 #define SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_offset 5
1970 #define SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_mask 0xFFFFFFFF
1971 #define SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_shift 0
1972 #define SDMA_PKT_PTEPDE_RMW_VALUE_LO_VALUE_31_0(x) (((x) & SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_mask) << SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_shift)
1974 /*define for VALUE_HI word*/
1975 /*define for value_63_32 field*/
1976 #define SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_offset 6
1977 #define SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_mask 0xFFFFFFFF
1978 #define SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_shift 0
1979 #define SDMA_PKT_PTEPDE_RMW_VALUE_HI_VALUE_63_32(x) (((x) & SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_mask) << SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_shift)
1983 ** Definitions for SDMA_PKT_WRITE_INCR packet
1986 /*define for HEADER word*/
1987 /*define for op field*/
1988 #define SDMA_PKT_WRITE_INCR_HEADER_op_offset 0
1989 #define SDMA_PKT_WRITE_INCR_HEADER_op_mask 0x000000FF
1990 #define SDMA_PKT_WRITE_INCR_HEADER_op_shift 0
1991 #define SDMA_PKT_WRITE_INCR_HEADER_OP(x) (((x) & SDMA_PKT_WRITE_INCR_HEADER_op_mask) << SDMA_PKT_WRITE_INCR_HEADER_op_shift)
1993 /*define for sub_op field*/
1994 #define SDMA_PKT_WRITE_INCR_HEADER_sub_op_offset 0
1995 #define SDMA_PKT_WRITE_INCR_HEADER_sub_op_mask 0x000000FF
1996 #define SDMA_PKT_WRITE_INCR_HEADER_sub_op_shift 8
1997 #define SDMA_PKT_WRITE_INCR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_WRITE_INCR_HEADER_sub_op_mask) << SDMA_PKT_WRITE_INCR_HEADER_sub_op_shift)
1999 /*define for DST_ADDR_LO word*/
2000 /*define for dst_addr_31_0 field*/
2001 #define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_offset 1
2002 #define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF
2003 #define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_shift 0
2004 #define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_shift)
2006 /*define for DST_ADDR_HI word*/
2007 /*define for dst_addr_63_32 field*/
2008 #define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_offset 2
2009 #define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF
2010 #define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_shift 0
2011 #define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_shift)
2013 /*define for MASK_DW0 word*/
2014 /*define for mask_dw0 field*/
2015 #define SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_offset 3
2016 #define SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_mask 0xFFFFFFFF
2017 #define SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_shift 0
2018 #define SDMA_PKT_WRITE_INCR_MASK_DW0_MASK_DW0(x) (((x) & SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_mask) << SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_shift)
2020 /*define for MASK_DW1 word*/
2021 /*define for mask_dw1 field*/
2022 #define SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_offset 4
2023 #define SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_mask 0xFFFFFFFF
2024 #define SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_shift 0
2025 #define SDMA_PKT_WRITE_INCR_MASK_DW1_MASK_DW1(x) (((x) & SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_mask) << SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_shift)
2027 /*define for INIT_DW0 word*/
2028 /*define for init_dw0 field*/
2029 #define SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_offset 5
2030 #define SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_mask 0xFFFFFFFF
2031 #define SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_shift 0
2032 #define SDMA_PKT_WRITE_INCR_INIT_DW0_INIT_DW0(x) (((x) & SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_mask) << SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_shift)
2034 /*define for INIT_DW1 word*/
2035 /*define for init_dw1 field*/
2036 #define SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_offset 6
2037 #define SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_mask 0xFFFFFFFF
2038 #define SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_shift 0
2039 #define SDMA_PKT_WRITE_INCR_INIT_DW1_INIT_DW1(x) (((x) & SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_mask) << SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_shift)
2041 /*define for INCR_DW0 word*/
2042 /*define for incr_dw0 field*/
2043 #define SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_offset 7
2044 #define SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_mask 0xFFFFFFFF
2045 #define SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_shift 0
2046 #define SDMA_PKT_WRITE_INCR_INCR_DW0_INCR_DW0(x) (((x) & SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_mask) << SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_shift)
2048 /*define for INCR_DW1 word*/
2049 /*define for incr_dw1 field*/
2050 #define SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_offset 8
2051 #define SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_mask 0xFFFFFFFF
2052 #define SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_shift 0
2053 #define SDMA_PKT_WRITE_INCR_INCR_DW1_INCR_DW1(x) (((x) & SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_mask) << SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_shift)
2055 /*define for COUNT word*/
2056 /*define for count field*/
2057 #define SDMA_PKT_WRITE_INCR_COUNT_count_offset 9
2058 #define SDMA_PKT_WRITE_INCR_COUNT_count_mask 0x0007FFFF
2059 #define SDMA_PKT_WRITE_INCR_COUNT_count_shift 0
2060 #define SDMA_PKT_WRITE_INCR_COUNT_COUNT(x) (((x) & SDMA_PKT_WRITE_INCR_COUNT_count_mask) << SDMA_PKT_WRITE_INCR_COUNT_count_shift)
2064 ** Definitions for SDMA_PKT_INDIRECT packet
2067 /*define for HEADER word*/
2068 /*define for op field*/
2069 #define SDMA_PKT_INDIRECT_HEADER_op_offset 0
2070 #define SDMA_PKT_INDIRECT_HEADER_op_mask 0x000000FF
2071 #define SDMA_PKT_INDIRECT_HEADER_op_shift 0
2072 #define SDMA_PKT_INDIRECT_HEADER_OP(x) (((x) & SDMA_PKT_INDIRECT_HEADER_op_mask) << SDMA_PKT_INDIRECT_HEADER_op_shift)
2074 /*define for sub_op field*/
2075 #define SDMA_PKT_INDIRECT_HEADER_sub_op_offset 0
2076 #define SDMA_PKT_INDIRECT_HEADER_sub_op_mask 0x000000FF
2077 #define SDMA_PKT_INDIRECT_HEADER_sub_op_shift 8
2078 #define SDMA_PKT_INDIRECT_HEADER_SUB_OP(x) (((x) & SDMA_PKT_INDIRECT_HEADER_sub_op_mask) << SDMA_PKT_INDIRECT_HEADER_sub_op_shift)
2080 /*define for vmid field*/
2081 #define SDMA_PKT_INDIRECT_HEADER_vmid_offset 0
2082 #define SDMA_PKT_INDIRECT_HEADER_vmid_mask 0x0000000F
2083 #define SDMA_PKT_INDIRECT_HEADER_vmid_shift 16
2084 #define SDMA_PKT_INDIRECT_HEADER_VMID(x) (((x) & SDMA_PKT_INDIRECT_HEADER_vmid_mask) << SDMA_PKT_INDIRECT_HEADER_vmid_shift)
2086 /*define for BASE_LO word*/
2087 /*define for ib_base_31_0 field*/
2088 #define SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_offset 1
2089 #define SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_mask 0xFFFFFFFF
2090 #define SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_shift 0
2091 #define SDMA_PKT_INDIRECT_BASE_LO_IB_BASE_31_0(x) (((x) & SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_mask) << SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_shift)
2093 /*define for BASE_HI word*/
2094 /*define for ib_base_63_32 field*/
2095 #define SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_offset 2
2096 #define SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_mask 0xFFFFFFFF
2097 #define SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_shift 0
2098 #define SDMA_PKT_INDIRECT_BASE_HI_IB_BASE_63_32(x) (((x) & SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_mask) << SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_shift)
2100 /*define for IB_SIZE word*/
2101 /*define for ib_size field*/
2102 #define SDMA_PKT_INDIRECT_IB_SIZE_ib_size_offset 3
2103 #define SDMA_PKT_INDIRECT_IB_SIZE_ib_size_mask 0x000FFFFF
2104 #define SDMA_PKT_INDIRECT_IB_SIZE_ib_size_shift 0
2105 #define SDMA_PKT_INDIRECT_IB_SIZE_IB_SIZE(x) (((x) & SDMA_PKT_INDIRECT_IB_SIZE_ib_size_mask) << SDMA_PKT_INDIRECT_IB_SIZE_ib_size_shift)
2107 /*define for CSA_ADDR_LO word*/
2108 /*define for csa_addr_31_0 field*/
2109 #define SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_offset 4
2110 #define SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_mask 0xFFFFFFFF
2111 #define SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_shift 0
2112 #define SDMA_PKT_INDIRECT_CSA_ADDR_LO_CSA_ADDR_31_0(x) (((x) & SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_mask) << SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_shift)
2114 /*define for CSA_ADDR_HI word*/
2115 /*define for csa_addr_63_32 field*/
2116 #define SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_offset 5
2117 #define SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_mask 0xFFFFFFFF
2118 #define SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_shift 0
2119 #define SDMA_PKT_INDIRECT_CSA_ADDR_HI_CSA_ADDR_63_32(x) (((x) & SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_mask) << SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_shift)
2123 ** Definitions for SDMA_PKT_SEMAPHORE packet
2126 /*define for HEADER word*/
2127 /*define for op field*/
2128 #define SDMA_PKT_SEMAPHORE_HEADER_op_offset 0
2129 #define SDMA_PKT_SEMAPHORE_HEADER_op_mask 0x000000FF
2130 #define SDMA_PKT_SEMAPHORE_HEADER_op_shift 0
2131 #define SDMA_PKT_SEMAPHORE_HEADER_OP(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_op_mask) << SDMA_PKT_SEMAPHORE_HEADER_op_shift)
2133 /*define for sub_op field*/
2134 #define SDMA_PKT_SEMAPHORE_HEADER_sub_op_offset 0
2135 #define SDMA_PKT_SEMAPHORE_HEADER_sub_op_mask 0x000000FF
2136 #define SDMA_PKT_SEMAPHORE_HEADER_sub_op_shift 8
2137 #define SDMA_PKT_SEMAPHORE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_sub_op_mask) << SDMA_PKT_SEMAPHORE_HEADER_sub_op_shift)
2139 /*define for write_one field*/
2140 #define SDMA_PKT_SEMAPHORE_HEADER_write_one_offset 0
2141 #define SDMA_PKT_SEMAPHORE_HEADER_write_one_mask 0x00000001
2142 #define SDMA_PKT_SEMAPHORE_HEADER_write_one_shift 29
2143 #define SDMA_PKT_SEMAPHORE_HEADER_WRITE_ONE(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_write_one_mask) << SDMA_PKT_SEMAPHORE_HEADER_write_one_shift)
2145 /*define for signal field*/
2146 #define SDMA_PKT_SEMAPHORE_HEADER_signal_offset 0
2147 #define SDMA_PKT_SEMAPHORE_HEADER_signal_mask 0x00000001
2148 #define SDMA_PKT_SEMAPHORE_HEADER_signal_shift 30
2149 #define SDMA_PKT_SEMAPHORE_HEADER_SIGNAL(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_signal_mask) << SDMA_PKT_SEMAPHORE_HEADER_signal_shift)
2151 /*define for mailbox field*/
2152 #define SDMA_PKT_SEMAPHORE_HEADER_mailbox_offset 0
2153 #define SDMA_PKT_SEMAPHORE_HEADER_mailbox_mask 0x00000001
2154 #define SDMA_PKT_SEMAPHORE_HEADER_mailbox_shift 31
2155 #define SDMA_PKT_SEMAPHORE_HEADER_MAILBOX(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_mailbox_mask) << SDMA_PKT_SEMAPHORE_HEADER_mailbox_shift)
2157 /*define for ADDR_LO word*/
2158 /*define for addr_31_0 field*/
2159 #define SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_offset 1
2160 #define SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_mask 0xFFFFFFFF
2161 #define SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_shift 0
2162 #define SDMA_PKT_SEMAPHORE_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_mask) << SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_shift)
2164 /*define for ADDR_HI word*/
2165 /*define for addr_63_32 field*/
2166 #define SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_offset 2
2167 #define SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_mask 0xFFFFFFFF
2168 #define SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_shift 0
2169 #define SDMA_PKT_SEMAPHORE_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_mask) << SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_shift)
2173 ** Definitions for SDMA_PKT_FENCE packet
2176 /*define for HEADER word*/
2177 /*define for op field*/
2178 #define SDMA_PKT_FENCE_HEADER_op_offset 0
2179 #define SDMA_PKT_FENCE_HEADER_op_mask 0x000000FF
2180 #define SDMA_PKT_FENCE_HEADER_op_shift 0
2181 #define SDMA_PKT_FENCE_HEADER_OP(x) (((x) & SDMA_PKT_FENCE_HEADER_op_mask) << SDMA_PKT_FENCE_HEADER_op_shift)
2183 /*define for sub_op field*/
2184 #define SDMA_PKT_FENCE_HEADER_sub_op_offset 0
2185 #define SDMA_PKT_FENCE_HEADER_sub_op_mask 0x000000FF
2186 #define SDMA_PKT_FENCE_HEADER_sub_op_shift 8
2187 #define SDMA_PKT_FENCE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_FENCE_HEADER_sub_op_mask) << SDMA_PKT_FENCE_HEADER_sub_op_shift)
2189 /*define for ADDR_LO word*/
2190 /*define for addr_31_0 field*/
2191 #define SDMA_PKT_FENCE_ADDR_LO_addr_31_0_offset 1
2192 #define SDMA_PKT_FENCE_ADDR_LO_addr_31_0_mask 0xFFFFFFFF
2193 #define SDMA_PKT_FENCE_ADDR_LO_addr_31_0_shift 0
2194 #define SDMA_PKT_FENCE_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_FENCE_ADDR_LO_addr_31_0_mask) << SDMA_PKT_FENCE_ADDR_LO_addr_31_0_shift)
2196 /*define for ADDR_HI word*/
2197 /*define for addr_63_32 field*/
2198 #define SDMA_PKT_FENCE_ADDR_HI_addr_63_32_offset 2
2199 #define SDMA_PKT_FENCE_ADDR_HI_addr_63_32_mask 0xFFFFFFFF
2200 #define SDMA_PKT_FENCE_ADDR_HI_addr_63_32_shift 0
2201 #define SDMA_PKT_FENCE_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_FENCE_ADDR_HI_addr_63_32_mask) << SDMA_PKT_FENCE_ADDR_HI_addr_63_32_shift)
2203 /*define for DATA word*/
2204 /*define for data field*/
2205 #define SDMA_PKT_FENCE_DATA_data_offset 3
2206 #define SDMA_PKT_FENCE_DATA_data_mask 0xFFFFFFFF
2207 #define SDMA_PKT_FENCE_DATA_data_shift 0
2208 #define SDMA_PKT_FENCE_DATA_DATA(x) (((x) & SDMA_PKT_FENCE_DATA_data_mask) << SDMA_PKT_FENCE_DATA_data_shift)
2212 ** Definitions for SDMA_PKT_SRBM_WRITE packet
2215 /*define for HEADER word*/
2216 /*define for op field*/
2217 #define SDMA_PKT_SRBM_WRITE_HEADER_op_offset 0
2218 #define SDMA_PKT_SRBM_WRITE_HEADER_op_mask 0x000000FF
2219 #define SDMA_PKT_SRBM_WRITE_HEADER_op_shift 0
2220 #define SDMA_PKT_SRBM_WRITE_HEADER_OP(x) (((x) & SDMA_PKT_SRBM_WRITE_HEADER_op_mask) << SDMA_PKT_SRBM_WRITE_HEADER_op_shift)
2222 /*define for sub_op field*/
2223 #define SDMA_PKT_SRBM_WRITE_HEADER_sub_op_offset 0
2224 #define SDMA_PKT_SRBM_WRITE_HEADER_sub_op_mask 0x000000FF
2225 #define SDMA_PKT_SRBM_WRITE_HEADER_sub_op_shift 8
2226 #define SDMA_PKT_SRBM_WRITE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_SRBM_WRITE_HEADER_sub_op_mask) << SDMA_PKT_SRBM_WRITE_HEADER_sub_op_shift)
2228 /*define for byte_en field*/
2229 #define SDMA_PKT_SRBM_WRITE_HEADER_byte_en_offset 0
2230 #define SDMA_PKT_SRBM_WRITE_HEADER_byte_en_mask 0x0000000F
2231 #define SDMA_PKT_SRBM_WRITE_HEADER_byte_en_shift 28
2232 #define SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(x) (((x) & SDMA_PKT_SRBM_WRITE_HEADER_byte_en_mask) << SDMA_PKT_SRBM_WRITE_HEADER_byte_en_shift)
2234 /*define for ADDR word*/
2235 /*define for addr field*/
2236 #define SDMA_PKT_SRBM_WRITE_ADDR_addr_offset 1
2237 #define SDMA_PKT_SRBM_WRITE_ADDR_addr_mask 0x0003FFFF
2238 #define SDMA_PKT_SRBM_WRITE_ADDR_addr_shift 0
2239 #define SDMA_PKT_SRBM_WRITE_ADDR_ADDR(x) (((x) & SDMA_PKT_SRBM_WRITE_ADDR_addr_mask) << SDMA_PKT_SRBM_WRITE_ADDR_addr_shift)
2241 /*define for DATA word*/
2242 /*define for data field*/
2243 #define SDMA_PKT_SRBM_WRITE_DATA_data_offset 2
2244 #define SDMA_PKT_SRBM_WRITE_DATA_data_mask 0xFFFFFFFF
2245 #define SDMA_PKT_SRBM_WRITE_DATA_data_shift 0
2246 #define SDMA_PKT_SRBM_WRITE_DATA_DATA(x) (((x) & SDMA_PKT_SRBM_WRITE_DATA_data_mask) << SDMA_PKT_SRBM_WRITE_DATA_data_shift)
2250 ** Definitions for SDMA_PKT_PRE_EXE packet
2253 /*define for HEADER word*/
2254 /*define for op field*/
2255 #define SDMA_PKT_PRE_EXE_HEADER_op_offset 0
2256 #define SDMA_PKT_PRE_EXE_HEADER_op_mask 0x000000FF
2257 #define SDMA_PKT_PRE_EXE_HEADER_op_shift 0
2258 #define SDMA_PKT_PRE_EXE_HEADER_OP(x) (((x) & SDMA_PKT_PRE_EXE_HEADER_op_mask) << SDMA_PKT_PRE_EXE_HEADER_op_shift)
2260 /*define for sub_op field*/
2261 #define SDMA_PKT_PRE_EXE_HEADER_sub_op_offset 0
2262 #define SDMA_PKT_PRE_EXE_HEADER_sub_op_mask 0x000000FF
2263 #define SDMA_PKT_PRE_EXE_HEADER_sub_op_shift 8
2264 #define SDMA_PKT_PRE_EXE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_PRE_EXE_HEADER_sub_op_mask) << SDMA_PKT_PRE_EXE_HEADER_sub_op_shift)
2266 /*define for dev_sel field*/
2267 #define SDMA_PKT_PRE_EXE_HEADER_dev_sel_offset 0
2268 #define SDMA_PKT_PRE_EXE_HEADER_dev_sel_mask 0x000000FF
2269 #define SDMA_PKT_PRE_EXE_HEADER_dev_sel_shift 16
2270 #define SDMA_PKT_PRE_EXE_HEADER_DEV_SEL(x) (((x) & SDMA_PKT_PRE_EXE_HEADER_dev_sel_mask) << SDMA_PKT_PRE_EXE_HEADER_dev_sel_shift)
2272 /*define for EXEC_COUNT word*/
2273 /*define for exec_count field*/
2274 #define SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_offset 1
2275 #define SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_mask 0x00003FFF
2276 #define SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_shift 0
2277 #define SDMA_PKT_PRE_EXE_EXEC_COUNT_EXEC_COUNT(x) (((x) & SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_mask) << SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_shift)
2281 ** Definitions for SDMA_PKT_COND_EXE packet
2284 /*define for HEADER word*/
2285 /*define for op field*/
2286 #define SDMA_PKT_COND_EXE_HEADER_op_offset 0
2287 #define SDMA_PKT_COND_EXE_HEADER_op_mask 0x000000FF
2288 #define SDMA_PKT_COND_EXE_HEADER_op_shift 0
2289 #define SDMA_PKT_COND_EXE_HEADER_OP(x) (((x) & SDMA_PKT_COND_EXE_HEADER_op_mask) << SDMA_PKT_COND_EXE_HEADER_op_shift)
2291 /*define for sub_op field*/
2292 #define SDMA_PKT_COND_EXE_HEADER_sub_op_offset 0
2293 #define SDMA_PKT_COND_EXE_HEADER_sub_op_mask 0x000000FF
2294 #define SDMA_PKT_COND_EXE_HEADER_sub_op_shift 8
2295 #define SDMA_PKT_COND_EXE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COND_EXE_HEADER_sub_op_mask) << SDMA_PKT_COND_EXE_HEADER_sub_op_shift)
2297 /*define for ADDR_LO word*/
2298 /*define for addr_31_0 field*/
2299 #define SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_offset 1
2300 #define SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_mask 0xFFFFFFFF
2301 #define SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_shift 0
2302 #define SDMA_PKT_COND_EXE_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_mask) << SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_shift)
2304 /*define for ADDR_HI word*/
2305 /*define for addr_63_32 field*/
2306 #define SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_offset 2
2307 #define SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_mask 0xFFFFFFFF
2308 #define SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_shift 0
2309 #define SDMA_PKT_COND_EXE_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_mask) << SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_shift)
2311 /*define for REFERENCE word*/
2312 /*define for reference field*/
2313 #define SDMA_PKT_COND_EXE_REFERENCE_reference_offset 3
2314 #define SDMA_PKT_COND_EXE_REFERENCE_reference_mask 0xFFFFFFFF
2315 #define SDMA_PKT_COND_EXE_REFERENCE_reference_shift 0
2316 #define SDMA_PKT_COND_EXE_REFERENCE_REFERENCE(x) (((x) & SDMA_PKT_COND_EXE_REFERENCE_reference_mask) << SDMA_PKT_COND_EXE_REFERENCE_reference_shift)
2318 /*define for EXEC_COUNT word*/
2319 /*define for exec_count field*/
2320 #define SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_offset 4
2321 #define SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_mask 0x00003FFF
2322 #define SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_shift 0
2323 #define SDMA_PKT_COND_EXE_EXEC_COUNT_EXEC_COUNT(x) (((x) & SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_mask) << SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_shift)
2327 ** Definitions for SDMA_PKT_CONSTANT_FILL packet
2330 /*define for HEADER word*/
2331 /*define for op field*/
2332 #define SDMA_PKT_CONSTANT_FILL_HEADER_op_offset 0
2333 #define SDMA_PKT_CONSTANT_FILL_HEADER_op_mask 0x000000FF
2334 #define SDMA_PKT_CONSTANT_FILL_HEADER_op_shift 0
2335 #define SDMA_PKT_CONSTANT_FILL_HEADER_OP(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_op_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_op_shift)
2337 /*define for sub_op field*/
2338 #define SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_offset 0
2339 #define SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_mask 0x000000FF
2340 #define SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_shift 8
2341 #define SDMA_PKT_CONSTANT_FILL_HEADER_SUB_OP(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_shift)
2343 /*define for sw field*/
2344 #define SDMA_PKT_CONSTANT_FILL_HEADER_sw_offset 0
2345 #define SDMA_PKT_CONSTANT_FILL_HEADER_sw_mask 0x00000003
2346 #define SDMA_PKT_CONSTANT_FILL_HEADER_sw_shift 16
2347 #define SDMA_PKT_CONSTANT_FILL_HEADER_SW(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_sw_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_sw_shift)
2349 /*define for fillsize field*/
2350 #define SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_offset 0
2351 #define SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_mask 0x00000003
2352 #define SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_shift 30
2353 #define SDMA_PKT_CONSTANT_FILL_HEADER_FILLSIZE(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_shift)
2355 /*define for DST_ADDR_LO word*/
2356 /*define for dst_addr_31_0 field*/
2357 #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_offset 1
2358 #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF
2359 #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_shift 0
2360 #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_shift)
2362 /*define for DST_ADDR_HI word*/
2363 /*define for dst_addr_63_32 field*/
2364 #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_offset 2
2365 #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF
2366 #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_shift 0
2367 #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_shift)
2369 /*define for DATA word*/
2370 /*define for src_data_31_0 field*/
2371 #define SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_offset 3
2372 #define SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_mask 0xFFFFFFFF
2373 #define SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_shift 0
2374 #define SDMA_PKT_CONSTANT_FILL_DATA_SRC_DATA_31_0(x) (((x) & SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_mask) << SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_shift)
2376 /*define for COUNT word*/
2377 /*define for count field*/
2378 #define SDMA_PKT_CONSTANT_FILL_COUNT_count_offset 4
2379 #define SDMA_PKT_CONSTANT_FILL_COUNT_count_mask 0x003FFFFF
2380 #define SDMA_PKT_CONSTANT_FILL_COUNT_count_shift 0
2381 #define SDMA_PKT_CONSTANT_FILL_COUNT_COUNT(x) (((x) & SDMA_PKT_CONSTANT_FILL_COUNT_count_mask) << SDMA_PKT_CONSTANT_FILL_COUNT_count_shift)
2385 ** Definitions for SDMA_PKT_DATA_FILL_MULTI packet
2388 /*define for HEADER word*/
2389 /*define for op field*/
2390 #define SDMA_PKT_DATA_FILL_MULTI_HEADER_op_offset 0
2391 #define SDMA_PKT_DATA_FILL_MULTI_HEADER_op_mask 0x000000FF
2392 #define SDMA_PKT_DATA_FILL_MULTI_HEADER_op_shift 0
2393 #define SDMA_PKT_DATA_FILL_MULTI_HEADER_OP(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_HEADER_op_mask) << SDMA_PKT_DATA_FILL_MULTI_HEADER_op_shift)
2395 /*define for sub_op field*/
2396 #define SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_offset 0
2397 #define SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_mask 0x000000FF
2398 #define SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_shift 8
2399 #define SDMA_PKT_DATA_FILL_MULTI_HEADER_SUB_OP(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_mask) << SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_shift)
2401 /*define for memlog_clr field*/
2402 #define SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_offset 0
2403 #define SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_mask 0x00000001
2404 #define SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_shift 31
2405 #define SDMA_PKT_DATA_FILL_MULTI_HEADER_MEMLOG_CLR(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_mask) << SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_shift)
2407 /*define for BYTE_STRIDE word*/
2408 /*define for byte_stride field*/
2409 #define SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_offset 1
2410 #define SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_mask 0xFFFFFFFF
2411 #define SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_shift 0
2412 #define SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_BYTE_STRIDE(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_mask) << SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_shift)
2414 /*define for DMA_COUNT word*/
2415 /*define for dma_count field*/
2416 #define SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_offset 2
2417 #define SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_mask 0xFFFFFFFF
2418 #define SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_shift 0
2419 #define SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_DMA_COUNT(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_mask) << SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_shift)
2421 /*define for DST_ADDR_LO word*/
2422 /*define for dst_addr_31_0 field*/
2423 #define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_offset 3
2424 #define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF
2425 #define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_shift 0
2426 #define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_shift)
2428 /*define for DST_ADDR_HI word*/
2429 /*define for dst_addr_63_32 field*/
2430 #define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_offset 4
2431 #define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF
2432 #define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_shift 0
2433 #define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_shift)
2435 /*define for BYTE_COUNT word*/
2436 /*define for count field*/
2437 #define SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_offset 5
2438 #define SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_mask 0x03FFFFFF
2439 #define SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_shift 0
2440 #define SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_COUNT(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_mask) << SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_shift)
2444 ** Definitions for SDMA_PKT_POLL_REGMEM packet
2447 /*define for HEADER word*/
2448 /*define for op field*/
2449 #define SDMA_PKT_POLL_REGMEM_HEADER_op_offset 0
2450 #define SDMA_PKT_POLL_REGMEM_HEADER_op_mask 0x000000FF
2451 #define SDMA_PKT_POLL_REGMEM_HEADER_op_shift 0
2452 #define SDMA_PKT_POLL_REGMEM_HEADER_OP(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_op_mask) << SDMA_PKT_POLL_REGMEM_HEADER_op_shift)
2454 /*define for sub_op field*/
2455 #define SDMA_PKT_POLL_REGMEM_HEADER_sub_op_offset 0
2456 #define SDMA_PKT_POLL_REGMEM_HEADER_sub_op_mask 0x000000FF
2457 #define SDMA_PKT_POLL_REGMEM_HEADER_sub_op_shift 8
2458 #define SDMA_PKT_POLL_REGMEM_HEADER_SUB_OP(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_sub_op_mask) << SDMA_PKT_POLL_REGMEM_HEADER_sub_op_shift)
2460 /*define for hdp_flush field*/
2461 #define SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_offset 0
2462 #define SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_mask 0x00000001
2463 #define SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_shift 26
2464 #define SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_mask) << SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_shift)
2466 /*define for func field*/
2467 #define SDMA_PKT_POLL_REGMEM_HEADER_func_offset 0
2468 #define SDMA_PKT_POLL_REGMEM_HEADER_func_mask 0x00000007
2469 #define SDMA_PKT_POLL_REGMEM_HEADER_func_shift 28
2470 #define SDMA_PKT_POLL_REGMEM_HEADER_FUNC(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_func_mask) << SDMA_PKT_POLL_REGMEM_HEADER_func_shift)
2472 /*define for mem_poll field*/
2473 #define SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_offset 0
2474 #define SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_mask 0x00000001
2475 #define SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_shift 31
2476 #define SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_mask) << SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_shift)
2478 /*define for ADDR_LO word*/
2479 /*define for addr_31_0 field*/
2480 #define SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_offset 1
2481 #define SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_mask 0xFFFFFFFF
2482 #define SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_shift 0
2483 #define SDMA_PKT_POLL_REGMEM_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_mask) << SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_shift)
2485 /*define for ADDR_HI word*/
2486 /*define for addr_63_32 field*/
2487 #define SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_offset 2
2488 #define SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_mask 0xFFFFFFFF
2489 #define SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_shift 0
2490 #define SDMA_PKT_POLL_REGMEM_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_mask) << SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_shift)
2492 /*define for VALUE word*/
2493 /*define for value field*/
2494 #define SDMA_PKT_POLL_REGMEM_VALUE_value_offset 3
2495 #define SDMA_PKT_POLL_REGMEM_VALUE_value_mask 0xFFFFFFFF
2496 #define SDMA_PKT_POLL_REGMEM_VALUE_value_shift 0
2497 #define SDMA_PKT_POLL_REGMEM_VALUE_VALUE(x) (((x) & SDMA_PKT_POLL_REGMEM_VALUE_value_mask) << SDMA_PKT_POLL_REGMEM_VALUE_value_shift)
2499 /*define for MASK word*/
2500 /*define for mask field*/
2501 #define SDMA_PKT_POLL_REGMEM_MASK_mask_offset 4
2502 #define SDMA_PKT_POLL_REGMEM_MASK_mask_mask 0xFFFFFFFF
2503 #define SDMA_PKT_POLL_REGMEM_MASK_mask_shift 0
2504 #define SDMA_PKT_POLL_REGMEM_MASK_MASK(x) (((x) & SDMA_PKT_POLL_REGMEM_MASK_mask_mask) << SDMA_PKT_POLL_REGMEM_MASK_mask_shift)
2506 /*define for DW5 word*/
2507 /*define for interval field*/
2508 #define SDMA_PKT_POLL_REGMEM_DW5_interval_offset 5
2509 #define SDMA_PKT_POLL_REGMEM_DW5_interval_mask 0x0000FFFF
2510 #define SDMA_PKT_POLL_REGMEM_DW5_interval_shift 0
2511 #define SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(x) (((x) & SDMA_PKT_POLL_REGMEM_DW5_interval_mask) << SDMA_PKT_POLL_REGMEM_DW5_interval_shift)
2513 /*define for retry_count field*/
2514 #define SDMA_PKT_POLL_REGMEM_DW5_retry_count_offset 5
2515 #define SDMA_PKT_POLL_REGMEM_DW5_retry_count_mask 0x00000FFF
2516 #define SDMA_PKT_POLL_REGMEM_DW5_retry_count_shift 16
2517 #define SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(x) (((x) & SDMA_PKT_POLL_REGMEM_DW5_retry_count_mask) << SDMA_PKT_POLL_REGMEM_DW5_retry_count_shift)
2521 ** Definitions for SDMA_PKT_POLL_REG_WRITE_MEM packet
2524 /*define for HEADER word*/
2525 /*define for op field*/
2526 #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_offset 0
2527 #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_mask 0x000000FF
2528 #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_shift 0
2529 #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_OP(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_shift)
2531 /*define for sub_op field*/
2532 #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_offset 0
2533 #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_mask 0x000000FF
2534 #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_shift 8
2535 #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_SUB_OP(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_shift)
2537 /*define for SRC_ADDR word*/
2538 /*define for addr_31_2 field*/
2539 #define SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_offset 1
2540 #define SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_mask 0x3FFFFFFF
2541 #define SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_shift 2
2542 #define SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_ADDR_31_2(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_shift)
2544 /*define for DST_ADDR_LO word*/
2545 /*define for addr_31_0 field*/
2546 #define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset 2
2547 #define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask 0xFFFFFFFF
2548 #define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift 0
2549 #define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift)
2551 /*define for DST_ADDR_HI word*/
2552 /*define for addr_63_32 field*/
2553 #define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset 3
2554 #define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask 0xFFFFFFFF
2555 #define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift 0
2556 #define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift)
2560 ** Definitions for SDMA_PKT_POLL_DBIT_WRITE_MEM packet
2563 /*define for HEADER word*/
2564 /*define for op field*/
2565 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_offset 0
2566 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_mask 0x000000FF
2567 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_shift 0
2568 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_OP(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_shift)
2570 /*define for sub_op field*/
2571 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_offset 0
2572 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_mask 0x000000FF
2573 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_shift 8
2574 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_SUB_OP(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_shift)
2576 /*define for ea field*/
2577 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_offset 0
2578 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_mask 0x00000003
2579 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_shift 16
2580 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_EA(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_shift)
2582 /*define for DST_ADDR_LO word*/
2583 /*define for addr_31_0 field*/
2584 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset 1
2585 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask 0xFFFFFFFF
2586 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift 0
2587 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift)
2589 /*define for DST_ADDR_HI word*/
2590 /*define for addr_63_32 field*/
2591 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset 2
2592 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask 0xFFFFFFFF
2593 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift 0
2594 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift)
2596 /*define for START_PAGE word*/
2597 /*define for addr_31_4 field*/
2598 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_offset 3
2599 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_mask 0x0FFFFFFF
2600 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_shift 4
2601 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_ADDR_31_4(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_shift)
2603 /*define for PAGE_NUM word*/
2604 /*define for page_num_31_0 field*/
2605 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_offset 4
2606 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_mask 0xFFFFFFFF
2607 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_shift 0
2608 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_PAGE_NUM_31_0(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_shift)
2612 ** Definitions for SDMA_PKT_POLL_MEM_VERIFY packet
2615 /*define for HEADER word*/
2616 /*define for op field*/
2617 #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_offset 0
2618 #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_mask 0x000000FF
2619 #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_shift 0
2620 #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_OP(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_mask) << SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_shift)
2622 /*define for sub_op field*/
2623 #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_offset 0
2624 #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_mask 0x000000FF
2625 #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_shift 8
2626 #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_SUB_OP(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_mask) << SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_shift)
2628 /*define for mode field*/
2629 #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_offset 0
2630 #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_mask 0x00000001
2631 #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_shift 31
2632 #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_MODE(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_mask) << SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_shift)
2634 /*define for PATTERN word*/
2635 /*define for pattern field*/
2636 #define SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_offset 1
2637 #define SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_mask 0xFFFFFFFF
2638 #define SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_shift 0
2639 #define SDMA_PKT_POLL_MEM_VERIFY_PATTERN_PATTERN(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_mask) << SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_shift)
2641 /*define for CMP0_ADDR_START_LO word*/
2642 /*define for cmp0_start_31_0 field*/
2643 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_offset 2
2644 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_mask 0xFFFFFFFF
2645 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_shift 0
2646 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_CMP0_START_31_0(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_shift)
2648 /*define for CMP0_ADDR_START_HI word*/
2649 /*define for cmp0_start_63_32 field*/
2650 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_offset 3
2651 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_mask 0xFFFFFFFF
2652 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_shift 0
2653 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_CMP0_START_63_32(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_shift)
2655 /*define for CMP0_ADDR_END_LO word*/
2656 /*define for cmp1_end_31_0 field*/
2657 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_offset 4
2658 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_mask 0xFFFFFFFF
2659 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_shift 0
2660 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_CMP1_END_31_0(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_shift)
2662 /*define for CMP0_ADDR_END_HI word*/
2663 /*define for cmp1_end_63_32 field*/
2664 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_offset 5
2665 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_mask 0xFFFFFFFF
2666 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_shift 0
2667 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_CMP1_END_63_32(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_shift)
2669 /*define for CMP1_ADDR_START_LO word*/
2670 /*define for cmp1_start_31_0 field*/
2671 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_offset 6
2672 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_mask 0xFFFFFFFF
2673 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_shift 0
2674 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_CMP1_START_31_0(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_shift)
2676 /*define for CMP1_ADDR_START_HI word*/
2677 /*define for cmp1_start_63_32 field*/
2678 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_offset 7
2679 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_mask 0xFFFFFFFF
2680 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_shift 0
2681 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_CMP1_START_63_32(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_shift)
2683 /*define for CMP1_ADDR_END_LO word*/
2684 /*define for cmp1_end_31_0 field*/
2685 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_offset 8
2686 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_mask 0xFFFFFFFF
2687 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_shift 0
2688 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_CMP1_END_31_0(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_shift)
2690 /*define for CMP1_ADDR_END_HI word*/
2691 /*define for cmp1_end_63_32 field*/
2692 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_offset 9
2693 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_mask 0xFFFFFFFF
2694 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_shift 0
2695 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_CMP1_END_63_32(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_shift)
2697 /*define for REC_ADDR_LO word*/
2698 /*define for rec_31_0 field*/
2699 #define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_offset 10
2700 #define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_mask 0xFFFFFFFF
2701 #define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_shift 0
2702 #define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_REC_31_0(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_shift)
2704 /*define for REC_ADDR_HI word*/
2705 /*define for rec_63_32 field*/
2706 #define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_offset 11
2707 #define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_mask 0xFFFFFFFF
2708 #define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_shift 0
2709 #define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_REC_63_32(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_shift)
2711 /*define for RESERVED word*/
2712 /*define for reserved field*/
2713 #define SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_offset 12
2714 #define SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_mask 0xFFFFFFFF
2715 #define SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_shift 0
2716 #define SDMA_PKT_POLL_MEM_VERIFY_RESERVED_RESERVED(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_mask) << SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_shift)
2720 ** Definitions for SDMA_PKT_ATOMIC packet
2723 /*define for HEADER word*/
2724 /*define for op field*/
2725 #define SDMA_PKT_ATOMIC_HEADER_op_offset 0
2726 #define SDMA_PKT_ATOMIC_HEADER_op_mask 0x000000FF
2727 #define SDMA_PKT_ATOMIC_HEADER_op_shift 0
2728 #define SDMA_PKT_ATOMIC_HEADER_OP(x) (((x) & SDMA_PKT_ATOMIC_HEADER_op_mask) << SDMA_PKT_ATOMIC_HEADER_op_shift)
2730 /*define for loop field*/
2731 #define SDMA_PKT_ATOMIC_HEADER_loop_offset 0
2732 #define SDMA_PKT_ATOMIC_HEADER_loop_mask 0x00000001
2733 #define SDMA_PKT_ATOMIC_HEADER_loop_shift 16
2734 #define SDMA_PKT_ATOMIC_HEADER_LOOP(x) (((x) & SDMA_PKT_ATOMIC_HEADER_loop_mask) << SDMA_PKT_ATOMIC_HEADER_loop_shift)
2736 /*define for tmz field*/
2737 #define SDMA_PKT_ATOMIC_HEADER_tmz_offset 0
2738 #define SDMA_PKT_ATOMIC_HEADER_tmz_mask 0x00000001
2739 #define SDMA_PKT_ATOMIC_HEADER_tmz_shift 18
2740 #define SDMA_PKT_ATOMIC_HEADER_TMZ(x) (((x) & SDMA_PKT_ATOMIC_HEADER_tmz_mask) << SDMA_PKT_ATOMIC_HEADER_tmz_shift)
2742 /*define for atomic_op field*/
2743 #define SDMA_PKT_ATOMIC_HEADER_atomic_op_offset 0
2744 #define SDMA_PKT_ATOMIC_HEADER_atomic_op_mask 0x0000007F
2745 #define SDMA_PKT_ATOMIC_HEADER_atomic_op_shift 25
2746 #define SDMA_PKT_ATOMIC_HEADER_ATOMIC_OP(x) (((x) & SDMA_PKT_ATOMIC_HEADER_atomic_op_mask) << SDMA_PKT_ATOMIC_HEADER_atomic_op_shift)
2748 /*define for ADDR_LO word*/
2749 /*define for addr_31_0 field*/
2750 #define SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_offset 1
2751 #define SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_mask 0xFFFFFFFF
2752 #define SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_shift 0
2753 #define SDMA_PKT_ATOMIC_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_mask) << SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_shift)
2755 /*define for ADDR_HI word*/
2756 /*define for addr_63_32 field*/
2757 #define SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_offset 2
2758 #define SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_mask 0xFFFFFFFF
2759 #define SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_shift 0
2760 #define SDMA_PKT_ATOMIC_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_mask) << SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_shift)
2762 /*define for SRC_DATA_LO word*/
2763 /*define for src_data_31_0 field*/
2764 #define SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_offset 3
2765 #define SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_mask 0xFFFFFFFF
2766 #define SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_shift 0
2767 #define SDMA_PKT_ATOMIC_SRC_DATA_LO_SRC_DATA_31_0(x) (((x) & SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_mask) << SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_shift)
2769 /*define for SRC_DATA_HI word*/
2770 /*define for src_data_63_32 field*/
2771 #define SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_offset 4
2772 #define SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_mask 0xFFFFFFFF
2773 #define SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_shift 0
2774 #define SDMA_PKT_ATOMIC_SRC_DATA_HI_SRC_DATA_63_32(x) (((x) & SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_mask) << SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_shift)
2776 /*define for CMP_DATA_LO word*/
2777 /*define for cmp_data_31_0 field*/
2778 #define SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_offset 5
2779 #define SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_mask 0xFFFFFFFF
2780 #define SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_shift 0
2781 #define SDMA_PKT_ATOMIC_CMP_DATA_LO_CMP_DATA_31_0(x) (((x) & SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_mask) << SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_shift)
2783 /*define for CMP_DATA_HI word*/
2784 /*define for cmp_data_63_32 field*/
2785 #define SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_offset 6
2786 #define SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_mask 0xFFFFFFFF
2787 #define SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_shift 0
2788 #define SDMA_PKT_ATOMIC_CMP_DATA_HI_CMP_DATA_63_32(x) (((x) & SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_mask) << SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_shift)
2790 /*define for LOOP_INTERVAL word*/
2791 /*define for loop_interval field*/
2792 #define SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_offset 7
2793 #define SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_mask 0x00001FFF
2794 #define SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_shift 0
2795 #define SDMA_PKT_ATOMIC_LOOP_INTERVAL_LOOP_INTERVAL(x) (((x) & SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_mask) << SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_shift)
2799 ** Definitions for SDMA_PKT_TIMESTAMP_SET packet
2802 /*define for HEADER word*/
2803 /*define for op field*/
2804 #define SDMA_PKT_TIMESTAMP_SET_HEADER_op_offset 0
2805 #define SDMA_PKT_TIMESTAMP_SET_HEADER_op_mask 0x000000FF
2806 #define SDMA_PKT_TIMESTAMP_SET_HEADER_op_shift 0
2807 #define SDMA_PKT_TIMESTAMP_SET_HEADER_OP(x) (((x) & SDMA_PKT_TIMESTAMP_SET_HEADER_op_mask) << SDMA_PKT_TIMESTAMP_SET_HEADER_op_shift)
2809 /*define for sub_op field*/
2810 #define SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_offset 0
2811 #define SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_mask 0x000000FF
2812 #define SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_shift 8
2813 #define SDMA_PKT_TIMESTAMP_SET_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_mask) << SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_shift)
2815 /*define for INIT_DATA_LO word*/
2816 /*define for init_data_31_0 field*/
2817 #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_offset 1
2818 #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_mask 0xFFFFFFFF
2819 #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_shift 0
2820 #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_INIT_DATA_31_0(x) (((x) & SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_mask) << SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_shift)
2822 /*define for INIT_DATA_HI word*/
2823 /*define for init_data_63_32 field*/
2824 #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_offset 2
2825 #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_mask 0xFFFFFFFF
2826 #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_shift 0
2827 #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_INIT_DATA_63_32(x) (((x) & SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_mask) << SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_shift)
2831 ** Definitions for SDMA_PKT_TIMESTAMP_GET packet
2834 /*define for HEADER word*/
2835 /*define for op field*/
2836 #define SDMA_PKT_TIMESTAMP_GET_HEADER_op_offset 0
2837 #define SDMA_PKT_TIMESTAMP_GET_HEADER_op_mask 0x000000FF
2838 #define SDMA_PKT_TIMESTAMP_GET_HEADER_op_shift 0
2839 #define SDMA_PKT_TIMESTAMP_GET_HEADER_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_HEADER_op_mask) << SDMA_PKT_TIMESTAMP_GET_HEADER_op_shift)
2841 /*define for sub_op field*/
2842 #define SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_offset 0
2843 #define SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_mask 0x000000FF
2844 #define SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_shift 8
2845 #define SDMA_PKT_TIMESTAMP_GET_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_mask) << SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_shift)
2847 /*define for WRITE_ADDR_LO word*/
2848 /*define for write_addr_31_3 field*/
2849 #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_offset 1
2850 #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_mask 0x1FFFFFFF
2851 #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_shift 3
2852 #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_WRITE_ADDR_31_3(x) (((x) & SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_mask) << SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_shift)
2854 /*define for WRITE_ADDR_HI word*/
2855 /*define for write_addr_63_32 field*/
2856 #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_offset 2
2857 #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_mask 0xFFFFFFFF
2858 #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_shift 0
2859 #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_WRITE_ADDR_63_32(x) (((x) & SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_mask) << SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_shift)
2863 ** Definitions for SDMA_PKT_TIMESTAMP_GET_GLOBAL packet
2866 /*define for HEADER word*/
2867 /*define for op field*/
2868 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_offset 0
2869 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_mask 0x000000FF
2870 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_shift 0
2871 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_shift)
2873 /*define for sub_op field*/
2874 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_offset 0
2875 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_mask 0x000000FF
2876 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_shift 8
2877 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_shift)
2879 /*define for WRITE_ADDR_LO word*/
2880 /*define for write_addr_31_3 field*/
2881 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_offset 1
2882 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_mask 0x1FFFFFFF
2883 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_shift 3
2884 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_WRITE_ADDR_31_3(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_shift)
2886 /*define for WRITE_ADDR_HI word*/
2887 /*define for write_addr_63_32 field*/
2888 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_offset 2
2889 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_mask 0xFFFFFFFF
2890 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_shift 0
2891 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_WRITE_ADDR_63_32(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_shift)
2895 ** Definitions for SDMA_PKT_TRAP packet
2898 /*define for HEADER word*/
2899 /*define for op field*/
2900 #define SDMA_PKT_TRAP_HEADER_op_offset 0
2901 #define SDMA_PKT_TRAP_HEADER_op_mask 0x000000FF
2902 #define SDMA_PKT_TRAP_HEADER_op_shift 0
2903 #define SDMA_PKT_TRAP_HEADER_OP(x) (((x) & SDMA_PKT_TRAP_HEADER_op_mask) << SDMA_PKT_TRAP_HEADER_op_shift)
2905 /*define for sub_op field*/
2906 #define SDMA_PKT_TRAP_HEADER_sub_op_offset 0
2907 #define SDMA_PKT_TRAP_HEADER_sub_op_mask 0x000000FF
2908 #define SDMA_PKT_TRAP_HEADER_sub_op_shift 8
2909 #define SDMA_PKT_TRAP_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TRAP_HEADER_sub_op_mask) << SDMA_PKT_TRAP_HEADER_sub_op_shift)
2911 /*define for INT_CONTEXT word*/
2912 /*define for int_context field*/
2913 #define SDMA_PKT_TRAP_INT_CONTEXT_int_context_offset 1
2914 #define SDMA_PKT_TRAP_INT_CONTEXT_int_context_mask 0x0FFFFFFF
2915 #define SDMA_PKT_TRAP_INT_CONTEXT_int_context_shift 0
2916 #define SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(x) (((x) & SDMA_PKT_TRAP_INT_CONTEXT_int_context_mask) << SDMA_PKT_TRAP_INT_CONTEXT_int_context_shift)
2920 ** Definitions for SDMA_PKT_DUMMY_TRAP packet
2923 /*define for HEADER word*/
2924 /*define for op field*/
2925 #define SDMA_PKT_DUMMY_TRAP_HEADER_op_offset 0
2926 #define SDMA_PKT_DUMMY_TRAP_HEADER_op_mask 0x000000FF
2927 #define SDMA_PKT_DUMMY_TRAP_HEADER_op_shift 0
2928 #define SDMA_PKT_DUMMY_TRAP_HEADER_OP(x) (((x) & SDMA_PKT_DUMMY_TRAP_HEADER_op_mask) << SDMA_PKT_DUMMY_TRAP_HEADER_op_shift)
2930 /*define for sub_op field*/
2931 #define SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_offset 0
2932 #define SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_mask 0x000000FF
2933 #define SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_shift 8
2934 #define SDMA_PKT_DUMMY_TRAP_HEADER_SUB_OP(x) (((x) & SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_mask) << SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_shift)
2936 /*define for INT_CONTEXT word*/
2937 /*define for int_context field*/
2938 #define SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_offset 1
2939 #define SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_mask 0x0FFFFFFF
2940 #define SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_shift 0
2941 #define SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_INT_CONTEXT(x) (((x) & SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_mask) << SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_shift)
2945 ** Definitions for SDMA_PKT_NOP packet
2948 /*define for HEADER word*/
2949 /*define for op field*/
2950 #define SDMA_PKT_NOP_HEADER_op_offset 0
2951 #define SDMA_PKT_NOP_HEADER_op_mask 0x000000FF
2952 #define SDMA_PKT_NOP_HEADER_op_shift 0
2953 #define SDMA_PKT_NOP_HEADER_OP(x) (((x) & SDMA_PKT_NOP_HEADER_op_mask) << SDMA_PKT_NOP_HEADER_op_shift)
2955 /*define for sub_op field*/
2956 #define SDMA_PKT_NOP_HEADER_sub_op_offset 0
2957 #define SDMA_PKT_NOP_HEADER_sub_op_mask 0x000000FF
2958 #define SDMA_PKT_NOP_HEADER_sub_op_shift 8
2959 #define SDMA_PKT_NOP_HEADER_SUB_OP(x) (((x) & SDMA_PKT_NOP_HEADER_sub_op_mask) << SDMA_PKT_NOP_HEADER_sub_op_shift)
2961 /*define for count field*/
2962 #define SDMA_PKT_NOP_HEADER_count_offset 0
2963 #define SDMA_PKT_NOP_HEADER_count_mask 0x00003FFF
2964 #define SDMA_PKT_NOP_HEADER_count_shift 16
2965 #define SDMA_PKT_NOP_HEADER_COUNT(x) (((x) & SDMA_PKT_NOP_HEADER_count_mask) << SDMA_PKT_NOP_HEADER_count_shift)
2967 /*define for DATA0 word*/
2968 /*define for data0 field*/
2969 #define SDMA_PKT_NOP_DATA0_data0_offset 1
2970 #define SDMA_PKT_NOP_DATA0_data0_mask 0xFFFFFFFF
2971 #define SDMA_PKT_NOP_DATA0_data0_shift 0
2972 #define SDMA_PKT_NOP_DATA0_DATA0(x) (((x) & SDMA_PKT_NOP_DATA0_data0_mask) << SDMA_PKT_NOP_DATA0_data0_shift)
2976 ** Definitions for SDMA_AQL_PKT_HEADER packet
2979 /*define for HEADER word*/
2980 /*define for format field*/
2981 #define SDMA_AQL_PKT_HEADER_HEADER_format_offset 0
2982 #define SDMA_AQL_PKT_HEADER_HEADER_format_mask 0x000000FF
2983 #define SDMA_AQL_PKT_HEADER_HEADER_format_shift 0
2984 #define SDMA_AQL_PKT_HEADER_HEADER_FORMAT(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_format_mask) << SDMA_AQL_PKT_HEADER_HEADER_format_shift)
2986 /*define for barrier field*/
2987 #define SDMA_AQL_PKT_HEADER_HEADER_barrier_offset 0
2988 #define SDMA_AQL_PKT_HEADER_HEADER_barrier_mask 0x00000001
2989 #define SDMA_AQL_PKT_HEADER_HEADER_barrier_shift 8
2990 #define SDMA_AQL_PKT_HEADER_HEADER_BARRIER(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_barrier_mask) << SDMA_AQL_PKT_HEADER_HEADER_barrier_shift)
2992 /*define for acquire_fence_scope field*/
2993 #define SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_offset 0
2994 #define SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_mask 0x00000003
2995 #define SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_shift 9
2996 #define SDMA_AQL_PKT_HEADER_HEADER_ACQUIRE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_mask) << SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_shift)
2998 /*define for release_fence_scope field*/
2999 #define SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_offset 0
3000 #define SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_mask 0x00000003
3001 #define SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_shift 11
3002 #define SDMA_AQL_PKT_HEADER_HEADER_RELEASE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_mask) << SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_shift)
3004 /*define for reserved field*/
3005 #define SDMA_AQL_PKT_HEADER_HEADER_reserved_offset 0
3006 #define SDMA_AQL_PKT_HEADER_HEADER_reserved_mask 0x00000007
3007 #define SDMA_AQL_PKT_HEADER_HEADER_reserved_shift 13
3008 #define SDMA_AQL_PKT_HEADER_HEADER_RESERVED(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_reserved_mask) << SDMA_AQL_PKT_HEADER_HEADER_reserved_shift)
3010 /*define for op field*/
3011 #define SDMA_AQL_PKT_HEADER_HEADER_op_offset 0
3012 #define SDMA_AQL_PKT_HEADER_HEADER_op_mask 0x0000000F
3013 #define SDMA_AQL_PKT_HEADER_HEADER_op_shift 16
3014 #define SDMA_AQL_PKT_HEADER_HEADER_OP(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_op_mask) << SDMA_AQL_PKT_HEADER_HEADER_op_shift)
3016 /*define for subop field*/
3017 #define SDMA_AQL_PKT_HEADER_HEADER_subop_offset 0
3018 #define SDMA_AQL_PKT_HEADER_HEADER_subop_mask 0x00000007
3019 #define SDMA_AQL_PKT_HEADER_HEADER_subop_shift 20
3020 #define SDMA_AQL_PKT_HEADER_HEADER_SUBOP(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_subop_mask) << SDMA_AQL_PKT_HEADER_HEADER_subop_shift)
3024 ** Definitions for SDMA_AQL_PKT_COPY_LINEAR packet
3027 /*define for HEADER word*/
3028 /*define for format field*/
3029 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_offset 0
3030 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_mask 0x000000FF
3031 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_shift 0
3032 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_FORMAT(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_shift)
3034 /*define for barrier field*/
3035 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_offset 0
3036 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_mask 0x00000001
3037 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_shift 8
3038 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_BARRIER(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_shift)
3040 /*define for acquire_fence_scope field*/
3041 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_offset 0
3042 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_mask 0x00000003
3043 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_shift 9
3044 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_ACQUIRE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_shift)
3046 /*define for release_fence_scope field*/
3047 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_offset 0
3048 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_mask 0x00000003
3049 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_shift 11
3050 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_RELEASE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_shift)
3052 /*define for reserved field*/
3053 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_offset 0
3054 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_mask 0x00000007
3055 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_shift 13
3056 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_RESERVED(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_shift)
3058 /*define for op field*/
3059 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_offset 0
3060 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_mask 0x0000000F
3061 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_shift 16
3062 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_OP(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_shift)
3064 /*define for subop field*/
3065 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_offset 0
3066 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_mask 0x00000007
3067 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_shift 20
3068 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_SUBOP(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_shift)
3070 /*define for RESERVED_DW1 word*/
3071 /*define for reserved_dw1 field*/
3072 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_offset 1
3073 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_mask 0xFFFFFFFF
3074 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_shift 0
3075 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_RESERVED_DW1(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_shift)
3077 /*define for RETURN_ADDR_LO word*/
3078 /*define for return_addr_31_0 field*/
3079 #define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_offset 2
3080 #define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_mask 0xFFFFFFFF
3081 #define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_shift 0
3082 #define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_RETURN_ADDR_31_0(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_mask) << SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_shift)
3084 /*define for RETURN_ADDR_HI word*/
3085 /*define for return_addr_63_32 field*/
3086 #define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_offset 3
3087 #define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_mask 0xFFFFFFFF
3088 #define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_shift 0
3089 #define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_RETURN_ADDR_63_32(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_mask) << SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_shift)
3091 /*define for COUNT word*/
3092 /*define for count field*/
3093 #define SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_offset 4
3094 #define SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_mask 0x003FFFFF
3095 #define SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_shift 0
3096 #define SDMA_AQL_PKT_COPY_LINEAR_COUNT_COUNT(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_mask) << SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_shift)
3098 /*define for PARAMETER word*/
3099 /*define for dst_sw field*/
3100 #define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset 5
3101 #define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask 0x00000003
3102 #define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift 16
3103 #define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_DST_SW(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask) << SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift)
3105 /*define for src_sw field*/
3106 #define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_offset 5
3107 #define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_mask 0x00000003
3108 #define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_shift 24
3109 #define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_SRC_SW(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_mask) << SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_shift)
3111 /*define for SRC_ADDR_LO word*/
3112 /*define for src_addr_31_0 field*/
3113 #define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset 6
3114 #define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF
3115 #define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift 0
3116 #define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift)
3118 /*define for SRC_ADDR_HI word*/
3119 /*define for src_addr_63_32 field*/
3120 #define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset 7
3121 #define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF
3122 #define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift 0
3123 #define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift)
3125 /*define for DST_ADDR_LO word*/
3126 /*define for dst_addr_31_0 field*/
3127 #define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset 8
3128 #define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF
3129 #define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift 0
3130 #define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift)
3132 /*define for DST_ADDR_HI word*/
3133 /*define for dst_addr_63_32 field*/
3134 #define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset 9
3135 #define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF
3136 #define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift 0
3137 #define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift)
3139 /*define for RESERVED_DW10 word*/
3140 /*define for reserved_dw10 field*/
3141 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_offset 10
3142 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_mask 0xFFFFFFFF
3143 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_shift 0
3144 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_RESERVED_DW10(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_shift)
3146 /*define for RESERVED_DW11 word*/
3147 /*define for reserved_dw11 field*/
3148 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_offset 11
3149 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_mask 0xFFFFFFFF
3150 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_shift 0
3151 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_RESERVED_DW11(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_shift)
3153 /*define for RESERVED_DW12 word*/
3154 /*define for reserved_dw12 field*/
3155 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_offset 12
3156 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_mask 0xFFFFFFFF
3157 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_shift 0
3158 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_RESERVED_DW12(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_shift)
3160 /*define for RESERVED_DW13 word*/
3161 /*define for reserved_dw13 field*/
3162 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_offset 13
3163 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_mask 0xFFFFFFFF
3164 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_shift 0
3165 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_RESERVED_DW13(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_shift)
3167 /*define for COMPLETION_SIGNAL_LO word*/
3168 /*define for completion_signal_31_0 field*/
3169 #define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset 14
3170 #define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask 0xFFFFFFFF
3171 #define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift 0
3172 #define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_COMPLETION_SIGNAL_31_0(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask) << SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift)
3174 /*define for COMPLETION_SIGNAL_HI word*/
3175 /*define for completion_signal_63_32 field*/
3176 #define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset 15
3177 #define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask 0xFFFFFFFF
3178 #define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift 0
3179 #define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_COMPLETION_SIGNAL_63_32(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask) << SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift)
3183 ** Definitions for SDMA_AQL_PKT_BARRIER_OR packet
3186 /*define for HEADER word*/
3187 /*define for format field*/
3188 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_format_offset 0
3189 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_format_mask 0x000000FF
3190 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_format_shift 0
3191 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_FORMAT(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_format_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_format_shift)
3193 /*define for barrier field*/
3194 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_offset 0
3195 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_mask 0x00000001
3196 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_shift 8
3197 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_BARRIER(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_shift)
3199 /*define for acquire_fence_scope field*/
3200 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_offset 0
3201 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_mask 0x00000003
3202 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_shift 9
3203 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_ACQUIRE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_shift)
3205 /*define for release_fence_scope field*/
3206 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_offset 0
3207 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_mask 0x00000003
3208 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_shift 11
3209 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_RELEASE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_shift)
3211 /*define for reserved field*/
3212 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_offset 0
3213 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_mask 0x00000007
3214 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_shift 13
3215 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_RESERVED(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_shift)
3217 /*define for op field*/
3218 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_op_offset 0
3219 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_op_mask 0x0000000F
3220 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_op_shift 16
3221 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_OP(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_op_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_op_shift)
3223 /*define for subop field*/
3224 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_offset 0
3225 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_mask 0x00000007
3226 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_shift 20
3227 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_SUBOP(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_shift)
3229 /*define for RESERVED_DW1 word*/
3230 /*define for reserved_dw1 field*/
3231 #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_offset 1
3232 #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_mask 0xFFFFFFFF
3233 #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_shift 0
3234 #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_RESERVED_DW1(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_mask) << SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_shift)
3236 /*define for DEPENDENT_ADDR_0_LO word*/
3237 /*define for dependent_addr_0_31_0 field*/
3238 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_offset 2
3239 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_mask 0xFFFFFFFF
3240 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_shift 0
3241 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_DEPENDENT_ADDR_0_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_shift)
3243 /*define for DEPENDENT_ADDR_0_HI word*/
3244 /*define for dependent_addr_0_63_32 field*/
3245 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_offset 3
3246 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_mask 0xFFFFFFFF
3247 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_shift 0
3248 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_DEPENDENT_ADDR_0_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_shift)
3250 /*define for DEPENDENT_ADDR_1_LO word*/
3251 /*define for dependent_addr_1_31_0 field*/
3252 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_offset 4
3253 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_mask 0xFFFFFFFF
3254 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_shift 0
3255 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_DEPENDENT_ADDR_1_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_shift)
3257 /*define for DEPENDENT_ADDR_1_HI word*/
3258 /*define for dependent_addr_1_63_32 field*/
3259 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_offset 5
3260 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_mask 0xFFFFFFFF
3261 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_shift 0
3262 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_DEPENDENT_ADDR_1_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_shift)
3264 /*define for DEPENDENT_ADDR_2_LO word*/
3265 /*define for dependent_addr_2_31_0 field*/
3266 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_offset 6
3267 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_mask 0xFFFFFFFF
3268 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_shift 0
3269 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_DEPENDENT_ADDR_2_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_shift)
3271 /*define for DEPENDENT_ADDR_2_HI word*/
3272 /*define for dependent_addr_2_63_32 field*/
3273 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_offset 7
3274 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_mask 0xFFFFFFFF
3275 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_shift 0
3276 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_DEPENDENT_ADDR_2_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_shift)
3278 /*define for DEPENDENT_ADDR_3_LO word*/
3279 /*define for dependent_addr_3_31_0 field*/
3280 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_offset 8
3281 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_mask 0xFFFFFFFF
3282 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_shift 0
3283 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_DEPENDENT_ADDR_3_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_shift)
3285 /*define for DEPENDENT_ADDR_3_HI word*/
3286 /*define for dependent_addr_3_63_32 field*/
3287 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_offset 9
3288 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_mask 0xFFFFFFFF
3289 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_shift 0
3290 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_DEPENDENT_ADDR_3_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_shift)
3292 /*define for DEPENDENT_ADDR_4_LO word*/
3293 /*define for dependent_addr_4_31_0 field*/
3294 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_offset 10
3295 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_mask 0xFFFFFFFF
3296 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_shift 0
3297 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_DEPENDENT_ADDR_4_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_shift)
3299 /*define for DEPENDENT_ADDR_4_HI word*/
3300 /*define for dependent_addr_4_63_32 field*/
3301 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_offset 11
3302 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_mask 0xFFFFFFFF
3303 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_shift 0
3304 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_DEPENDENT_ADDR_4_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_shift)
3306 /*define for RESERVED_DW12 word*/
3307 /*define for reserved_dw12 field*/
3308 #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_offset 12
3309 #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_mask 0xFFFFFFFF
3310 #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_shift 0
3311 #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_RESERVED_DW12(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_mask) << SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_shift)
3313 /*define for RESERVED_DW13 word*/
3314 /*define for reserved_dw13 field*/
3315 #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_offset 13
3316 #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_mask 0xFFFFFFFF
3317 #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_shift 0
3318 #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_RESERVED_DW13(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_mask) << SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_shift)
3320 /*define for COMPLETION_SIGNAL_LO word*/
3321 /*define for completion_signal_31_0 field*/
3322 #define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset 14
3323 #define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask 0xFFFFFFFF
3324 #define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift 0
3325 #define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_COMPLETION_SIGNAL_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift)
3327 /*define for COMPLETION_SIGNAL_HI word*/
3328 /*define for completion_signal_63_32 field*/
3329 #define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset 15
3330 #define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask 0xFFFFFFFF
3331 #define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift 0
3332 #define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_COMPLETION_SIGNAL_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift)
3335 #endif /* __SDMA_PKT_OPEN_H_ */