drivers/gpu/drm/amd/amdkfd/kfd_dbgmgr.h

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #ifndef KFD_DBGMGR_H_
  25 #define KFD_DBGMGR_H_
  26
  27 #include "kfd_priv.h"
  28
  29 /* must align with hsakmttypes definition */
  30 #pragma pack(push, 4)
  31
  32 enum HSA_DBG_WAVEOP {
  33         HSA_DBG_WAVEOP_HALT = 1,   /* Halts a wavefront */
  34         HSA_DBG_WAVEOP_RESUME = 2, /* Resumes a wavefront */
  35         HSA_DBG_WAVEOP_KILL = 3,   /* Kills a wavefront */
  36         HSA_DBG_WAVEOP_DEBUG = 4,  /* Causes wavefront to enter dbg mode */
  37         HSA_DBG_WAVEOP_TRAP = 5,   /* Causes wavefront to take a trap */
  38         HSA_DBG_NUM_WAVEOP = 5,
  39         HSA_DBG_MAX_WAVEOP = 0xFFFFFFFF
  40 };
  41
  42 enum HSA_DBG_WAVEMODE {
  43         /* send command to a single wave */
  44         HSA_DBG_WAVEMODE_SINGLE = 0,
  45         /*
  46          * Broadcast to all wavefronts of all processes is not
  47          * supported for HSA user mode
  48          */
  49
  50         /* send to waves within current process */
  51         HSA_DBG_WAVEMODE_BROADCAST_PROCESS = 2,
  52         /* send to waves within current process on CU  */
  53         HSA_DBG_WAVEMODE_BROADCAST_PROCESS_CU = 3,
  54         HSA_DBG_NUM_WAVEMODE = 3,
  55         HSA_DBG_MAX_WAVEMODE = 0xFFFFFFFF
  56 };
  57
  58 enum HSA_DBG_WAVEMSG_TYPE {
  59         HSA_DBG_WAVEMSG_AUTO = 0,
  60         HSA_DBG_WAVEMSG_USER = 1,
  61         HSA_DBG_WAVEMSG_ERROR = 2,
  62         HSA_DBG_NUM_WAVEMSG,
  63         HSA_DBG_MAX_WAVEMSG = 0xFFFFFFFF
  64 };
  65
  66 enum HSA_DBG_WATCH_MODE {
  67         HSA_DBG_WATCH_READ = 0,         /* Read operations only */
  68         HSA_DBG_WATCH_NONREAD = 1,      /* Write or Atomic operations only */
  69         HSA_DBG_WATCH_ATOMIC = 2,       /* Atomic Operations only */
  70         HSA_DBG_WATCH_ALL = 3,          /* Read, Write or Atomic operations */
  71         HSA_DBG_WATCH_NUM,
  72         HSA_DBG_WATCH_SIZE = 0xFFFFFFFF
  73 };
  74
  75 /* This structure is hardware specific and may change in the future */
  76 struct HsaDbgWaveMsgAMDGen2 {
  77         union {
  78                 struct ui32 {
  79                         uint32_t UserData:8;    /* user data */
  80                         uint32_t ShaderArray:1; /* Shader array */
  81                         uint32_t Priv:1;        /* Privileged */
  82                         uint32_t Reserved0:4;   /* Reserved, should be 0 */
  83                         uint32_t WaveId:4;      /* wave id */
  84                         uint32_t SIMD:2;        /* SIMD id */
  85                         uint32_t HSACU:4;       /* Compute unit */
  86                         uint32_t ShaderEngine:2;/* Shader engine */
  87                         uint32_t MessageType:2; /* see HSA_DBG_WAVEMSG_TYPE */
  88                         uint32_t Reserved1:4;   /* Reserved, should be 0 */
  89                 } ui32;
  90                 uint32_t Value;
  91         };
  92         uint32_t Reserved2;
  93 };
  94
  95 union HsaDbgWaveMessageAMD {
  96         struct HsaDbgWaveMsgAMDGen2 WaveMsgInfoGen2;
  97         /* for future HsaDbgWaveMsgAMDGen3; */
  98 };
  99
 100 struct HsaDbgWaveMessage {
 101         void *MemoryVA;         /* ptr to associated host-accessible data */
 102         union HsaDbgWaveMessageAMD DbgWaveMsg;
 103 };
 104
 105 /*
 106  * TODO: This definitions to be MOVED to kfd_event, once it is implemented.
 107  *
 108  * HSA sync primitive, Event and HW Exception notification API definitions.
 109  * The API functions allow the runtime to define a so-called sync-primitive,
 110  * a SW object combining a user-mode provided "syncvar" and a scheduler event
 111  * that can be signaled through a defined GPU interrupt. A syncvar is
 112  * a process virtual memory location of a certain size that can be accessed
 113  * by CPU and GPU shader code within the process to set and query the content
 114  * within that memory. The definition of the content is determined by the HSA
 115  * runtime and potentially GPU shader code interfacing with the HSA runtime.
 116  * The syncvar values may be commonly written through an PM4 WRITE_DATA packet
 117  * in the user mode instruction stream. The OS scheduler event is typically
 118  * associated and signaled by an interrupt issued by the GPU, but other HSA
 119  * system interrupt conditions from other HW (e.g. IOMMUv2) may be surfaced
 120  * by the KFD by this mechanism, too.
 121  */
 122
 123 /* these are the new definitions for events */
 124 enum HSA_EVENTTYPE {
 125         HSA_EVENTTYPE_SIGNAL = 0,       /* user-mode generated GPU signal */
 126         HSA_EVENTTYPE_NODECHANGE = 1,   /* HSA node change (attach/detach) */
 127         HSA_EVENTTYPE_DEVICESTATECHANGE = 2,    /* HSA device state change
 128                                                  * (start/stop)
 129                                                  */
 130         HSA_EVENTTYPE_HW_EXCEPTION = 3, /* GPU shader exception event */
 131         HSA_EVENTTYPE_SYSTEM_EVENT = 4, /* GPU SYSCALL with parameter info */
 132         HSA_EVENTTYPE_DEBUG_EVENT = 5,  /* GPU signal for debugging */
 133         HSA_EVENTTYPE_PROFILE_EVENT = 6,/* GPU signal for profiling */
 134         HSA_EVENTTYPE_QUEUE_EVENT = 7,  /* GPU signal queue idle state
 135                                          * (EOP pm4)
 136                                          */
 137         /* ...  */
 138         HSA_EVENTTYPE_MAXID,
 139         HSA_EVENTTYPE_TYPE_SIZE = 0xFFFFFFFF
 140 };
 141
 142 /* Sub-definitions for various event types: Syncvar */
 143 struct HsaSyncVar {
 144         union SyncVar {
 145                 void *UserData; /* pointer to user mode data */
 146                 uint64_t UserDataPtrValue; /* 64bit compatibility of value */
 147         } SyncVar;
 148         uint64_t SyncVarSize;
 149 };
 150
 151 /* Sub-definitions for various event types: NodeChange */
 152
 153 enum HSA_EVENTTYPE_NODECHANGE_FLAGS {
 154         HSA_EVENTTYPE_NODECHANGE_ADD = 0,
 155         HSA_EVENTTYPE_NODECHANGE_REMOVE = 1,
 156         HSA_EVENTTYPE_NODECHANGE_SIZE = 0xFFFFFFFF
 157 };
 158
 159 struct HsaNodeChange {
 160         /* HSA node added/removed on the platform */
 161         enum HSA_EVENTTYPE_NODECHANGE_FLAGS Flags;
 162 };
 163
 164 /* Sub-definitions for various event types: DeviceStateChange */
 165 enum HSA_EVENTTYPE_DEVICESTATECHANGE_FLAGS {
 166         /* device started (and available) */
 167         HSA_EVENTTYPE_DEVICESTATUSCHANGE_START = 0,
 168         /* device stopped (i.e. unavailable) */
 169         HSA_EVENTTYPE_DEVICESTATUSCHANGE_STOP = 1,
 170         HSA_EVENTTYPE_DEVICESTATUSCHANGE_SIZE = 0xFFFFFFFF
 171 };
 172
 173 enum HSA_DEVICE {
 174         HSA_DEVICE_CPU = 0,
 175         HSA_DEVICE_GPU = 1,
 176         MAX_HSA_DEVICE = 2
 177 };
 178
 179 struct HsaDeviceStateChange {
 180         uint32_t NodeId;        /* F-NUMA node that contains the device */
 181         enum HSA_DEVICE Device; /* device type: GPU or CPU */
 182         enum HSA_EVENTTYPE_DEVICESTATECHANGE_FLAGS Flags; /* event flags */
 183 };
 184
 185 struct HsaEventData {
 186         enum HSA_EVENTTYPE EventType; /* event type */
 187         union EventData {
 188                 /*
 189                  * return data associated with HSA_EVENTTYPE_SIGNAL
 190                  * and other events
 191                  */
 192                 struct HsaSyncVar SyncVar;
 193
 194                 /* data associated with HSA_EVENTTYPE_NODE_CHANGE */
 195                 struct HsaNodeChange NodeChangeState;
 196
 197                 /* data associated with HSA_EVENTTYPE_DEVICE_STATE_CHANGE */
 198                 struct HsaDeviceStateChange DeviceState;
 199         } EventData;
 200
 201         /* the following data entries are internal to the KFD & thunk itself */
 202
 203         /* internal thunk store for Event data (OsEventHandle) */
 204         uint64_t HWData1;
 205         /* internal thunk store for Event data (HWAddress) */
 206         uint64_t HWData2;
 207         /* internal thunk store for Event data (HWData) */
 208         uint32_t HWData3;
 209 };
 210
 211 struct HsaEventDescriptor {
 212         /* event type to allocate */
 213         enum HSA_EVENTTYPE EventType;
 214         /* H-NUMA node containing GPU device that is event source */
 215         uint32_t NodeId;
 216         /* pointer to user mode syncvar data, syncvar->UserDataPtrValue
 217          * may be NULL
 218          */
 219         struct HsaSyncVar SyncVar;
 220 };
 221
 222 struct HsaEvent {
 223         uint32_t EventId;
 224         struct HsaEventData EventData;
 225 };
 226
 227 #pragma pack(pop)
 228
 229 enum DBGDEV_TYPE {
 230         DBGDEV_TYPE_ILLEGAL = 0,
 231         DBGDEV_TYPE_NODIQ = 1,
 232         DBGDEV_TYPE_DIQ = 2,
 233         DBGDEV_TYPE_TEST = 3
 234 };
 235
 236 struct dbg_address_watch_info {
 237         struct kfd_process *process;
 238         enum HSA_DBG_WATCH_MODE *watch_mode;
 239         uint64_t *watch_address;
 240         uint64_t *watch_mask;
 241         struct HsaEvent *watch_event;
 242         uint32_t num_watch_points;
 243 };
 244
 245 struct dbg_wave_control_info {
 246         struct kfd_process *process;
 247         uint32_t trapId;
 248         enum HSA_DBG_WAVEOP operand;
 249         enum HSA_DBG_WAVEMODE mode;
 250         struct HsaDbgWaveMessage dbgWave_msg;
 251 };
 252
 253 struct kfd_dbgdev {
 254
 255         /* The device that owns this data. */
 256         struct kfd_dev *dev;
 257
 258         /* kernel queue for DIQ */
 259         struct kernel_queue *kq;
 260
 261         /* a pointer to the pqm of the calling process */
 262         struct process_queue_manager *pqm;
 263
 264         /* type of debug device ( DIQ, non DIQ, etc. ) */
 265         enum DBGDEV_TYPE type;
 266
 267         /* virtualized function pointers to device dbg */
 268         int (*dbgdev_register)(struct kfd_dbgdev *dbgdev);
 269         int (*dbgdev_unregister)(struct kfd_dbgdev *dbgdev);
 270         int (*dbgdev_address_watch)(struct kfd_dbgdev *dbgdev,
 271                                 struct dbg_address_watch_info *adw_info);
 272         int (*dbgdev_wave_control)(struct kfd_dbgdev *dbgdev,
 273                                 struct dbg_wave_control_info *wac_info);
 274
 275 };
 276
 277 struct kfd_dbgmgr {
 278         unsigned int pasid;
 279         struct kfd_dev *dev;
 280         struct kfd_dbgdev *dbgdev;
 281 };
 282
 283 /* prototypes for debug manager functions */
 284 struct mutex *kfd_get_dbgmgr_mutex(void);
 285 void kfd_dbgmgr_destroy(struct kfd_dbgmgr *pmgr);
 286 bool kfd_dbgmgr_create(struct kfd_dbgmgr **ppmgr, struct kfd_dev *pdev);
 287 long kfd_dbgmgr_register(struct kfd_dbgmgr *pmgr, struct kfd_process *p);
 288 long kfd_dbgmgr_unregister(struct kfd_dbgmgr *pmgr, struct kfd_process *p);
 289 long kfd_dbgmgr_wave_control(struct kfd_dbgmgr *pmgr,
 290                                 struct dbg_wave_control_info *wac_info);
 291 long kfd_dbgmgr_address_watch(struct kfd_dbgmgr *pmgr,
 292                         struct dbg_address_watch_info *adw_info);
 293 #endif /* KFD_DBGMGR_H_ */