drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/printk.h>
  25 #include <linux/slab.h>
  26 #include <linux/mm_types.h>
  27
  28 #include "kfd_priv.h"
  29 #include "kfd_mqd_manager.h"
  30 #include "vi_structs.h"
  31 #include "gca/gfx_8_0_sh_mask.h"
  32 #include "gca/gfx_8_0_enum.h"
  33 #include "oss/oss_3_0_sh_mask.h"
  34 #define CP_MQD_CONTROL__PRIV_STATE__SHIFT 0x8
  35
  36 static inline struct vi_mqd *get_mqd(void *mqd)
  37 {
  38         return (struct vi_mqd *)mqd;
  39 }
  40
  41 static inline struct vi_sdma_mqd *get_sdma_mqd(void *mqd)
  42 {
  43         return (struct vi_sdma_mqd *)mqd;
  44 }
  45
  46 static void update_cu_mask(struct mqd_manager *mm, void *mqd,
  47                         struct queue_properties *q)
  48 {
  49         struct vi_mqd *m;
  50         uint32_t se_mask[4] = {0}; /* 4 is the max # of SEs */
  51
  52         if (q->cu_mask_count == 0)
  53                 return;
  54
  55         mqd_symmetrically_map_cu_mask(mm,
  56                 q->cu_mask, q->cu_mask_count, se_mask);
  57
  58         m = get_mqd(mqd);
  59         m->compute_static_thread_mgmt_se0 = se_mask[0];
  60         m->compute_static_thread_mgmt_se1 = se_mask[1];
  61         m->compute_static_thread_mgmt_se2 = se_mask[2];
  62         m->compute_static_thread_mgmt_se3 = se_mask[3];
  63
  64         pr_debug("Update cu mask to %#x %#x %#x %#x\n",
  65                 m->compute_static_thread_mgmt_se0,
  66                 m->compute_static_thread_mgmt_se1,
  67                 m->compute_static_thread_mgmt_se2,
  68                 m->compute_static_thread_mgmt_se3);
  69 }
  70
  71 static int init_mqd(struct mqd_manager *mm, void **mqd,
  72                         struct kfd_mem_obj **mqd_mem_obj, uint64_t *gart_addr,
  73                         struct queue_properties *q)
  74 {
  75         int retval;
  76         uint64_t addr;
  77         struct vi_mqd *m;
  78
  79         retval = kfd_gtt_sa_allocate(mm->dev, sizeof(struct vi_mqd),
  80                         mqd_mem_obj);
  81         if (retval != 0)
  82                 return -ENOMEM;
  83
  84         m = (struct vi_mqd *) (*mqd_mem_obj)->cpu_ptr;
  85         addr = (*mqd_mem_obj)->gpu_addr;
  86
  87         memset(m, 0, sizeof(struct vi_mqd));
  88
  89         m->header = 0xC0310800;
  90         m->compute_pipelinestat_enable = 1;
  91         m->compute_static_thread_mgmt_se0 = 0xFFFFFFFF;
  92         m->compute_static_thread_mgmt_se1 = 0xFFFFFFFF;
  93         m->compute_static_thread_mgmt_se2 = 0xFFFFFFFF;
  94         m->compute_static_thread_mgmt_se3 = 0xFFFFFFFF;
  95
  96         m->cp_hqd_persistent_state = CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK |
  97                         0x53 << CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT;
  98
  99         m->cp_mqd_control = 1 << CP_MQD_CONTROL__PRIV_STATE__SHIFT |
 100                         MTYPE_UC << CP_MQD_CONTROL__MTYPE__SHIFT;
 101
 102         m->cp_mqd_base_addr_lo        = lower_32_bits(addr);
 103         m->cp_mqd_base_addr_hi        = upper_32_bits(addr);
 104
 105         m->cp_hqd_quantum = 1 << CP_HQD_QUANTUM__QUANTUM_EN__SHIFT |
 106                         1 << CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT |
 107                         10 << CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT;
 108
 109         m->cp_hqd_pipe_priority = 1;
 110         m->cp_hqd_queue_priority = 15;
 111
 112         m->cp_hqd_eop_rptr = 1 << CP_HQD_EOP_RPTR__INIT_FETCHER__SHIFT;
 113
 114         if (q->format == KFD_QUEUE_FORMAT_AQL)
 115                 m->cp_hqd_iq_rptr = 1;
 116
 117         if (q->tba_addr) {
 118                 m->compute_tba_lo = lower_32_bits(q->tba_addr >> 8);
 119                 m->compute_tba_hi = upper_32_bits(q->tba_addr >> 8);
 120                 m->compute_tma_lo = lower_32_bits(q->tma_addr >> 8);
 121                 m->compute_tma_hi = upper_32_bits(q->tma_addr >> 8);
 122                 m->compute_pgm_rsrc2 |=
 123                         (1 << COMPUTE_PGM_RSRC2__TRAP_PRESENT__SHIFT);
 124         }
 125
 126         if (mm->dev->cwsr_enabled && q->ctx_save_restore_area_address) {
 127                 m->cp_hqd_persistent_state |=
 128                         (1 << CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT);
 129                 m->cp_hqd_ctx_save_base_addr_lo =
 130                         lower_32_bits(q->ctx_save_restore_area_address);
 131                 m->cp_hqd_ctx_save_base_addr_hi =
 132                         upper_32_bits(q->ctx_save_restore_area_address);
 133                 m->cp_hqd_ctx_save_size = q->ctx_save_restore_area_size;
 134                 m->cp_hqd_cntl_stack_size = q->ctl_stack_size;
 135                 m->cp_hqd_cntl_stack_offset = q->ctl_stack_size;
 136                 m->cp_hqd_wg_state_offset = q->ctl_stack_size;
 137         }
 138
 139         *mqd = m;
 140         if (gart_addr)
 141                 *gart_addr = addr;
 142         retval = mm->update_mqd(mm, m, q);
 143
 144         return retval;
 145 }
 146
 147 static int load_mqd(struct mqd_manager *mm, void *mqd,
 148                         uint32_t pipe_id, uint32_t queue_id,
 149                         struct queue_properties *p, struct mm_struct *mms)
 150 {
 151         /* AQL write pointer counts in 64B packets, PM4/CP counts in dwords. */
 152         uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0);
 153         uint32_t wptr_mask = (uint32_t)((p->queue_size / 4) - 1);
 154
 155         return mm->dev->kfd2kgd->hqd_load(mm->dev->kgd, mqd, pipe_id, queue_id,
 156                                           (uint32_t __user *)p->write_ptr,
 157                                           wptr_shift, wptr_mask, mms);
 158 }
 159
 160 static int __update_mqd(struct mqd_manager *mm, void *mqd,
 161                         struct queue_properties *q, unsigned int mtype,
 162                         unsigned int atc_bit)
 163 {
 164         struct vi_mqd *m;
 165
 166         m = get_mqd(mqd);
 167
 168         m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT |
 169                         atc_bit << CP_HQD_PQ_CONTROL__PQ_ATC__SHIFT |
 170                         mtype << CP_HQD_PQ_CONTROL__MTYPE__SHIFT;
 171         m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1;
 172         pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control);
 173
 174         m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8);
 175         m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8);
 176
 177         m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr);
 178         m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr);
 179         m->cp_hqd_pq_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr);
 180         m->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr);
 181
 182         m->cp_hqd_pq_doorbell_control =
 183                 q->doorbell_off <<
 184                         CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT;
 185         pr_debug("cp_hqd_pq_doorbell_control 0x%x\n",
 186                         m->cp_hqd_pq_doorbell_control);
 187
 188         m->cp_hqd_eop_control = atc_bit << CP_HQD_EOP_CONTROL__EOP_ATC__SHIFT |
 189                         mtype << CP_HQD_EOP_CONTROL__MTYPE__SHIFT;
 190
 191         m->cp_hqd_ib_control = atc_bit << CP_HQD_IB_CONTROL__IB_ATC__SHIFT |
 192                         3 << CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT |
 193                         mtype << CP_HQD_IB_CONTROL__MTYPE__SHIFT;
 194
 195         /*
 196          * HW does not clamp this field correctly. Maximum EOP queue size
 197          * is constrained by per-SE EOP done signal count, which is 8-bit.
 198          * Limit is 0xFF EOP entries (= 0x7F8 dwords). CP will not submit
 199          * more than (EOP entry count - 1) so a queue size of 0x800 dwords
 200          * is safe, giving a maximum field value of 0xA.
 201          */
 202         m->cp_hqd_eop_control |= min(0xA,
 203                 order_base_2(q->eop_ring_buffer_size / 4) - 1);
 204         m->cp_hqd_eop_base_addr_lo =
 205                         lower_32_bits(q->eop_ring_buffer_address >> 8);
 206         m->cp_hqd_eop_base_addr_hi =
 207                         upper_32_bits(q->eop_ring_buffer_address >> 8);
 208
 209         m->cp_hqd_iq_timer = atc_bit << CP_HQD_IQ_TIMER__IQ_ATC__SHIFT |
 210                         mtype << CP_HQD_IQ_TIMER__MTYPE__SHIFT;
 211
 212         m->cp_hqd_vmid = q->vmid;
 213
 214         if (q->format == KFD_QUEUE_FORMAT_AQL) {
 215                 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK |
 216                                 2 << CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT;
 217         }
 218
 219         if (mm->dev->cwsr_enabled && q->ctx_save_restore_area_address)
 220                 m->cp_hqd_ctx_save_control =
 221                         atc_bit << CP_HQD_CTX_SAVE_CONTROL__ATC__SHIFT |
 222                         mtype << CP_HQD_CTX_SAVE_CONTROL__MTYPE__SHIFT;
 223
 224         update_cu_mask(mm, mqd, q);
 225
 226         q->is_active = (q->queue_size > 0 &&
 227                         q->queue_address != 0 &&
 228                         q->queue_percent > 0 &&
 229                         !q->is_evicted);
 230
 231         return 0;
 232 }
 233
 234
 235 static int update_mqd(struct mqd_manager *mm, void *mqd,
 236                         struct queue_properties *q)
 237 {
 238         return __update_mqd(mm, mqd, q, MTYPE_CC, 1);
 239 }
 240
 241 static int update_mqd_tonga(struct mqd_manager *mm, void *mqd,
 242                         struct queue_properties *q)
 243 {
 244         return __update_mqd(mm, mqd, q, MTYPE_UC, 0);
 245 }
 246
 247 static int destroy_mqd(struct mqd_manager *mm, void *mqd,
 248                         enum kfd_preempt_type type,
 249                         unsigned int timeout, uint32_t pipe_id,
 250                         uint32_t queue_id)
 251 {
 252         return mm->dev->kfd2kgd->hqd_destroy
 253                 (mm->dev->kgd, mqd, type, timeout,
 254                 pipe_id, queue_id);
 255 }
 256
 257 static void uninit_mqd(struct mqd_manager *mm, void *mqd,
 258                         struct kfd_mem_obj *mqd_mem_obj)
 259 {
 260         kfd_gtt_sa_free(mm->dev, mqd_mem_obj);
 261 }
 262
 263 static bool is_occupied(struct mqd_manager *mm, void *mqd,
 264                         uint64_t queue_address, uint32_t pipe_id,
 265                         uint32_t queue_id)
 266 {
 267         return mm->dev->kfd2kgd->hqd_is_occupied(
 268                 mm->dev->kgd, queue_address,
 269                 pipe_id, queue_id);
 270 }
 271
 272 static int get_wave_state(struct mqd_manager *mm, void *mqd,
 273                           void __user *ctl_stack,
 274                           u32 *ctl_stack_used_size,
 275                           u32 *save_area_used_size)
 276 {
 277         struct vi_mqd *m;
 278
 279         m = get_mqd(mqd);
 280
 281         *ctl_stack_used_size = m->cp_hqd_cntl_stack_size -
 282                 m->cp_hqd_cntl_stack_offset;
 283         *save_area_used_size = m->cp_hqd_wg_state_offset -
 284                 m->cp_hqd_cntl_stack_size;
 285
 286         /* Control stack is not copied to user mode for GFXv8 because
 287          * it's part of the context save area that is already
 288          * accessible to user mode
 289          */
 290
 291         return 0;
 292 }
 293
 294 static int init_mqd_hiq(struct mqd_manager *mm, void **mqd,
 295                         struct kfd_mem_obj **mqd_mem_obj, uint64_t *gart_addr,
 296                         struct queue_properties *q)
 297 {
 298         struct vi_mqd *m;
 299         int retval = init_mqd(mm, mqd, mqd_mem_obj, gart_addr, q);
 300
 301         if (retval != 0)
 302                 return retval;
 303
 304         m = get_mqd(*mqd);
 305
 306         m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT |
 307                         1 << CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT;
 308
 309         return retval;
 310 }
 311
 312 static int update_mqd_hiq(struct mqd_manager *mm, void *mqd,
 313                         struct queue_properties *q)
 314 {
 315         struct vi_mqd *m;
 316         int retval = __update_mqd(mm, mqd, q, MTYPE_UC, 0);
 317
 318         if (retval != 0)
 319                 return retval;
 320
 321         m = get_mqd(mqd);
 322         m->cp_hqd_vmid = q->vmid;
 323         return retval;
 324 }
 325
 326 static int init_mqd_sdma(struct mqd_manager *mm, void **mqd,
 327                 struct kfd_mem_obj **mqd_mem_obj, uint64_t *gart_addr,
 328                 struct queue_properties *q)
 329 {
 330         int retval;
 331         struct vi_sdma_mqd *m;
 332
 333
 334         retval = kfd_gtt_sa_allocate(mm->dev,
 335                         sizeof(struct vi_sdma_mqd),
 336                         mqd_mem_obj);
 337
 338         if (retval != 0)
 339                 return -ENOMEM;
 340
 341         m = (struct vi_sdma_mqd *) (*mqd_mem_obj)->cpu_ptr;
 342
 343         memset(m, 0, sizeof(struct vi_sdma_mqd));
 344
 345         *mqd = m;
 346         if (gart_addr != NULL)
 347                 *gart_addr = (*mqd_mem_obj)->gpu_addr;
 348
 349         retval = mm->update_mqd(mm, m, q);
 350
 351         return retval;
 352 }
 353
 354 static void uninit_mqd_sdma(struct mqd_manager *mm, void *mqd,
 355                 struct kfd_mem_obj *mqd_mem_obj)
 356 {
 357         kfd_gtt_sa_free(mm->dev, mqd_mem_obj);
 358 }
 359
 360 static int load_mqd_sdma(struct mqd_manager *mm, void *mqd,
 361                 uint32_t pipe_id, uint32_t queue_id,
 362                 struct queue_properties *p, struct mm_struct *mms)
 363 {
 364         return mm->dev->kfd2kgd->hqd_sdma_load(mm->dev->kgd, mqd,
 365                                                (uint32_t __user *)p->write_ptr,
 366                                                mms);
 367 }
 368
 369 static int update_mqd_sdma(struct mqd_manager *mm, void *mqd,
 370                 struct queue_properties *q)
 371 {
 372         struct vi_sdma_mqd *m;
 373
 374         m = get_sdma_mqd(mqd);
 375         m->sdmax_rlcx_rb_cntl = order_base_2(q->queue_size / 4)
 376                 << SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT |
 377                 q->vmid << SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT |
 378                 1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT |
 379                 6 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT;
 380
 381         m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8);
 382         m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8);
 383         m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr);
 384         m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr);
 385         m->sdmax_rlcx_doorbell =
 386                 q->doorbell_off << SDMA0_RLC0_DOORBELL__OFFSET__SHIFT;
 387
 388         m->sdmax_rlcx_virtual_addr = q->sdma_vm_addr;
 389
 390         m->sdma_engine_id = q->sdma_engine_id;
 391         m->sdma_queue_id = q->sdma_queue_id;
 392
 393         q->is_active = (q->queue_size > 0 &&
 394                         q->queue_address != 0 &&
 395                         q->queue_percent > 0 &&
 396                         !q->is_evicted);
 397
 398         return 0;
 399 }
 400
 401 /*
 402  *  * preempt type here is ignored because there is only one way
 403  *  * to preempt sdma queue
 404  */
 405 static int destroy_mqd_sdma(struct mqd_manager *mm, void *mqd,
 406                 enum kfd_preempt_type type,
 407                 unsigned int timeout, uint32_t pipe_id,
 408                 uint32_t queue_id)
 409 {
 410         return mm->dev->kfd2kgd->hqd_sdma_destroy(mm->dev->kgd, mqd, timeout);
 411 }
 412
 413 static bool is_occupied_sdma(struct mqd_manager *mm, void *mqd,
 414                 uint64_t queue_address, uint32_t pipe_id,
 415                 uint32_t queue_id)
 416 {
 417         return mm->dev->kfd2kgd->hqd_sdma_is_occupied(mm->dev->kgd, mqd);
 418 }
 419
 420 #if defined(CONFIG_DEBUG_FS)
 421
 422 static int debugfs_show_mqd(struct seq_file *m, void *data)
 423 {
 424         seq_hex_dump(m, "    ", DUMP_PREFIX_OFFSET, 32, 4,
 425                      data, sizeof(struct vi_mqd), false);
 426         return 0;
 427 }
 428
 429 static int debugfs_show_mqd_sdma(struct seq_file *m, void *data)
 430 {
 431         seq_hex_dump(m, "    ", DUMP_PREFIX_OFFSET, 32, 4,
 432                      data, sizeof(struct vi_sdma_mqd), false);
 433         return 0;
 434 }
 435
 436 #endif
 437
 438 struct mqd_manager *mqd_manager_init_vi(enum KFD_MQD_TYPE type,
 439                 struct kfd_dev *dev)
 440 {
 441         struct mqd_manager *mqd;
 442
 443         if (WARN_ON(type >= KFD_MQD_TYPE_MAX))
 444                 return NULL;
 445
 446         mqd = kzalloc(sizeof(*mqd), GFP_KERNEL);
 447         if (!mqd)
 448                 return NULL;
 449
 450         mqd->dev = dev;
 451
 452         switch (type) {
 453         case KFD_MQD_TYPE_CP:
 454         case KFD_MQD_TYPE_COMPUTE:
 455                 mqd->init_mqd = init_mqd;
 456                 mqd->uninit_mqd = uninit_mqd;
 457                 mqd->load_mqd = load_mqd;
 458                 mqd->update_mqd = update_mqd;
 459                 mqd->destroy_mqd = destroy_mqd;
 460                 mqd->is_occupied = is_occupied;
 461                 mqd->get_wave_state = get_wave_state;
 462 #if defined(CONFIG_DEBUG_FS)
 463                 mqd->debugfs_show_mqd = debugfs_show_mqd;
 464 #endif
 465                 break;
 466         case KFD_MQD_TYPE_HIQ:
 467                 mqd->init_mqd = init_mqd_hiq;
 468                 mqd->uninit_mqd = uninit_mqd;
 469                 mqd->load_mqd = load_mqd;
 470                 mqd->update_mqd = update_mqd_hiq;
 471                 mqd->destroy_mqd = destroy_mqd;
 472                 mqd->is_occupied = is_occupied;
 473 #if defined(CONFIG_DEBUG_FS)
 474                 mqd->debugfs_show_mqd = debugfs_show_mqd;
 475 #endif
 476                 break;
 477         case KFD_MQD_TYPE_SDMA:
 478                 mqd->init_mqd = init_mqd_sdma;
 479                 mqd->uninit_mqd = uninit_mqd_sdma;
 480                 mqd->load_mqd = load_mqd_sdma;
 481                 mqd->update_mqd = update_mqd_sdma;
 482                 mqd->destroy_mqd = destroy_mqd_sdma;
 483                 mqd->is_occupied = is_occupied_sdma;
 484 #if defined(CONFIG_DEBUG_FS)
 485                 mqd->debugfs_show_mqd = debugfs_show_mqd_sdma;
 486 #endif
 487                 break;
 488         default:
 489                 kfree(mqd);
 490                 return NULL;
 491         }
 492
 493         return mqd;
 494 }
 495
 496 struct mqd_manager *mqd_manager_init_vi_tonga(enum KFD_MQD_TYPE type,
 497                         struct kfd_dev *dev)
 498 {
 499         struct mqd_manager *mqd;
 500
 501         mqd = mqd_manager_init_vi(type, dev);
 502         if (!mqd)
 503                 return NULL;
 504         if ((type == KFD_MQD_TYPE_CP) || (type == KFD_MQD_TYPE_COMPUTE))
 505                 mqd->update_mqd = update_mqd_tonga;
 506         return mqd;
 507 }