drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #ifndef F32_MES_PM4_PACKETS_H
  25 #define F32_MES_PM4_PACKETS_H
  26
  27 #ifndef PM4_MES_HEADER_DEFINED
  28 #define PM4_MES_HEADER_DEFINED
  29 union PM4_MES_TYPE_3_HEADER {
  30         struct {
  31                 uint32_t reserved1 : 8; /* < reserved */
  32                 uint32_t opcode    : 8; /* < IT opcode */
  33                 uint32_t count     : 14;/* < number of DWORDs - 1 in the
  34                                          *   information body.
  35                                          */
  36                 uint32_t type      : 2; /* < packet identifier.
  37                                          *   It should be 3 for type 3 packets
  38                                          */
  39         };
  40         uint32_t u32All;
  41 };
  42 #endif /* PM4_MES_HEADER_DEFINED */
  43
  44 /*--------------------MES_SET_RESOURCES--------------------*/
  45
  46 #ifndef PM4_MES_SET_RESOURCES_DEFINED
  47 #define PM4_MES_SET_RESOURCES_DEFINED
  48 enum mes_set_resources_queue_type_enum {
  49         queue_type__mes_set_resources__kernel_interface_queue_kiq = 0,
  50         queue_type__mes_set_resources__hsa_interface_queue_hiq = 1,
  51         queue_type__mes_set_resources__hsa_debug_interface_queue = 4
  52 };
  53
  54
  55 struct pm4_mes_set_resources {
  56         union {
  57                 union PM4_MES_TYPE_3_HEADER     header;         /* header */
  58                 uint32_t                        ordinal1;
  59         };
  60
  61         union {
  62                 struct {
  63                         uint32_t vmid_mask:16;
  64                         uint32_t unmap_latency:8;
  65                         uint32_t reserved1:5;
  66                         enum mes_set_resources_queue_type_enum queue_type:3;
  67                 } bitfields2;
  68                 uint32_t ordinal2;
  69         };
  70
  71         uint32_t queue_mask_lo;
  72         uint32_t queue_mask_hi;
  73         uint32_t gws_mask_lo;
  74         uint32_t gws_mask_hi;
  75
  76         union {
  77                 struct {
  78                         uint32_t oac_mask:16;
  79                         uint32_t reserved2:16;
  80                 } bitfields7;
  81                 uint32_t ordinal7;
  82         };
  83
  84         union {
  85                 struct {
  86                 uint32_t gds_heap_base:6;
  87                 uint32_t reserved3:5;
  88                 uint32_t gds_heap_size:6;
  89                 uint32_t reserved4:15;
  90                 } bitfields8;
  91                 uint32_t ordinal8;
  92         };
  93
  94 };
  95 #endif
  96
  97 /*--------------------MES_RUN_LIST--------------------*/
  98
  99 #ifndef PM4_MES_RUN_LIST_DEFINED
 100 #define PM4_MES_RUN_LIST_DEFINED
 101
 102 struct pm4_mes_runlist {
 103         union {
 104                 union PM4_MES_TYPE_3_HEADER header; /* header */
 105                 uint32_t ordinal1;
 106         };
 107
 108         union {
 109                 struct {
 110                         uint32_t reserved1:2;
 111                         uint32_t ib_base_lo:30;
 112                 } bitfields2;
 113                 uint32_t ordinal2;
 114         };
 115
 116         uint32_t ib_base_hi;
 117
 118         union {
 119                 struct {
 120                         uint32_t ib_size:20;
 121                         uint32_t chain:1;
 122                         uint32_t offload_polling:1;
 123                         uint32_t reserved2:1;
 124                         uint32_t valid:1;
 125                         uint32_t process_cnt:4;
 126                         uint32_t reserved3:4;
 127                 } bitfields4;
 128                 uint32_t ordinal4;
 129         };
 130
 131 };
 132 #endif
 133
 134 /*--------------------MES_MAP_PROCESS--------------------*/
 135
 136 #ifndef PM4_MES_MAP_PROCESS_DEFINED
 137 #define PM4_MES_MAP_PROCESS_DEFINED
 138
 139 struct pm4_mes_map_process {
 140         union {
 141                 union PM4_MES_TYPE_3_HEADER header;     /* header */
 142                 uint32_t ordinal1;
 143         };
 144
 145         union {
 146                 struct {
 147                         uint32_t pasid:16;
 148                         uint32_t reserved1:8;
 149                         uint32_t diq_enable:1;
 150                         uint32_t process_quantum:7;
 151                 } bitfields2;
 152                 uint32_t ordinal2;
 153         };
 154
 155         uint32_t vm_context_page_table_base_addr_lo32;
 156
 157         uint32_t vm_context_page_table_base_addr_hi32;
 158
 159         uint32_t sh_mem_bases;
 160
 161         uint32_t sh_mem_config;
 162
 163         uint32_t sq_shader_tba_lo;
 164
 165         uint32_t sq_shader_tba_hi;
 166
 167         uint32_t sq_shader_tma_lo;
 168
 169         uint32_t sq_shader_tma_hi;
 170
 171         uint32_t reserved6;
 172
 173         uint32_t gds_addr_lo;
 174
 175         uint32_t gds_addr_hi;
 176
 177         union {
 178                 struct {
 179                         uint32_t num_gws:6;
 180                         uint32_t reserved7:1;
 181                         uint32_t sdma_enable:1;
 182                         uint32_t num_oac:4;
 183                         uint32_t reserved8:4;
 184                         uint32_t gds_size:6;
 185                         uint32_t num_queues:10;
 186                 } bitfields14;
 187                 uint32_t ordinal14;
 188         };
 189
 190         uint32_t completion_signal_lo;
 191
 192         uint32_t completion_signal_hi;
 193
 194 };
 195
 196 #endif
 197
 198 /*--------------------MES_MAP_PROCESS_VM--------------------*/
 199
 200 #ifndef PM4_MES_MAP_PROCESS_VM_DEFINED
 201 #define PM4_MES_MAP_PROCESS_VM_DEFINED
 202
 203 struct PM4_MES_MAP_PROCESS_VM {
 204         union {
 205                 union PM4_MES_TYPE_3_HEADER header;     /* header */
 206                 uint32_t ordinal1;
 207         };
 208
 209         uint32_t reserved1;
 210
 211         uint32_t vm_context_cntl;
 212
 213         uint32_t reserved2;
 214
 215         uint32_t vm_context_page_table_end_addr_lo32;
 216
 217         uint32_t vm_context_page_table_end_addr_hi32;
 218
 219         uint32_t vm_context_page_table_start_addr_lo32;
 220
 221         uint32_t vm_context_page_table_start_addr_hi32;
 222
 223         uint32_t reserved3;
 224
 225         uint32_t reserved4;
 226
 227         uint32_t reserved5;
 228
 229         uint32_t reserved6;
 230
 231         uint32_t reserved7;
 232
 233         uint32_t reserved8;
 234
 235         uint32_t completion_signal_lo32;
 236
 237         uint32_t completion_signal_hi32;
 238
 239 };
 240 #endif
 241
 242 /*--------------------MES_MAP_QUEUES--------------------*/
 243
 244 #ifndef PM4_MES_MAP_QUEUES_VI_DEFINED
 245 #define PM4_MES_MAP_QUEUES_VI_DEFINED
 246 enum mes_map_queues_queue_sel_enum {
 247         queue_sel__mes_map_queues__map_to_specified_queue_slots_vi = 0,
 248 queue_sel__mes_map_queues__map_to_hws_determined_queue_slots_vi = 1
 249 };
 250
 251 enum mes_map_queues_queue_type_enum {
 252         queue_type__mes_map_queues__normal_compute_vi = 0,
 253         queue_type__mes_map_queues__debug_interface_queue_vi = 1,
 254         queue_type__mes_map_queues__normal_latency_static_queue_vi = 2,
 255 queue_type__mes_map_queues__low_latency_static_queue_vi = 3
 256 };
 257
 258 enum mes_map_queues_alloc_format_enum {
 259         alloc_format__mes_map_queues__one_per_pipe_vi = 0,
 260 alloc_format__mes_map_queues__all_on_one_pipe_vi = 1
 261 };
 262
 263 enum mes_map_queues_engine_sel_enum {
 264         engine_sel__mes_map_queues__compute_vi = 0,
 265         engine_sel__mes_map_queues__sdma0_vi = 2,
 266         engine_sel__mes_map_queues__sdma1_vi = 3
 267 };
 268
 269
 270 struct pm4_mes_map_queues {
 271         union {
 272                 union PM4_MES_TYPE_3_HEADER   header;            /* header */
 273                 uint32_t            ordinal1;
 274         };
 275
 276         union {
 277                 struct {
 278                         uint32_t reserved1:4;
 279                         enum mes_map_queues_queue_sel_enum queue_sel:2;
 280                         uint32_t reserved2:15;
 281                         enum mes_map_queues_queue_type_enum queue_type:3;
 282                         enum mes_map_queues_alloc_format_enum alloc_format:2;
 283                         enum mes_map_queues_engine_sel_enum engine_sel:3;
 284                         uint32_t num_queues:3;
 285                 } bitfields2;
 286                 uint32_t ordinal2;
 287         };
 288
 289         union {
 290                 struct {
 291                         uint32_t reserved3:1;
 292                         uint32_t check_disable:1;
 293                         uint32_t doorbell_offset:26;
 294                         uint32_t reserved4:4;
 295                 } bitfields3;
 296                 uint32_t ordinal3;
 297         };
 298
 299         uint32_t mqd_addr_lo;
 300         uint32_t mqd_addr_hi;
 301         uint32_t wptr_addr_lo;
 302         uint32_t wptr_addr_hi;
 303 };
 304 #endif
 305
 306 /*--------------------MES_QUERY_STATUS--------------------*/
 307
 308 #ifndef PM4_MES_QUERY_STATUS_DEFINED
 309 #define PM4_MES_QUERY_STATUS_DEFINED
 310 enum mes_query_status_interrupt_sel_enum {
 311         interrupt_sel__mes_query_status__completion_status = 0,
 312         interrupt_sel__mes_query_status__process_status = 1,
 313         interrupt_sel__mes_query_status__queue_status = 2
 314 };
 315
 316 enum mes_query_status_command_enum {
 317         command__mes_query_status__interrupt_only = 0,
 318         command__mes_query_status__fence_only_immediate = 1,
 319         command__mes_query_status__fence_only_after_write_ack = 2,
 320         command__mes_query_status__fence_wait_for_write_ack_send_interrupt = 3
 321 };
 322
 323 enum mes_query_status_engine_sel_enum {
 324         engine_sel__mes_query_status__compute = 0,
 325         engine_sel__mes_query_status__sdma0_queue = 2,
 326         engine_sel__mes_query_status__sdma1_queue = 3
 327 };
 328
 329 struct pm4_mes_query_status {
 330         union {
 331                 union PM4_MES_TYPE_3_HEADER   header;            /* header */
 332                 uint32_t            ordinal1;
 333         };
 334
 335         union {
 336                 struct {
 337                         uint32_t context_id:28;
 338                         enum mes_query_status_interrupt_sel_enum        interrupt_sel:2;
 339                         enum mes_query_status_command_enum command:2;
 340                 } bitfields2;
 341                 uint32_t ordinal2;
 342         };
 343
 344         union {
 345                 struct {
 346                         uint32_t pasid:16;
 347                         uint32_t reserved1:16;
 348                 } bitfields3a;
 349                 struct {
 350                         uint32_t reserved2:2;
 351                         uint32_t doorbell_offset:26;
 352                         enum mes_query_status_engine_sel_enum engine_sel:3;
 353                         uint32_t reserved3:1;
 354                 } bitfields3b;
 355                 uint32_t ordinal3;
 356         };
 357
 358         uint32_t addr_lo;
 359         uint32_t addr_hi;
 360         uint32_t data_lo;
 361         uint32_t data_hi;
 362 };
 363 #endif
 364
 365 /*--------------------MES_UNMAP_QUEUES--------------------*/
 366
 367 #ifndef PM4_MES_UNMAP_QUEUES_DEFINED
 368 #define PM4_MES_UNMAP_QUEUES_DEFINED
 369 enum mes_unmap_queues_action_enum {
 370         action__mes_unmap_queues__preempt_queues = 0,
 371         action__mes_unmap_queues__reset_queues = 1,
 372         action__mes_unmap_queues__disable_process_queues = 2,
 373         action__mes_unmap_queues__reserved = 3
 374 };
 375
 376 enum mes_unmap_queues_queue_sel_enum {
 377         queue_sel__mes_unmap_queues__perform_request_on_specified_queues = 0,
 378         queue_sel__mes_unmap_queues__perform_request_on_pasid_queues = 1,
 379         queue_sel__mes_unmap_queues__unmap_all_queues = 2,
 380         queue_sel__mes_unmap_queues__unmap_all_non_static_queues = 3
 381 };
 382
 383 enum mes_unmap_queues_engine_sel_enum {
 384         engine_sel__mes_unmap_queues__compute = 0,
 385         engine_sel__mes_unmap_queues__sdma0 = 2,
 386         engine_sel__mes_unmap_queues__sdmal = 3
 387 };
 388
 389 struct pm4_mes_unmap_queues {
 390         union {
 391                 union PM4_MES_TYPE_3_HEADER   header;            /* header */
 392                 uint32_t            ordinal1;
 393         };
 394
 395         union {
 396                 struct {
 397                         enum mes_unmap_queues_action_enum action:2;
 398                         uint32_t reserved1:2;
 399                         enum mes_unmap_queues_queue_sel_enum queue_sel:2;
 400                         uint32_t reserved2:20;
 401                         enum mes_unmap_queues_engine_sel_enum engine_sel:3;
 402                         uint32_t num_queues:3;
 403                 } bitfields2;
 404                 uint32_t ordinal2;
 405         };
 406
 407         union {
 408                 struct {
 409                         uint32_t pasid:16;
 410                         uint32_t reserved3:16;
 411                 } bitfields3a;
 412                 struct {
 413                         uint32_t reserved4:2;
 414                         uint32_t doorbell_offset0:26;
 415                         int32_t reserved5:4;
 416                 } bitfields3b;
 417                 uint32_t ordinal3;
 418         };
 419
 420         union {
 421         struct {
 422                         uint32_t reserved6:2;
 423                         uint32_t doorbell_offset1:26;
 424                         uint32_t reserved7:4;
 425                 } bitfields4;
 426                 uint32_t ordinal4;
 427         };
 428
 429         union {
 430                 struct {
 431                         uint32_t reserved8:2;
 432                         uint32_t doorbell_offset2:26;
 433                         uint32_t reserved9:4;
 434                 } bitfields5;
 435                 uint32_t ordinal5;
 436         };
 437
 438         union {
 439                 struct {
 440                         uint32_t reserved10:2;
 441                         uint32_t doorbell_offset3:26;
 442                         uint32_t reserved11:4;
 443                 } bitfields6;
 444                 uint32_t ordinal6;
 445         };
 446 };
 447 #endif
 448
 449 #ifndef PM4_MEC_RELEASE_MEM_DEFINED
 450 #define PM4_MEC_RELEASE_MEM_DEFINED
 451
 452 enum mec_release_mem_event_index_enum {
 453         event_index__mec_release_mem__end_of_pipe = 5,
 454         event_index__mec_release_mem__shader_done = 6
 455 };
 456
 457 enum mec_release_mem_cache_policy_enum {
 458         cache_policy__mec_release_mem__lru = 0,
 459         cache_policy__mec_release_mem__stream = 1
 460 };
 461
 462 enum mec_release_mem_pq_exe_status_enum {
 463         pq_exe_status__mec_release_mem__default = 0,
 464         pq_exe_status__mec_release_mem__phase_update = 1
 465 };
 466
 467 enum mec_release_mem_dst_sel_enum {
 468         dst_sel__mec_release_mem__memory_controller = 0,
 469         dst_sel__mec_release_mem__tc_l2 = 1,
 470         dst_sel__mec_release_mem__queue_write_pointer_register = 2,
 471         dst_sel__mec_release_mem__queue_write_pointer_poll_mask_bit = 3
 472 };
 473
 474 enum mec_release_mem_int_sel_enum {
 475         int_sel__mec_release_mem__none = 0,
 476         int_sel__mec_release_mem__send_interrupt_only = 1,
 477         int_sel__mec_release_mem__send_interrupt_after_write_confirm = 2,
 478         int_sel__mec_release_mem__send_data_after_write_confirm = 3,
 479         int_sel__mec_release_mem__unconditionally_send_int_ctxid = 4,
 480         int_sel__mec_release_mem__conditionally_send_int_ctxid_based_on_32_bit_compare = 5,
 481         int_sel__mec_release_mem__conditionally_send_int_ctxid_based_on_64_bit_compare = 6
 482 };
 483
 484 enum mec_release_mem_data_sel_enum {
 485         data_sel__mec_release_mem__none = 0,
 486         data_sel__mec_release_mem__send_32_bit_low = 1,
 487         data_sel__mec_release_mem__send_64_bit_data = 2,
 488         data_sel__mec_release_mem__send_gpu_clock_counter = 3,
 489         data_sel__mec_release_mem__send_cp_perfcounter_hi_lo = 4,
 490         data_sel__mec_release_mem__store_gds_data_to_memory = 5
 491 };
 492
 493 struct pm4_mec_release_mem {
 494         union {
 495                 union PM4_MES_TYPE_3_HEADER header;     /*header */
 496                 unsigned int ordinal1;
 497         };
 498
 499         union {
 500                 struct {
 501                         unsigned int event_type:6;
 502                         unsigned int reserved1:2;
 503                         enum mec_release_mem_event_index_enum event_index:4;
 504                         unsigned int tcl1_vol_action_ena:1;
 505                         unsigned int tc_vol_action_ena:1;
 506                         unsigned int reserved2:1;
 507                         unsigned int tc_wb_action_ena:1;
 508                         unsigned int tcl1_action_ena:1;
 509                         unsigned int tc_action_ena:1;
 510                         uint32_t reserved3:1;
 511                         uint32_t tc_nc_action_ena:1;
 512                         uint32_t tc_wc_action_ena:1;
 513                         uint32_t tc_md_action_ena:1;
 514                         uint32_t reserved4:3;
 515                         enum mec_release_mem_cache_policy_enum cache_policy:2;
 516                         uint32_t reserved5:2;
 517                         enum mec_release_mem_pq_exe_status_enum pq_exe_status:1;
 518                         uint32_t reserved6:2;
 519                 } bitfields2;
 520                 unsigned int ordinal2;
 521         };
 522
 523         union {
 524                 struct {
 525                         uint32_t reserved7:16;
 526                         enum mec_release_mem_dst_sel_enum dst_sel:2;
 527                         uint32_t reserved8:6;
 528                         enum mec_release_mem_int_sel_enum int_sel:3;
 529                         uint32_t reserved9:2;
 530                         enum mec_release_mem_data_sel_enum data_sel:3;
 531                 } bitfields3;
 532                 unsigned int ordinal3;
 533         };
 534
 535         union {
 536                 struct {
 537                         uint32_t reserved10:2;
 538                         unsigned int address_lo_32b:30;
 539                 } bitfields4;
 540                 struct {
 541                         uint32_t reserved11:3;
 542                         uint32_t address_lo_64b:29;
 543                 } bitfields4b;
 544                 uint32_t reserved12;
 545                 unsigned int ordinal4;
 546         };
 547
 548         union {
 549                 uint32_t address_hi;
 550                 uint32_t reserved13;
 551                 uint32_t ordinal5;
 552         };
 553
 554         union {
 555                 uint32_t data_lo;
 556                 uint32_t cmp_data_lo;
 557                 struct {
 558                         uint32_t dw_offset:16;
 559                         uint32_t num_dwords:16;
 560                 } bitfields6c;
 561                 uint32_t reserved14;
 562                 uint32_t ordinal6;
 563         };
 564
 565         union {
 566                 uint32_t data_hi;
 567                 uint32_t cmp_data_hi;
 568                 uint32_t reserved15;
 569                 uint32_t reserved16;
 570                 uint32_t ordinal7;
 571         };
 572
 573         uint32_t int_ctxid;
 574
 575 };
 576
 577 #endif
 578
 579 enum {
 580         CACHE_FLUSH_AND_INV_TS_EVENT = 0x00000014
 581 };
 582 #endif
 583