| blob | 0b81183125e33fc5936fb811213ba6c1778d0dff |
1 /*
2 * Copyright (C) 2016 BayLibre, SAS
3 * Author: Neil Armstrong <narmstrong@baylibre.com>
4 * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of the
9 * License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
18 */
20 #ifndef __MESON_DW_HDMI_H
21 #define __MESON_DW_HDMI_H
23 /*
24 * Bit 7 RW Reserved. Default 1.
25 * Bit 6 RW Reserved. Default 1.
26 * Bit 5 RW Reserved. Default 1.
27 * Bit 4 RW sw_reset_phyif: PHY interface. 1=Apply reset; 0=Release from reset.
28 * Default 1.
29 * Bit 3 RW sw_reset_intr: interrupt module. 1=Apply reset;
30 * 0=Release from reset.
31 * Default 1.
32 * Bit 2 RW sw_reset_mem: KSV/REVOC mem. 1=Apply reset; 0=Release from reset.
33 * Default 1.
34 * Bit 1 RW sw_reset_rnd: random number interface to HDCP. 1=Apply reset;
35 * 0=Release from reset. Default 1.
36 * Bit 0 RW sw_reset_core: connects to IP's ~irstz. 1=Apply reset;
37 * 0=Release from reset. Default 1.
38 */
39 #define HDMITX_TOP_SW_RESET (0x000)
41 /*
42 * Bit 12 RW i2s_ws_inv:1=Invert i2s_ws; 0=No invert. Default 0.
43 * Bit 11 RW i2s_clk_inv: 1=Invert i2s_clk; 0=No invert. Default 0.
44 * Bit 10 RW spdif_clk_inv: 1=Invert spdif_clk; 0=No invert. Default 0.
45 * Bit 9 RW tmds_clk_inv: 1=Invert tmds_clk; 0=No invert. Default 0.
46 * Bit 8 RW pixel_clk_inv: 1=Invert pixel_clk; 0=No invert. Default 0.
47 * Bit 4 RW cec_clk_en: 1=enable cec_clk; 0=disable. Default 0.
48 * Bit 3 RW i2s_clk_en: 1=enable i2s_clk; 0=disable. Default 0.
49 * Bit 2 RW spdif_clk_en: 1=enable spdif_clk; 0=disable. Default 0.
50 * Bit 1 RW tmds_clk_en: 1=enable tmds_clk; 0=disable. Default 0.
51 * Bit 0 RW pixel_clk_en: 1=enable pixel_clk; 0=disable. Default 0.
52 */
53 #define HDMITX_TOP_CLK_CNTL (0x001)
55 /*
56 * Bit 11: 0 RW hpd_valid_width: filter out width <= M*1024. Default 0.
57 * Bit 15:12 RW hpd_glitch_width: filter out glitch <= N. Default 0.
58 */
59 #define HDMITX_TOP_HPD_FILTER (0x002)
61 /*
62 * intr_maskn: MASK_N, one bit per interrupt source.
63 * 1=Enable interrupt source; 0=Disable interrupt source. Default 0.
64 * [ 4] hdcp22_rndnum_err
65 * [ 3] nonce_rfrsh_rise
66 * [ 2] hpd_fall_intr
67 * [ 1] hpd_rise_intr
68 * [ 0] core_intr
69 */
70 #define HDMITX_TOP_INTR_MASKN (0x003)
72 /*
73 * Bit 30: 0 RW intr_stat: For each bit, write 1 to manually set the interrupt
74 * bit, read back the interrupt status.
75 * Bit 31 R IP interrupt status
76 * Bit 2 RW hpd_fall
77 * Bit 1 RW hpd_rise
78 * Bit 0 RW IP interrupt
79 */
80 #define HDMITX_TOP_INTR_STAT (0x004)
82 /*
83 * [4] hdcp22_rndnum_err
84 * [3] nonce_rfrsh_rise
85 * [2] hpd_fall
86 * [1] hpd_rise
87 * [0] core_intr_rise
88 */
89 #define HDMITX_TOP_INTR_STAT_CLR (0x005)
91 #define HDMITX_TOP_INTR_CORE BIT(0)
92 #define HDMITX_TOP_INTR_HPD_RISE BIT(1)
93 #define HDMITX_TOP_INTR_HPD_FALL BIT(2)
95 /* Bit 14:12 RW tmds_sel: 3'b000=Output zero; 3'b001=Output normal TMDS data;
96 * 3'b010=Output PRBS data; 3'b100=Output shift pattern. Default 0.
97 * Bit 11: 9 RW shift_pttn_repeat: 0=New pattern every clk cycle; 1=New pattern
98 * every 2 clk cycles; ...; 7=New pattern every 8 clk cycles. Default 0.
99 * Bit 8 RW shift_pttn_en: 1= Enable shift pattern generator; 0=Disable.
100 * Default 0.
101 * Bit 4: 3 RW prbs_pttn_mode: 0=PRBS11; 1=PRBS15; 2=PRBS7; 3=PRBS31. Default 0.
102 * Bit 2: 1 RW prbs_pttn_width: 0=idle; 1=output 8-bit pattern;
103 * 2=Output 1-bit pattern; 3=output 10-bit pattern. Default 0.
104 * Bit 0 RW prbs_pttn_en: 1=Enable PRBS generator; 0=Disable. Default 0.
105 */
106 #define HDMITX_TOP_BIST_CNTL (0x006)
108 /* Bit 29:20 RW shift_pttn_data[59:50]. Default 0. */
109 /* Bit 19:10 RW shift_pttn_data[69:60]. Default 0. */
110 /* Bit 9: 0 RW shift_pttn_data[79:70]. Default 0. */
111 #define HDMITX_TOP_SHIFT_PTTN_012 (0x007)
113 /* Bit 29:20 RW shift_pttn_data[29:20]. Default 0. */
114 /* Bit 19:10 RW shift_pttn_data[39:30]. Default 0. */
115 /* Bit 9: 0 RW shift_pttn_data[49:40]. Default 0. */
116 #define HDMITX_TOP_SHIFT_PTTN_345 (0x008)
118 /* Bit 19:10 RW shift_pttn_data[ 9: 0]. Default 0. */
119 /* Bit 9: 0 RW shift_pttn_data[19:10]. Default 0. */
120 #define HDMITX_TOP_SHIFT_PTTN_67 (0x009)
122 /* Bit 25:16 RW tmds_clk_pttn[19:10]. Default 0. */
123 /* Bit 9: 0 RW tmds_clk_pttn[ 9: 0]. Default 0. */
124 #define HDMITX_TOP_TMDS_CLK_PTTN_01 (0x00A)
126 /* Bit 25:16 RW tmds_clk_pttn[39:30]. Default 0. */
127 /* Bit 9: 0 RW tmds_clk_pttn[29:20]. Default 0. */
128 #define HDMITX_TOP_TMDS_CLK_PTTN_23 (0x00B)
130 /* Bit 1 RW shift_tmds_clk_pttn:1=Enable shifting clk pattern,
131 * used when TMDS CLK rate = TMDS character rate /4. Default 0.
132 * Bit 0 R Reserved. Default 0.
133 * [ 1] shift_tmds_clk_pttn
134 * [ 0] load_tmds_clk_pttn
135 */
136 #define HDMITX_TOP_TMDS_CLK_PTTN_CNTL (0x00C)
138 /* Bit 0 RW revocmem_wr_fail: Read back 1 to indicate Host write REVOC MEM
139 * failure, write 1 to clear the failure flag. Default 0.
140 */
141 #define HDMITX_TOP_REVOCMEM_STAT (0x00D)
143 /* Bit 0 R filtered HPD status. */
144 #define HDMITX_TOP_STAT0 (0x00E)