drivers/gpu/drm/meson/meson_viu.h

   1 /*
   2  * Copyright (C) 2016 BayLibre, SAS
   3  * Author: Neil Armstrong <narmstrong@baylibre.com>
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License as
   7  * published by the Free Software Foundation; either version 2 of the
   8  * License, or (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 /* Video Input Unit */
  20
  21 #ifndef __MESON_VIU_H
  22 #define __MESON_VIU_H
  23
  24 /* OSDx_BLKx_CFG */
  25 #define OSD_CANVAS_SEL          16
  26
  27 #define OSD_ENDIANNESS_LE       BIT(15)
  28 #define OSD_ENDIANNESS_BE       (0)
  29
  30 #define OSD_BLK_MODE_422        (0x03 << 8)
  31 #define OSD_BLK_MODE_16         (0x04 << 8)
  32 #define OSD_BLK_MODE_32         (0x05 << 8)
  33 #define OSD_BLK_MODE_24         (0x07 << 8)
  34
  35 #define OSD_OUTPUT_COLOR_RGB    BIT(7)
  36 #define OSD_OUTPUT_COLOR_YUV    (0)
  37
  38 #define OSD_COLOR_MATRIX_32_RGBA        (0x00 << 2)
  39 #define OSD_COLOR_MATRIX_32_ARGB        (0x01 << 2)
  40 #define OSD_COLOR_MATRIX_32_ABGR        (0x02 << 2)
  41 #define OSD_COLOR_MATRIX_32_BGRA        (0x03 << 2)
  42
  43 #define OSD_COLOR_MATRIX_24_RGB         (0x00 << 2)
  44
  45 #define OSD_COLOR_MATRIX_16_RGB655      (0x00 << 2)
  46 #define OSD_COLOR_MATRIX_16_RGB565      (0x04 << 2)
  47
  48 #define OSD_INTERLACE_ENABLED   BIT(1)
  49 #define OSD_INTERLACE_ODD       BIT(0)
  50 #define OSD_INTERLACE_EVEN      (0)
  51
  52 /* OSDx_CTRL_STAT */
  53 #define OSD_ENABLE              BIT(21)
  54 #define OSD_BLK0_ENABLE         BIT(0)
  55
  56 #define OSD_GLOBAL_ALPHA_SHIFT  12
  57
  58 /* OSDx_CTRL_STAT2 */
  59 #define OSD_REPLACE_EN          BIT(14)
  60 #define OSD_REPLACE_SHIFT       6
  61
  62 void meson_viu_osd1_reset(struct meson_drm *priv);
  63 void meson_viu_init(struct meson_drm *priv);
  64
  65 #endif /* __MESON_VIU_H */