drivers/gpu/drm/nouveau/nouveau_abi16.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef __NOUVEAU_ABI16_H__
   3 #define __NOUVEAU_ABI16_H__
   4
   5 #define ABI16_IOCTL_ARGS                                                       \
   6         struct drm_device *dev, void *data, struct drm_file *file_priv
   7
   8 int nouveau_abi16_ioctl_getparam(ABI16_IOCTL_ARGS);
   9 int nouveau_abi16_ioctl_setparam(ABI16_IOCTL_ARGS);
  10 int nouveau_abi16_ioctl_channel_alloc(ABI16_IOCTL_ARGS);
  11 int nouveau_abi16_ioctl_channel_free(ABI16_IOCTL_ARGS);
  12 int nouveau_abi16_ioctl_grobj_alloc(ABI16_IOCTL_ARGS);
  13 int nouveau_abi16_ioctl_notifierobj_alloc(ABI16_IOCTL_ARGS);
  14 int nouveau_abi16_ioctl_gpuobj_free(ABI16_IOCTL_ARGS);
  15
  16 struct nouveau_abi16_ntfy {
  17         struct nvif_object object;
  18         struct list_head head;
  19         struct nvkm_mm_node *node;
  20 };
  21
  22 struct nouveau_abi16_chan {
  23         struct list_head head;
  24         struct nouveau_channel *chan;
  25         struct list_head notifiers;
  26         struct nouveau_bo *ntfy;
  27         struct nouveau_vma *ntfy_vma;
  28         struct nvkm_mm  heap;
  29 };
  30
  31 struct nouveau_abi16 {
  32         struct nvif_device device;
  33         struct list_head channels;
  34         u64 handles;
  35 };
  36
  37 struct nouveau_abi16 *nouveau_abi16_get(struct drm_file *);
  38 int  nouveau_abi16_put(struct nouveau_abi16 *, int);
  39 void nouveau_abi16_fini(struct nouveau_abi16 *);
  40 s32  nouveau_abi16_swclass(struct nouveau_drm *);
  41 int  nouveau_abi16_usif(struct drm_file *, void *data, u32 size);
  42
  43 #define NOUVEAU_GEM_DOMAIN_VRAM      (1 << 1)
  44 #define NOUVEAU_GEM_DOMAIN_GART      (1 << 2)
  45
  46 struct drm_nouveau_channel_alloc {
  47         uint32_t     fb_ctxdma_handle;
  48         uint32_t     tt_ctxdma_handle;
  49
  50         int          channel;
  51         uint32_t     pushbuf_domains;
  52
  53         /* Notifier memory */
  54         uint32_t     notifier_handle;
  55
  56         /* DRM-enforced subchannel assignments */
  57         struct {
  58                 uint32_t handle;
  59                 uint32_t grclass;
  60         } subchan[8];
  61         uint32_t nr_subchan;
  62 };
  63
  64 struct drm_nouveau_channel_free {
  65         int channel;
  66 };
  67
  68 struct drm_nouveau_grobj_alloc {
  69         int      channel;
  70         uint32_t handle;
  71         int      class;
  72 };
  73
  74 struct drm_nouveau_notifierobj_alloc {
  75         uint32_t channel;
  76         uint32_t handle;
  77         uint32_t size;
  78         uint32_t offset;
  79 };
  80
  81 struct drm_nouveau_gpuobj_free {
  82         int      channel;
  83         uint32_t handle;
  84 };
  85
  86 #define NOUVEAU_GETPARAM_PCI_VENDOR      3
  87 #define NOUVEAU_GETPARAM_PCI_DEVICE      4
  88 #define NOUVEAU_GETPARAM_BUS_TYPE        5
  89 #define NOUVEAU_GETPARAM_FB_SIZE         8
  90 #define NOUVEAU_GETPARAM_AGP_SIZE        9
  91 #define NOUVEAU_GETPARAM_CHIPSET_ID      11
  92 #define NOUVEAU_GETPARAM_VM_VRAM_BASE    12
  93 #define NOUVEAU_GETPARAM_GRAPH_UNITS     13
  94 #define NOUVEAU_GETPARAM_PTIMER_TIME     14
  95 #define NOUVEAU_GETPARAM_HAS_BO_USAGE    15
  96 #define NOUVEAU_GETPARAM_HAS_PAGEFLIP    16
  97 struct drm_nouveau_getparam {
  98         uint64_t param;
  99         uint64_t value;
 100 };
 101
 102 struct drm_nouveau_setparam {
 103         uint64_t param;
 104         uint64_t value;
 105 };
 106
 107 #define DRM_IOCTL_NOUVEAU_GETPARAM           DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GETPARAM, struct drm_nouveau_getparam)
 108 #define DRM_IOCTL_NOUVEAU_SETPARAM           DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_SETPARAM, struct drm_nouveau_setparam)
 109 #define DRM_IOCTL_NOUVEAU_CHANNEL_ALLOC      DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_CHANNEL_ALLOC, struct drm_nouveau_channel_alloc)
 110 #define DRM_IOCTL_NOUVEAU_CHANNEL_FREE       DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_CHANNEL_FREE, struct drm_nouveau_channel_free)
 111 #define DRM_IOCTL_NOUVEAU_GROBJ_ALLOC        DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GROBJ_ALLOC, struct drm_nouveau_grobj_alloc)
 112 #define DRM_IOCTL_NOUVEAU_NOTIFIEROBJ_ALLOC  DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_NOTIFIEROBJ_ALLOC, struct drm_nouveau_notifierobj_alloc)
 113 #define DRM_IOCTL_NOUVEAU_GPUOBJ_FREE        DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GPUOBJ_FREE, struct drm_nouveau_gpuobj_free)
 114
 115 #endif