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dt-bindings: mtd: ingenic: Use standard ecc-engine property
[linux/fpc-iii.git] / drivers / gpu / drm / sti / sti_hdmi.c
blob6000df62498077609ac4761c70d045d19f6ba590
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) STMicroelectronics SA 2014
4 * Author: Vincent Abriou <vincent.abriou@st.com> for STMicroelectronics.
5 */
6
7 #include <linux/clk.h>
8 #include <linux/component.h>
9 #include <linux/debugfs.h>
10 #include <linux/hdmi.h>
11 #include <linux/module.h>
12 #include <linux/of_gpio.h>
13 #include <linux/platform_device.h>
14 #include <linux/reset.h>
15
16 #include <drm/drmP.h>
17 #include <drm/drm_atomic_helper.h>
18 #include <drm/drm_edid.h>
19 #include <drm/drm_probe_helper.h>
20
21 #include <sound/hdmi-codec.h>
22
23 #include "sti_hdmi.h"
24 #include "sti_hdmi_tx3g4c28phy.h"
25 #include "sti_vtg.h"
26
27 #define HDMI_CFG 0x0000
28 #define HDMI_INT_EN 0x0004
29 #define HDMI_INT_STA 0x0008
30 #define HDMI_INT_CLR 0x000C
31 #define HDMI_STA 0x0010
32 #define HDMI_ACTIVE_VID_XMIN 0x0100
33 #define HDMI_ACTIVE_VID_XMAX 0x0104
34 #define HDMI_ACTIVE_VID_YMIN 0x0108
35 #define HDMI_ACTIVE_VID_YMAX 0x010C
36 #define HDMI_DFLT_CHL0_DAT 0x0110
37 #define HDMI_DFLT_CHL1_DAT 0x0114
38 #define HDMI_DFLT_CHL2_DAT 0x0118
39 #define HDMI_AUDIO_CFG 0x0200
40 #define HDMI_SPDIF_FIFO_STATUS 0x0204
41 #define HDMI_SW_DI_1_HEAD_WORD 0x0210
42 #define HDMI_SW_DI_1_PKT_WORD0 0x0214
43 #define HDMI_SW_DI_1_PKT_WORD1 0x0218
44 #define HDMI_SW_DI_1_PKT_WORD2 0x021C
45 #define HDMI_SW_DI_1_PKT_WORD3 0x0220
46 #define HDMI_SW_DI_1_PKT_WORD4 0x0224
47 #define HDMI_SW_DI_1_PKT_WORD5 0x0228
48 #define HDMI_SW_DI_1_PKT_WORD6 0x022C
49 #define HDMI_SW_DI_CFG 0x0230
50 #define HDMI_SAMPLE_FLAT_MASK 0x0244
51 #define HDMI_AUDN 0x0400
52 #define HDMI_AUD_CTS 0x0404
53 #define HDMI_SW_DI_2_HEAD_WORD 0x0600
54 #define HDMI_SW_DI_2_PKT_WORD0 0x0604
55 #define HDMI_SW_DI_2_PKT_WORD1 0x0608
56 #define HDMI_SW_DI_2_PKT_WORD2 0x060C
57 #define HDMI_SW_DI_2_PKT_WORD3 0x0610
58 #define HDMI_SW_DI_2_PKT_WORD4 0x0614
59 #define HDMI_SW_DI_2_PKT_WORD5 0x0618
60 #define HDMI_SW_DI_2_PKT_WORD6 0x061C
61 #define HDMI_SW_DI_3_HEAD_WORD 0x0620
62 #define HDMI_SW_DI_3_PKT_WORD0 0x0624
63 #define HDMI_SW_DI_3_PKT_WORD1 0x0628
64 #define HDMI_SW_DI_3_PKT_WORD2 0x062C
65 #define HDMI_SW_DI_3_PKT_WORD3 0x0630
66 #define HDMI_SW_DI_3_PKT_WORD4 0x0634
67 #define HDMI_SW_DI_3_PKT_WORD5 0x0638
68 #define HDMI_SW_DI_3_PKT_WORD6 0x063C
69
70 #define HDMI_IFRAME_SLOT_AVI 1
71 #define HDMI_IFRAME_SLOT_AUDIO 2
72 #define HDMI_IFRAME_SLOT_VENDOR 3
73
74 #define XCAT(prefix, x, suffix) prefix ## x ## suffix
75 #define HDMI_SW_DI_N_HEAD_WORD(x) XCAT(HDMI_SW_DI_, x, _HEAD_WORD)
76 #define HDMI_SW_DI_N_PKT_WORD0(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD0)
77 #define HDMI_SW_DI_N_PKT_WORD1(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD1)
78 #define HDMI_SW_DI_N_PKT_WORD2(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD2)
79 #define HDMI_SW_DI_N_PKT_WORD3(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD3)
80 #define HDMI_SW_DI_N_PKT_WORD4(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD4)
81 #define HDMI_SW_DI_N_PKT_WORD5(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD5)
82 #define HDMI_SW_DI_N_PKT_WORD6(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD6)
83
84 #define HDMI_SW_DI_MAX_WORD 7
85
86 #define HDMI_IFRAME_DISABLED 0x0
87 #define HDMI_IFRAME_SINGLE_SHOT 0x1
88 #define HDMI_IFRAME_FIELD 0x2
89 #define HDMI_IFRAME_FRAME 0x3
90 #define HDMI_IFRAME_MASK 0x3
91 #define HDMI_IFRAME_CFG_DI_N(x, n) ((x) << ((n-1)*4)) /* n from 1 to 6 */
92
93 #define HDMI_CFG_DEVICE_EN BIT(0)
94 #define HDMI_CFG_HDMI_NOT_DVI BIT(1)
95 #define HDMI_CFG_HDCP_EN BIT(2)
96 #define HDMI_CFG_ESS_NOT_OESS BIT(3)
97 #define HDMI_CFG_H_SYNC_POL_NEG BIT(4)
98 #define HDMI_CFG_V_SYNC_POL_NEG BIT(6)
99 #define HDMI_CFG_422_EN BIT(8)
100 #define HDMI_CFG_FIFO_OVERRUN_CLR BIT(12)
101 #define HDMI_CFG_FIFO_UNDERRUN_CLR BIT(13)
102 #define HDMI_CFG_SW_RST_EN BIT(31)
103
104 #define HDMI_INT_GLOBAL BIT(0)
105 #define HDMI_INT_SW_RST BIT(1)
106 #define HDMI_INT_PIX_CAP BIT(3)
107 #define HDMI_INT_HOT_PLUG BIT(4)
108 #define HDMI_INT_DLL_LCK BIT(5)
109 #define HDMI_INT_NEW_FRAME BIT(6)
110 #define HDMI_INT_GENCTRL_PKT BIT(7)
111 #define HDMI_INT_AUDIO_FIFO_XRUN BIT(8)
112 #define HDMI_INT_SINK_TERM_PRESENT BIT(11)
113
114 #define HDMI_DEFAULT_INT (HDMI_INT_SINK_TERM_PRESENT \
115 | HDMI_INT_DLL_LCK \
116 | HDMI_INT_HOT_PLUG \
117 | HDMI_INT_GLOBAL)
118
119 #define HDMI_WORKING_INT (HDMI_INT_SINK_TERM_PRESENT \
120 | HDMI_INT_AUDIO_FIFO_XRUN \
121 | HDMI_INT_GENCTRL_PKT \
122 | HDMI_INT_NEW_FRAME \
123 | HDMI_INT_DLL_LCK \
124 | HDMI_INT_HOT_PLUG \
125 | HDMI_INT_PIX_CAP \
126 | HDMI_INT_SW_RST \
127 | HDMI_INT_GLOBAL)
128
129 #define HDMI_STA_SW_RST BIT(1)
130
131 #define HDMI_AUD_CFG_8CH BIT(0)
132 #define HDMI_AUD_CFG_SPDIF_DIV_2 BIT(1)
133 #define HDMI_AUD_CFG_SPDIF_DIV_3 BIT(2)
134 #define HDMI_AUD_CFG_SPDIF_CLK_DIV_4 (BIT(1) | BIT(2))
135 #define HDMI_AUD_CFG_CTS_CLK_256FS BIT(12)
136 #define HDMI_AUD_CFG_DTS_INVALID BIT(16)
137 #define HDMI_AUD_CFG_ONE_BIT_INVALID (BIT(18) | BIT(19) | BIT(20) | BIT(21))
138 #define HDMI_AUD_CFG_CH12_VALID BIT(28)
139 #define HDMI_AUD_CFG_CH34_VALID BIT(29)
140 #define HDMI_AUD_CFG_CH56_VALID BIT(30)
141 #define HDMI_AUD_CFG_CH78_VALID BIT(31)
142
143 /* sample flat mask */
144 #define HDMI_SAMPLE_FLAT_NO 0
145 #define HDMI_SAMPLE_FLAT_SP0 BIT(0)
146 #define HDMI_SAMPLE_FLAT_SP1 BIT(1)
147 #define HDMI_SAMPLE_FLAT_SP2 BIT(2)
148 #define HDMI_SAMPLE_FLAT_SP3 BIT(3)
149 #define HDMI_SAMPLE_FLAT_ALL (HDMI_SAMPLE_FLAT_SP0 | HDMI_SAMPLE_FLAT_SP1 |\
150 HDMI_SAMPLE_FLAT_SP2 | HDMI_SAMPLE_FLAT_SP3)
151
152 #define HDMI_INFOFRAME_HEADER_TYPE(x) (((x) & 0xff) << 0)
153 #define HDMI_INFOFRAME_HEADER_VERSION(x) (((x) & 0xff) << 8)
154 #define HDMI_INFOFRAME_HEADER_LEN(x) (((x) & 0x0f) << 16)
155
156 struct sti_hdmi_connector {
157 struct drm_connector drm_connector;
158 struct drm_encoder *encoder;
159 struct sti_hdmi *hdmi;
160 struct drm_property *colorspace_property;
161 };
162
163 #define to_sti_hdmi_connector(x) \
164 container_of(x, struct sti_hdmi_connector, drm_connector)
165
166 u32 hdmi_read(struct sti_hdmi *hdmi, int offset)
167 {
168 return readl(hdmi->regs + offset);
169 }
170
171 void hdmi_write(struct sti_hdmi *hdmi, u32 val, int offset)
172 {
173 writel(val, hdmi->regs + offset);
174 }
175
176 /**
177 * HDMI interrupt handler threaded
178 *
179 * @irq: irq number
180 * @arg: connector structure
181 */
182 static irqreturn_t hdmi_irq_thread(int irq, void *arg)
183 {
184 struct sti_hdmi *hdmi = arg;
185
186 /* Hot plug/unplug IRQ */
187 if (hdmi->irq_status & HDMI_INT_HOT_PLUG) {
188 hdmi->hpd = readl(hdmi->regs + HDMI_STA) & HDMI_STA_HOT_PLUG;
189 if (hdmi->drm_dev)
190 drm_helper_hpd_irq_event(hdmi->drm_dev);
191 }
192
193 /* Sw reset and PLL lock are exclusive so we can use the same
194 * event to signal them
195 */
196 if (hdmi->irq_status & (HDMI_INT_SW_RST | HDMI_INT_DLL_LCK)) {
197 hdmi->event_received = true;
198 wake_up_interruptible(&hdmi->wait_event);
199 }
200
201 /* Audio FIFO underrun IRQ */
202 if (hdmi->irq_status & HDMI_INT_AUDIO_FIFO_XRUN)
203 DRM_INFO("Warning: audio FIFO underrun occurs!\n");
204
205 return IRQ_HANDLED;
206 }
207
208 /**
209 * HDMI interrupt handler
210 *
211 * @irq: irq number
212 * @arg: connector structure
213 */
214 static irqreturn_t hdmi_irq(int irq, void *arg)
215 {
216 struct sti_hdmi *hdmi = arg;
217
218 /* read interrupt status */
219 hdmi->irq_status = hdmi_read(hdmi, HDMI_INT_STA);
220
221 /* clear interrupt status */
222 hdmi_write(hdmi, hdmi->irq_status, HDMI_INT_CLR);
223
224 /* force sync bus write */
225 hdmi_read(hdmi, HDMI_INT_STA);
226
227 return IRQ_WAKE_THREAD;
228 }
229
230 /**
231 * Set hdmi active area depending on the drm display mode selected
232 *
233 * @hdmi: pointer on the hdmi internal structure
234 */
235 static void hdmi_active_area(struct sti_hdmi *hdmi)
236 {
237 u32 xmin, xmax;
238 u32 ymin, ymax;
239
240 xmin = sti_vtg_get_pixel_number(hdmi->mode, 1);
241 xmax = sti_vtg_get_pixel_number(hdmi->mode, hdmi->mode.hdisplay);
242 ymin = sti_vtg_get_line_number(hdmi->mode, 0);
243 ymax = sti_vtg_get_line_number(hdmi->mode, hdmi->mode.vdisplay - 1);
244
245 hdmi_write(hdmi, xmin, HDMI_ACTIVE_VID_XMIN);
246 hdmi_write(hdmi, xmax, HDMI_ACTIVE_VID_XMAX);
247 hdmi_write(hdmi, ymin, HDMI_ACTIVE_VID_YMIN);
248 hdmi_write(hdmi, ymax, HDMI_ACTIVE_VID_YMAX);
249 }
250
251 /**
252 * Overall hdmi configuration
253 *
254 * @hdmi: pointer on the hdmi internal structure
255 */
256 static void hdmi_config(struct sti_hdmi *hdmi)
257 {
258 u32 conf;
259
260 DRM_DEBUG_DRIVER("\n");
261
262 /* Clear overrun and underrun fifo */
263 conf = HDMI_CFG_FIFO_OVERRUN_CLR | HDMI_CFG_FIFO_UNDERRUN_CLR;
264
265 /* Select encryption type and the framing mode */
266 conf |= HDMI_CFG_ESS_NOT_OESS;
267 if (hdmi->hdmi_monitor)
268 conf |= HDMI_CFG_HDMI_NOT_DVI;
269
270 /* Set Hsync polarity */
271 if (hdmi->mode.flags & DRM_MODE_FLAG_NHSYNC) {
272 DRM_DEBUG_DRIVER("H Sync Negative\n");
273 conf |= HDMI_CFG_H_SYNC_POL_NEG;
274 }
275
276 /* Set Vsync polarity */
277 if (hdmi->mode.flags & DRM_MODE_FLAG_NVSYNC) {
278 DRM_DEBUG_DRIVER("V Sync Negative\n");
279 conf |= HDMI_CFG_V_SYNC_POL_NEG;
280 }
281
282 /* Enable HDMI */
283 conf |= HDMI_CFG_DEVICE_EN;
284
285 hdmi_write(hdmi, conf, HDMI_CFG);
286 }
287
288 /*
289 * Helper to reset info frame
290 *
291 * @hdmi: pointer on the hdmi internal structure
292 * @slot: infoframe to reset
293 */
294 static void hdmi_infoframe_reset(struct sti_hdmi *hdmi,
295 u32 slot)
296 {
297 u32 val, i;
298 u32 head_offset, pack_offset;
299
300 switch (slot) {
301 case HDMI_IFRAME_SLOT_AVI:
302 head_offset = HDMI_SW_DI_N_HEAD_WORD(HDMI_IFRAME_SLOT_AVI);
303 pack_offset = HDMI_SW_DI_N_PKT_WORD0(HDMI_IFRAME_SLOT_AVI);
304 break;
305 case HDMI_IFRAME_SLOT_AUDIO:
306 head_offset = HDMI_SW_DI_N_HEAD_WORD(HDMI_IFRAME_SLOT_AUDIO);
307 pack_offset = HDMI_SW_DI_N_PKT_WORD0(HDMI_IFRAME_SLOT_AUDIO);
308 break;
309 case HDMI_IFRAME_SLOT_VENDOR:
310 head_offset = HDMI_SW_DI_N_HEAD_WORD(HDMI_IFRAME_SLOT_VENDOR);
311 pack_offset = HDMI_SW_DI_N_PKT_WORD0(HDMI_IFRAME_SLOT_VENDOR);
312 break;
313 default:
314 DRM_ERROR("unsupported infoframe slot: %#x\n", slot);
315 return;
316 }
317
318 /* Disable transmission for the selected slot */
319 val = hdmi_read(hdmi, HDMI_SW_DI_CFG);
320 val &= ~HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, slot);
321 hdmi_write(hdmi, val, HDMI_SW_DI_CFG);
322
323 /* Reset info frame registers */
324 hdmi_write(hdmi, 0x0, head_offset);
325 for (i = 0; i < HDMI_SW_DI_MAX_WORD; i += sizeof(u32))
326 hdmi_write(hdmi, 0x0, pack_offset + i);
327 }
328
329 /**
330 * Helper to concatenate infoframe in 32 bits word
331 *
332 * @ptr: pointer on the hdmi internal structure
333 * @data: infoframe to write
334 * @size: size to write
335 */
336 static inline unsigned int hdmi_infoframe_subpack(const u8 *ptr, size_t size)
337 {
338 unsigned long value = 0;
339 size_t i;
340
341 for (i = size; i > 0; i--)
342 value = (value << 8) | ptr[i - 1];
343
344 return value;
345 }
346
347 /**
348 * Helper to write info frame
349 *
350 * @hdmi: pointer on the hdmi internal structure
351 * @data: infoframe to write
352 * @size: size to write
353 */
354 static void hdmi_infoframe_write_infopack(struct sti_hdmi *hdmi,
355 const u8 *data,
356 size_t size)
357 {
358 const u8 *ptr = data;
359 u32 val, slot, mode, i;
360 u32 head_offset, pack_offset;
361
362 switch (*ptr) {
363 case HDMI_INFOFRAME_TYPE_AVI:
364 slot = HDMI_IFRAME_SLOT_AVI;
365 mode = HDMI_IFRAME_FIELD;
366 head_offset = HDMI_SW_DI_N_HEAD_WORD(HDMI_IFRAME_SLOT_AVI);
367 pack_offset = HDMI_SW_DI_N_PKT_WORD0(HDMI_IFRAME_SLOT_AVI);
368 break;
369 case HDMI_INFOFRAME_TYPE_AUDIO:
370 slot = HDMI_IFRAME_SLOT_AUDIO;
371 mode = HDMI_IFRAME_FRAME;
372 head_offset = HDMI_SW_DI_N_HEAD_WORD(HDMI_IFRAME_SLOT_AUDIO);
373 pack_offset = HDMI_SW_DI_N_PKT_WORD0(HDMI_IFRAME_SLOT_AUDIO);
374 break;
375 case HDMI_INFOFRAME_TYPE_VENDOR:
376 slot = HDMI_IFRAME_SLOT_VENDOR;
377 mode = HDMI_IFRAME_FRAME;
378 head_offset = HDMI_SW_DI_N_HEAD_WORD(HDMI_IFRAME_SLOT_VENDOR);
379 pack_offset = HDMI_SW_DI_N_PKT_WORD0(HDMI_IFRAME_SLOT_VENDOR);
380 break;
381 default:
382 DRM_ERROR("unsupported infoframe type: %#x\n", *ptr);
383 return;
384 }
385
386 /* Disable transmission slot for updated infoframe */
387 val = hdmi_read(hdmi, HDMI_SW_DI_CFG);
388 val &= ~HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, slot);
389 hdmi_write(hdmi, val, HDMI_SW_DI_CFG);
390
391 val = HDMI_INFOFRAME_HEADER_TYPE(*ptr++);
392 val |= HDMI_INFOFRAME_HEADER_VERSION(*ptr++);
393 val |= HDMI_INFOFRAME_HEADER_LEN(*ptr++);
394 writel(val, hdmi->regs + head_offset);
395
396 /*
397 * Each subpack contains 4 bytes
398 * The First Bytes of the first subpacket must contain the checksum
399 * Packet size is increase by one.
400 */
401 size = size - HDMI_INFOFRAME_HEADER_SIZE + 1;
402 for (i = 0; i < size; i += sizeof(u32)) {
403 size_t num;
404
405 num = min_t(size_t, size - i, sizeof(u32));
406 val = hdmi_infoframe_subpack(ptr, num);
407 ptr += sizeof(u32);
408 writel(val, hdmi->regs + pack_offset + i);
409 }
410
411 /* Enable transmission slot for updated infoframe */
412 val = hdmi_read(hdmi, HDMI_SW_DI_CFG);
413 val |= HDMI_IFRAME_CFG_DI_N(mode, slot);
414 hdmi_write(hdmi, val, HDMI_SW_DI_CFG);
415 }
416
417 /**
418 * Prepare and configure the AVI infoframe
419 *
420 * AVI infoframe are transmitted at least once per two video field and
421 * contains information about HDMI transmission mode such as color space,
422 * colorimetry, ...
423 *
424 * @hdmi: pointer on the hdmi internal structure
425 *
426 * Return negative value if error occurs
427 */
428 static int hdmi_avi_infoframe_config(struct sti_hdmi *hdmi)
429 {
430 struct drm_display_mode *mode = &hdmi->mode;
431 struct hdmi_avi_infoframe infoframe;
432 u8 buffer[HDMI_INFOFRAME_SIZE(AVI)];
433 int ret;
434
435 DRM_DEBUG_DRIVER("\n");
436
437 ret = drm_hdmi_avi_infoframe_from_display_mode(&infoframe,
438 hdmi->drm_connector, mode);
439 if (ret < 0) {
440 DRM_ERROR("failed to setup AVI infoframe: %d\n", ret);
441 return ret;
442 }
443
444 /* fixed infoframe configuration not linked to the mode */
445 infoframe.colorspace = hdmi->colorspace;
446 infoframe.quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
447 infoframe.colorimetry = HDMI_COLORIMETRY_NONE;
448
449 ret = hdmi_avi_infoframe_pack(&infoframe, buffer, sizeof(buffer));
450 if (ret < 0) {
451 DRM_ERROR("failed to pack AVI infoframe: %d\n", ret);
452 return ret;
453 }
454
455 hdmi_infoframe_write_infopack(hdmi, buffer, ret);
456
457 return 0;
458 }
459
460 /**
461 * Prepare and configure the AUDIO infoframe
462 *
463 * AUDIO infoframe are transmitted once per frame and
464 * contains information about HDMI transmission mode such as audio codec,
465 * sample size, ...
466 *
467 * @hdmi: pointer on the hdmi internal structure
468 *
469 * Return negative value if error occurs
470 */
471 static int hdmi_audio_infoframe_config(struct sti_hdmi *hdmi)
472 {
473 struct hdmi_audio_params *audio = &hdmi->audio;
474 u8 buffer[HDMI_INFOFRAME_SIZE(AUDIO)];
475 int ret, val;
476
477 DRM_DEBUG_DRIVER("enter %s, AIF %s\n", __func__,
478 audio->enabled ? "enable" : "disable");
479 if (audio->enabled) {
480 /* set audio parameters stored*/
481 ret = hdmi_audio_infoframe_pack(&audio->cea, buffer,
482 sizeof(buffer));
483 if (ret < 0) {
484 DRM_ERROR("failed to pack audio infoframe: %d\n", ret);
485 return ret;
486 }
487 hdmi_infoframe_write_infopack(hdmi, buffer, ret);
488 } else {
489 /*disable audio info frame transmission */
490 val = hdmi_read(hdmi, HDMI_SW_DI_CFG);
491 val &= ~HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK,
492 HDMI_IFRAME_SLOT_AUDIO);
493 hdmi_write(hdmi, val, HDMI_SW_DI_CFG);
494 }
495
496 return 0;
497 }
498
499 /*
500 * Prepare and configure the VS infoframe
501 *
502 * Vendor Specific infoframe are transmitted once per frame and
503 * contains vendor specific information.
504 *
505 * @hdmi: pointer on the hdmi internal structure
506 *
507 * Return negative value if error occurs
508 */
509 #define HDMI_VENDOR_INFOFRAME_MAX_SIZE 6
510 static int hdmi_vendor_infoframe_config(struct sti_hdmi *hdmi)
511 {
512 struct drm_display_mode *mode = &hdmi->mode;
513 struct hdmi_vendor_infoframe infoframe;
514 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_VENDOR_INFOFRAME_MAX_SIZE];
515 int ret;
516
517 DRM_DEBUG_DRIVER("\n");
518
519 ret = drm_hdmi_vendor_infoframe_from_display_mode(&infoframe,
520 hdmi->drm_connector,
521 mode);
522 if (ret < 0) {
523 /*
524 * Going into that statement does not means vendor infoframe
525 * fails. It just informed us that vendor infoframe is not
526 * needed for the selected mode. Only 4k or stereoscopic 3D
527 * mode requires vendor infoframe. So just simply return 0.
528 */
529 return 0;
530 }
531
532 ret = hdmi_vendor_infoframe_pack(&infoframe, buffer, sizeof(buffer));
533 if (ret < 0) {
534 DRM_ERROR("failed to pack VS infoframe: %d\n", ret);
535 return ret;
536 }
537
538 hdmi_infoframe_write_infopack(hdmi, buffer, ret);
539
540 return 0;
541 }
542
543 /**
544 * Software reset of the hdmi subsystem
545 *
546 * @hdmi: pointer on the hdmi internal structure
547 *
548 */
549 #define HDMI_TIMEOUT_SWRESET 100 /*milliseconds */
550 static void hdmi_swreset(struct sti_hdmi *hdmi)
551 {
552 u32 val;
553
554 DRM_DEBUG_DRIVER("\n");
555
556 /* Enable hdmi_audio clock only during hdmi reset */
557 if (clk_prepare_enable(hdmi->clk_audio))
558 DRM_INFO("Failed to prepare/enable hdmi_audio clk\n");
559
560 /* Sw reset */
561 hdmi->event_received = false;
562
563 val = hdmi_read(hdmi, HDMI_CFG);
564 val |= HDMI_CFG_SW_RST_EN;
565 hdmi_write(hdmi, val, HDMI_CFG);
566
567 /* Wait reset completed */
568 wait_event_interruptible_timeout(hdmi->wait_event,
569 hdmi->event_received,
570 msecs_to_jiffies
571 (HDMI_TIMEOUT_SWRESET));
572
573 /*
574 * HDMI_STA_SW_RST bit is set to '1' when SW_RST bit in HDMI_CFG is
575 * set to '1' and clk_audio is running.
576 */
577 if ((hdmi_read(hdmi, HDMI_STA) & HDMI_STA_SW_RST) == 0)
578 DRM_DEBUG_DRIVER("Warning: HDMI sw reset timeout occurs\n");
579
580 val = hdmi_read(hdmi, HDMI_CFG);
581 val &= ~HDMI_CFG_SW_RST_EN;
582 hdmi_write(hdmi, val, HDMI_CFG);
583
584 /* Disable hdmi_audio clock. Not used anymore for drm purpose */
585 clk_disable_unprepare(hdmi->clk_audio);
586 }
587
588 #define DBGFS_PRINT_STR(str1, str2) seq_printf(s, "%-24s %s\n", str1, str2)
589 #define DBGFS_PRINT_INT(str1, int2) seq_printf(s, "%-24s %d\n", str1, int2)
590 #define DBGFS_DUMP(str, reg) seq_printf(s, "%s %-25s 0x%08X", str, #reg, \
591 hdmi_read(hdmi, reg))
592 #define DBGFS_DUMP_DI(reg, slot) DBGFS_DUMP("\n", reg(slot))
593
594 static void hdmi_dbg_cfg(struct seq_file *s, int val)
595 {
596 int tmp;
597
598 seq_putc(s, '\t');
599 tmp = val & HDMI_CFG_HDMI_NOT_DVI;
600 DBGFS_PRINT_STR("mode:", tmp ? "HDMI" : "DVI");
601 seq_puts(s, "\t\t\t\t\t");
602 tmp = val & HDMI_CFG_HDCP_EN;
603 DBGFS_PRINT_STR("HDCP:", tmp ? "enable" : "disable");
604 seq_puts(s, "\t\t\t\t\t");
605 tmp = val & HDMI_CFG_ESS_NOT_OESS;
606 DBGFS_PRINT_STR("HDCP mode:", tmp ? "ESS enable" : "OESS enable");
607 seq_puts(s, "\t\t\t\t\t");
608 tmp = val & HDMI_CFG_H_SYNC_POL_NEG;
609 DBGFS_PRINT_STR("Hsync polarity:", tmp ? "inverted" : "normal");
610 seq_puts(s, "\t\t\t\t\t");
611 tmp = val & HDMI_CFG_V_SYNC_POL_NEG;
612 DBGFS_PRINT_STR("Vsync polarity:", tmp ? "inverted" : "normal");
613 seq_puts(s, "\t\t\t\t\t");
614 tmp = val & HDMI_CFG_422_EN;
615 DBGFS_PRINT_STR("YUV422 format:", tmp ? "enable" : "disable");
616 }
617
618 static void hdmi_dbg_sta(struct seq_file *s, int val)
619 {
620 int tmp;
621
622 seq_putc(s, '\t');
623 tmp = (val & HDMI_STA_DLL_LCK);
624 DBGFS_PRINT_STR("pll:", tmp ? "locked" : "not locked");
625 seq_puts(s, "\t\t\t\t\t");
626 tmp = (val & HDMI_STA_HOT_PLUG);
627 DBGFS_PRINT_STR("hdmi cable:", tmp ? "connected" : "not connected");
628 }
629
630 static void hdmi_dbg_sw_di_cfg(struct seq_file *s, int val)
631 {
632 int tmp;
633 char *const en_di[] = {"no transmission",
634 "single transmission",
635 "once every field",
636 "once every frame"};
637
638 seq_putc(s, '\t');
639 tmp = (val & HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, 1));
640 DBGFS_PRINT_STR("Data island 1:", en_di[tmp]);
641 seq_puts(s, "\t\t\t\t\t");
642 tmp = (val & HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, 2)) >> 4;
643 DBGFS_PRINT_STR("Data island 2:", en_di[tmp]);
644 seq_puts(s, "\t\t\t\t\t");
645 tmp = (val & HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, 3)) >> 8;
646 DBGFS_PRINT_STR("Data island 3:", en_di[tmp]);
647 seq_puts(s, "\t\t\t\t\t");
648 tmp = (val & HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, 4)) >> 12;
649 DBGFS_PRINT_STR("Data island 4:", en_di[tmp]);
650 seq_puts(s, "\t\t\t\t\t");
651 tmp = (val & HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, 5)) >> 16;
652 DBGFS_PRINT_STR("Data island 5:", en_di[tmp]);
653 seq_puts(s, "\t\t\t\t\t");
654 tmp = (val & HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, 6)) >> 20;
655 DBGFS_PRINT_STR("Data island 6:", en_di[tmp]);
656 }
657
658 static int hdmi_dbg_show(struct seq_file *s, void *data)
659 {
660 struct drm_info_node *node = s->private;
661 struct sti_hdmi *hdmi = (struct sti_hdmi *)node->info_ent->data;
662
663 seq_printf(s, "HDMI: (vaddr = 0x%p)", hdmi->regs);
664 DBGFS_DUMP("\n", HDMI_CFG);
665 hdmi_dbg_cfg(s, hdmi_read(hdmi, HDMI_CFG));
666 DBGFS_DUMP("", HDMI_INT_EN);
667 DBGFS_DUMP("\n", HDMI_STA);
668 hdmi_dbg_sta(s, hdmi_read(hdmi, HDMI_STA));
669 DBGFS_DUMP("", HDMI_ACTIVE_VID_XMIN);
670 seq_putc(s, '\t');
671 DBGFS_PRINT_INT("Xmin:", hdmi_read(hdmi, HDMI_ACTIVE_VID_XMIN));
672 DBGFS_DUMP("", HDMI_ACTIVE_VID_XMAX);
673 seq_putc(s, '\t');
674 DBGFS_PRINT_INT("Xmax:", hdmi_read(hdmi, HDMI_ACTIVE_VID_XMAX));
675 DBGFS_DUMP("", HDMI_ACTIVE_VID_YMIN);
676 seq_putc(s, '\t');
677 DBGFS_PRINT_INT("Ymin:", hdmi_read(hdmi, HDMI_ACTIVE_VID_YMIN));
678 DBGFS_DUMP("", HDMI_ACTIVE_VID_YMAX);
679 seq_putc(s, '\t');
680 DBGFS_PRINT_INT("Ymax:", hdmi_read(hdmi, HDMI_ACTIVE_VID_YMAX));
681 DBGFS_DUMP("", HDMI_SW_DI_CFG);
682 hdmi_dbg_sw_di_cfg(s, hdmi_read(hdmi, HDMI_SW_DI_CFG));
683
684 DBGFS_DUMP("\n", HDMI_AUDIO_CFG);
685 DBGFS_DUMP("\n", HDMI_SPDIF_FIFO_STATUS);
686 DBGFS_DUMP("\n", HDMI_AUDN);
687
688 seq_printf(s, "\n AVI Infoframe (Data Island slot N=%d):",
689 HDMI_IFRAME_SLOT_AVI);
690 DBGFS_DUMP_DI(HDMI_SW_DI_N_HEAD_WORD, HDMI_IFRAME_SLOT_AVI);
691 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD0, HDMI_IFRAME_SLOT_AVI);
692 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD1, HDMI_IFRAME_SLOT_AVI);
693 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD2, HDMI_IFRAME_SLOT_AVI);
694 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD3, HDMI_IFRAME_SLOT_AVI);
695 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD4, HDMI_IFRAME_SLOT_AVI);
696 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD5, HDMI_IFRAME_SLOT_AVI);
697 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD6, HDMI_IFRAME_SLOT_AVI);
698 seq_printf(s, "\n\n AUDIO Infoframe (Data Island slot N=%d):",
699 HDMI_IFRAME_SLOT_AUDIO);
700 DBGFS_DUMP_DI(HDMI_SW_DI_N_HEAD_WORD, HDMI_IFRAME_SLOT_AUDIO);
701 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD0, HDMI_IFRAME_SLOT_AUDIO);
702 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD1, HDMI_IFRAME_SLOT_AUDIO);
703 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD2, HDMI_IFRAME_SLOT_AUDIO);
704 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD3, HDMI_IFRAME_SLOT_AUDIO);
705 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD4, HDMI_IFRAME_SLOT_AUDIO);
706 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD5, HDMI_IFRAME_SLOT_AUDIO);
707 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD6, HDMI_IFRAME_SLOT_AUDIO);
708 seq_printf(s, "\n\n VENDOR SPECIFIC Infoframe (Data Island slot N=%d):",
709 HDMI_IFRAME_SLOT_VENDOR);
710 DBGFS_DUMP_DI(HDMI_SW_DI_N_HEAD_WORD, HDMI_IFRAME_SLOT_VENDOR);
711 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD0, HDMI_IFRAME_SLOT_VENDOR);
712 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD1, HDMI_IFRAME_SLOT_VENDOR);
713 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD2, HDMI_IFRAME_SLOT_VENDOR);
714 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD3, HDMI_IFRAME_SLOT_VENDOR);
715 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD4, HDMI_IFRAME_SLOT_VENDOR);
716 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD5, HDMI_IFRAME_SLOT_VENDOR);
717 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD6, HDMI_IFRAME_SLOT_VENDOR);
718 seq_putc(s, '\n');
719 return 0;
720 }
721
722 static struct drm_info_list hdmi_debugfs_files[] = {
723 { "hdmi", hdmi_dbg_show, 0, NULL },
724 };
725
726 static int hdmi_debugfs_init(struct sti_hdmi *hdmi, struct drm_minor *minor)
727 {
728 unsigned int i;
729
730 for (i = 0; i < ARRAY_SIZE(hdmi_debugfs_files); i++)
731 hdmi_debugfs_files[i].data = hdmi;
732
733 return drm_debugfs_create_files(hdmi_debugfs_files,
734 ARRAY_SIZE(hdmi_debugfs_files),
735 minor->debugfs_root, minor);
736 }
737
738 static void sti_hdmi_disable(struct drm_bridge *bridge)
739 {
740 struct sti_hdmi *hdmi = bridge->driver_private;
741
742 u32 val = hdmi_read(hdmi, HDMI_CFG);
743
744 if (!hdmi->enabled)
745 return;
746
747 DRM_DEBUG_DRIVER("\n");
748
749 /* Disable HDMI */
750 val &= ~HDMI_CFG_DEVICE_EN;
751 hdmi_write(hdmi, val, HDMI_CFG);
752
753 hdmi_write(hdmi, 0xffffffff, HDMI_INT_CLR);
754
755 /* Stop the phy */
756 hdmi->phy_ops->stop(hdmi);
757
758 /* Reset info frame transmission */
759 hdmi_infoframe_reset(hdmi, HDMI_IFRAME_SLOT_AVI);
760 hdmi_infoframe_reset(hdmi, HDMI_IFRAME_SLOT_AUDIO);
761 hdmi_infoframe_reset(hdmi, HDMI_IFRAME_SLOT_VENDOR);
762
763 /* Set the default channel data to be a dark red */
764 hdmi_write(hdmi, 0x0000, HDMI_DFLT_CHL0_DAT);
765 hdmi_write(hdmi, 0x0000, HDMI_DFLT_CHL1_DAT);
766 hdmi_write(hdmi, 0x0060, HDMI_DFLT_CHL2_DAT);
767
768 /* Disable/unprepare hdmi clock */
769 clk_disable_unprepare(hdmi->clk_phy);
770 clk_disable_unprepare(hdmi->clk_tmds);
771 clk_disable_unprepare(hdmi->clk_pix);
772
773 hdmi->enabled = false;
774
775 cec_notifier_set_phys_addr(hdmi->notifier, CEC_PHYS_ADDR_INVALID);
776 }
777
778 /**
779 * sti_hdmi_audio_get_non_coherent_n() - get N parameter for non-coherent
780 * clocks. None-coherent clocks means that audio and TMDS clocks have not the
781 * same source (drifts between clocks). In this case assumption is that CTS is
782 * automatically calculated by hardware.
783 *
784 * @audio_fs: audio frame clock frequency in Hz
785 *
786 * Values computed are based on table described in HDMI specification 1.4b
787 *
788 * Returns n value.
789 */
790 static int sti_hdmi_audio_get_non_coherent_n(unsigned int audio_fs)
791 {
792 unsigned int n;
793
794 switch (audio_fs) {
795 case 32000:
796 n = 4096;
797 break;
798 case 44100:
799 n = 6272;
800 break;
801 case 48000:
802 n = 6144;
803 break;
804 case 88200:
805 n = 6272 * 2;
806 break;
807 case 96000:
808 n = 6144 * 2;
809 break;
810 case 176400:
811 n = 6272 * 4;
812 break;
813 case 192000:
814 n = 6144 * 4;
815 break;
816 default:
817 /* Not pre-defined, recommended value: 128 * fs / 1000 */
818 n = (audio_fs * 128) / 1000;
819 }
820
821 return n;
822 }
823
824 static int hdmi_audio_configure(struct sti_hdmi *hdmi)
825 {
826 int audio_cfg, n;
827 struct hdmi_audio_params *params = &hdmi->audio;
828 struct hdmi_audio_infoframe *info = &params->cea;
829
830 DRM_DEBUG_DRIVER("\n");
831
832 if (!hdmi->enabled)
833 return 0;
834
835 /* update N parameter */
836 n = sti_hdmi_audio_get_non_coherent_n(params->sample_rate);
837
838 DRM_DEBUG_DRIVER("Audio rate = %d Hz, TMDS clock = %d Hz, n = %d\n",
839 params->sample_rate, hdmi->mode.clock * 1000, n);
840 hdmi_write(hdmi, n, HDMI_AUDN);
841
842 /* update HDMI registers according to configuration */
843 audio_cfg = HDMI_AUD_CFG_SPDIF_DIV_2 | HDMI_AUD_CFG_DTS_INVALID |
844 HDMI_AUD_CFG_ONE_BIT_INVALID;
845
846 switch (info->channels) {
847 case 8:
848 audio_cfg |= HDMI_AUD_CFG_CH78_VALID;
849 case 6:
850 audio_cfg |= HDMI_AUD_CFG_CH56_VALID;
851 case 4:
852 audio_cfg |= HDMI_AUD_CFG_CH34_VALID | HDMI_AUD_CFG_8CH;
853 case 2:
854 audio_cfg |= HDMI_AUD_CFG_CH12_VALID;
855 break;
856 default:
857 DRM_ERROR("ERROR: Unsupported number of channels (%d)!\n",
858 info->channels);
859 return -EINVAL;
860 }
861
862 hdmi_write(hdmi, audio_cfg, HDMI_AUDIO_CFG);
863
864 return hdmi_audio_infoframe_config(hdmi);
865 }
866
867 static void sti_hdmi_pre_enable(struct drm_bridge *bridge)
868 {
869 struct sti_hdmi *hdmi = bridge->driver_private;
870
871 DRM_DEBUG_DRIVER("\n");
872
873 if (hdmi->enabled)
874 return;
875
876 /* Prepare/enable clocks */
877 if (clk_prepare_enable(hdmi->clk_pix))
878 DRM_ERROR("Failed to prepare/enable hdmi_pix clk\n");
879 if (clk_prepare_enable(hdmi->clk_tmds))
880 DRM_ERROR("Failed to prepare/enable hdmi_tmds clk\n");
881 if (clk_prepare_enable(hdmi->clk_phy))
882 DRM_ERROR("Failed to prepare/enable hdmi_rejec_pll clk\n");
883
884 hdmi->enabled = true;
885
886 /* Program hdmi serializer and start phy */
887 if (!hdmi->phy_ops->start(hdmi)) {
888 DRM_ERROR("Unable to start hdmi phy\n");
889 return;
890 }
891
892 /* Program hdmi active area */
893 hdmi_active_area(hdmi);
894
895 /* Enable working interrupts */
896 hdmi_write(hdmi, HDMI_WORKING_INT, HDMI_INT_EN);
897
898 /* Program hdmi config */
899 hdmi_config(hdmi);
900
901 /* Program AVI infoframe */
902 if (hdmi_avi_infoframe_config(hdmi))
903 DRM_ERROR("Unable to configure AVI infoframe\n");
904
905 if (hdmi->audio.enabled) {
906 if (hdmi_audio_configure(hdmi))
907 DRM_ERROR("Unable to configure audio\n");
908 } else {
909 hdmi_audio_infoframe_config(hdmi);
910 }
911
912 /* Program VS infoframe */
913 if (hdmi_vendor_infoframe_config(hdmi))
914 DRM_ERROR("Unable to configure VS infoframe\n");
915
916 /* Sw reset */
917 hdmi_swreset(hdmi);
918 }
919
920 static void sti_hdmi_set_mode(struct drm_bridge *bridge,
921 const struct drm_display_mode *mode,
922 const struct drm_display_mode *adjusted_mode)
923 {
924 struct sti_hdmi *hdmi = bridge->driver_private;
925 int ret;
926
927 DRM_DEBUG_DRIVER("\n");
928
929 /* Copy the drm display mode in the connector local structure */
930 memcpy(&hdmi->mode, mode, sizeof(struct drm_display_mode));
931
932 /* Update clock framerate according to the selected mode */
933 ret = clk_set_rate(hdmi->clk_pix, mode->clock * 1000);
934 if (ret < 0) {
935 DRM_ERROR("Cannot set rate (%dHz) for hdmi_pix clk\n",
936 mode->clock * 1000);
937 return;
938 }
939 ret = clk_set_rate(hdmi->clk_phy, mode->clock * 1000);
940 if (ret < 0) {
941 DRM_ERROR("Cannot set rate (%dHz) for hdmi_rejection_pll clk\n",
942 mode->clock * 1000);
943 return;
944 }
945 }
946
947 static void sti_hdmi_bridge_nope(struct drm_bridge *bridge)
948 {
949 /* do nothing */
950 }
951
952 static const struct drm_bridge_funcs sti_hdmi_bridge_funcs = {
953 .pre_enable = sti_hdmi_pre_enable,
954 .enable = sti_hdmi_bridge_nope,
955 .disable = sti_hdmi_disable,
956 .post_disable = sti_hdmi_bridge_nope,
957 .mode_set = sti_hdmi_set_mode,
958 };
959
960 static int sti_hdmi_connector_get_modes(struct drm_connector *connector)
961 {
962 struct sti_hdmi_connector *hdmi_connector
963 = to_sti_hdmi_connector(connector);
964 struct sti_hdmi *hdmi = hdmi_connector->hdmi;
965 struct edid *edid;
966 int count;
967
968 DRM_DEBUG_DRIVER("\n");
969
970 edid = drm_get_edid(connector, hdmi->ddc_adapt);
971 if (!edid)
972 goto fail;
973
974 hdmi->hdmi_monitor = drm_detect_hdmi_monitor(edid);
975 DRM_DEBUG_KMS("%s : %dx%d cm\n",
976 (hdmi->hdmi_monitor ? "hdmi monitor" : "dvi monitor"),
977 edid->width_cm, edid->height_cm);
978 cec_notifier_set_phys_addr_from_edid(hdmi->notifier, edid);
979
980 count = drm_add_edid_modes(connector, edid);
981 drm_connector_update_edid_property(connector, edid);
982
983 kfree(edid);
984 return count;
985
986 fail:
987 DRM_ERROR("Can't read HDMI EDID\n");
988 return 0;
989 }
990
991 #define CLK_TOLERANCE_HZ 50
992
993 static int sti_hdmi_connector_mode_valid(struct drm_connector *connector,
994 struct drm_display_mode *mode)
995 {
996 int target = mode->clock * 1000;
997 int target_min = target - CLK_TOLERANCE_HZ;
998 int target_max = target + CLK_TOLERANCE_HZ;
999 int result;
1000 struct sti_hdmi_connector *hdmi_connector
1001 = to_sti_hdmi_connector(connector);
1002 struct sti_hdmi *hdmi = hdmi_connector->hdmi;
1003
1004
1005 result = clk_round_rate(hdmi->clk_pix, target);
1006
1007 DRM_DEBUG_DRIVER("target rate = %d => available rate = %d\n",
1008 target, result);
1009
1010 if ((result < target_min) || (result > target_max)) {
1011 DRM_DEBUG_DRIVER("hdmi pixclk=%d not supported\n", target);
1012 return MODE_BAD;
1013 }
1014
1015 return MODE_OK;
1016 }
1017
1018 static const
1019 struct drm_connector_helper_funcs sti_hdmi_connector_helper_funcs = {
1020 .get_modes = sti_hdmi_connector_get_modes,
1021 .mode_valid = sti_hdmi_connector_mode_valid,
1022 };
1023
1024 /* get detection status of display device */
1025 static enum drm_connector_status
1026 sti_hdmi_connector_detect(struct drm_connector *connector, bool force)
1027 {
1028 struct sti_hdmi_connector *hdmi_connector
1029 = to_sti_hdmi_connector(connector);
1030 struct sti_hdmi *hdmi = hdmi_connector->hdmi;
1031
1032 DRM_DEBUG_DRIVER("\n");
1033
1034 if (hdmi->hpd) {
1035 DRM_DEBUG_DRIVER("hdmi cable connected\n");
1036 return connector_status_connected;
1037 }
1038
1039 DRM_DEBUG_DRIVER("hdmi cable disconnected\n");
1040 cec_notifier_set_phys_addr(hdmi->notifier, CEC_PHYS_ADDR_INVALID);
1041 return connector_status_disconnected;
1042 }
1043
1044 static void sti_hdmi_connector_init_property(struct drm_device *drm_dev,
1045 struct drm_connector *connector)
1046 {
1047 struct sti_hdmi_connector *hdmi_connector
1048 = to_sti_hdmi_connector(connector);
1049 struct sti_hdmi *hdmi = hdmi_connector->hdmi;
1050 struct drm_property *prop;
1051
1052 /* colorspace property */
1053 hdmi->colorspace = DEFAULT_COLORSPACE_MODE;
1054 prop = drm_property_create_enum(drm_dev, 0, "colorspace",
1055 colorspace_mode_names,
1056 ARRAY_SIZE(colorspace_mode_names));
1057 if (!prop) {
1058 DRM_ERROR("fails to create colorspace property\n");
1059 return;
1060 }
1061 hdmi_connector->colorspace_property = prop;
1062 drm_object_attach_property(&connector->base, prop, hdmi->colorspace);
1063 }
1064
1065 static int
1066 sti_hdmi_connector_set_property(struct drm_connector *connector,
1067 struct drm_connector_state *state,
1068 struct drm_property *property,
1069 uint64_t val)
1070 {
1071 struct sti_hdmi_connector *hdmi_connector
1072 = to_sti_hdmi_connector(connector);
1073 struct sti_hdmi *hdmi = hdmi_connector->hdmi;
1074
1075 if (property == hdmi_connector->colorspace_property) {
1076 hdmi->colorspace = val;
1077 return 0;
1078 }
1079
1080 DRM_ERROR("failed to set hdmi connector property\n");
1081 return -EINVAL;
1082 }
1083
1084 static int
1085 sti_hdmi_connector_get_property(struct drm_connector *connector,
1086 const struct drm_connector_state *state,
1087 struct drm_property *property,
1088 uint64_t *val)
1089 {
1090 struct sti_hdmi_connector *hdmi_connector
1091 = to_sti_hdmi_connector(connector);
1092 struct sti_hdmi *hdmi = hdmi_connector->hdmi;
1093
1094 if (property == hdmi_connector->colorspace_property) {
1095 *val = hdmi->colorspace;
1096 return 0;
1097 }
1098
1099 DRM_ERROR("failed to get hdmi connector property\n");
1100 return -EINVAL;
1101 }
1102
1103 static int sti_hdmi_late_register(struct drm_connector *connector)
1104 {
1105 struct sti_hdmi_connector *hdmi_connector
1106 = to_sti_hdmi_connector(connector);
1107 struct sti_hdmi *hdmi = hdmi_connector->hdmi;
1108
1109 if (hdmi_debugfs_init(hdmi, hdmi->drm_dev->primary)) {
1110 DRM_ERROR("HDMI debugfs setup failed\n");
1111 return -EINVAL;
1112 }
1113
1114 return 0;
1115 }
1116
1117 static const struct drm_connector_funcs sti_hdmi_connector_funcs = {
1118 .fill_modes = drm_helper_probe_single_connector_modes,
1119 .detect = sti_hdmi_connector_detect,
1120 .destroy = drm_connector_cleanup,
1121 .reset = drm_atomic_helper_connector_reset,
1122 .atomic_set_property = sti_hdmi_connector_set_property,
1123 .atomic_get_property = sti_hdmi_connector_get_property,
1124 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1125 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1126 .late_register = sti_hdmi_late_register,
1127 };
1128
1129 static struct drm_encoder *sti_hdmi_find_encoder(struct drm_device *dev)
1130 {
1131 struct drm_encoder *encoder;
1132
1133 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1134 if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS)
1135 return encoder;
1136 }
1137
1138 return NULL;
1139 }
1140
1141 static void hdmi_audio_shutdown(struct device *dev, void *data)
1142 {
1143 struct sti_hdmi *hdmi = dev_get_drvdata(dev);
1144 int audio_cfg;
1145
1146 DRM_DEBUG_DRIVER("\n");
1147
1148 /* disable audio */
1149 audio_cfg = HDMI_AUD_CFG_SPDIF_DIV_2 | HDMI_AUD_CFG_DTS_INVALID |
1150 HDMI_AUD_CFG_ONE_BIT_INVALID;
1151 hdmi_write(hdmi, audio_cfg, HDMI_AUDIO_CFG);
1152
1153 hdmi->audio.enabled = false;
1154 hdmi_audio_infoframe_config(hdmi);
1155 }
1156
1157 static int hdmi_audio_hw_params(struct device *dev,
1158 void *data,
1159 struct hdmi_codec_daifmt *daifmt,
1160 struct hdmi_codec_params *params)
1161 {
1162 struct sti_hdmi *hdmi = dev_get_drvdata(dev);
1163 int ret;
1164
1165 DRM_DEBUG_DRIVER("\n");
1166
1167 if ((daifmt->fmt != HDMI_I2S) || daifmt->bit_clk_inv ||
1168 daifmt->frame_clk_inv || daifmt->bit_clk_master ||
1169 daifmt->frame_clk_master) {
1170 dev_err(dev, "%s: Bad flags %d %d %d %d\n", __func__,
1171 daifmt->bit_clk_inv, daifmt->frame_clk_inv,
1172 daifmt->bit_clk_master,
1173 daifmt->frame_clk_master);
1174 return -EINVAL;
1175 }
1176
1177 hdmi->audio.sample_width = params->sample_width;
1178 hdmi->audio.sample_rate = params->sample_rate;
1179 hdmi->audio.cea = params->cea;
1180
1181 hdmi->audio.enabled = true;
1182
1183 ret = hdmi_audio_configure(hdmi);
1184 if (ret < 0)
1185 return ret;
1186
1187 return 0;
1188 }
1189
1190 static int hdmi_audio_digital_mute(struct device *dev, void *data, bool enable)
1191 {
1192 struct sti_hdmi *hdmi = dev_get_drvdata(dev);
1193
1194 DRM_DEBUG_DRIVER("%s\n", enable ? "enable" : "disable");
1195
1196 if (enable)
1197 hdmi_write(hdmi, HDMI_SAMPLE_FLAT_ALL, HDMI_SAMPLE_FLAT_MASK);
1198 else
1199 hdmi_write(hdmi, HDMI_SAMPLE_FLAT_NO, HDMI_SAMPLE_FLAT_MASK);
1200
1201 return 0;
1202 }
1203
1204 static int hdmi_audio_get_eld(struct device *dev, void *data, uint8_t *buf, size_t len)
1205 {
1206 struct sti_hdmi *hdmi = dev_get_drvdata(dev);
1207 struct drm_connector *connector = hdmi->drm_connector;
1208
1209 DRM_DEBUG_DRIVER("\n");
1210 memcpy(buf, connector->eld, min(sizeof(connector->eld), len));
1211
1212 return 0;
1213 }
1214
1215 static const struct hdmi_codec_ops audio_codec_ops = {
1216 .hw_params = hdmi_audio_hw_params,
1217 .audio_shutdown = hdmi_audio_shutdown,
1218 .digital_mute = hdmi_audio_digital_mute,
1219 .get_eld = hdmi_audio_get_eld,
1220 };
1221
1222 static int sti_hdmi_register_audio_driver(struct device *dev,
1223 struct sti_hdmi *hdmi)
1224 {
1225 struct hdmi_codec_pdata codec_data = {
1226 .ops = &audio_codec_ops,
1227 .max_i2s_channels = 8,
1228 .i2s = 1,
1229 };
1230
1231 DRM_DEBUG_DRIVER("\n");
1232
1233 hdmi->audio.enabled = false;
1234
1235 hdmi->audio_pdev = platform_device_register_data(
1236 dev, HDMI_CODEC_DRV_NAME, PLATFORM_DEVID_AUTO,
1237 &codec_data, sizeof(codec_data));
1238
1239 if (IS_ERR(hdmi->audio_pdev))
1240 return PTR_ERR(hdmi->audio_pdev);
1241
1242 DRM_INFO("%s Driver bound %s\n", HDMI_CODEC_DRV_NAME, dev_name(dev));
1243
1244 return 0;
1245 }
1246
1247 static int sti_hdmi_bind(struct device *dev, struct device *master, void *data)
1248 {
1249 struct sti_hdmi *hdmi = dev_get_drvdata(dev);
1250 struct drm_device *drm_dev = data;
1251 struct drm_encoder *encoder;
1252 struct sti_hdmi_connector *connector;
1253 struct drm_connector *drm_connector;
1254 struct drm_bridge *bridge;
1255 int err;
1256
1257 /* Set the drm device handle */
1258 hdmi->drm_dev = drm_dev;
1259
1260 encoder = sti_hdmi_find_encoder(drm_dev);
1261 if (!encoder)
1262 return -EINVAL;
1263
1264 connector = devm_kzalloc(dev, sizeof(*connector), GFP_KERNEL);
1265 if (!connector)
1266 return -EINVAL;
1267
1268 connector->hdmi = hdmi;
1269
1270 bridge = devm_kzalloc(dev, sizeof(*bridge), GFP_KERNEL);
1271 if (!bridge)
1272 return -EINVAL;
1273
1274 bridge->driver_private = hdmi;
1275 bridge->funcs = &sti_hdmi_bridge_funcs;
1276 drm_bridge_attach(encoder, bridge, NULL);
1277
1278 connector->encoder = encoder;
1279
1280 drm_connector = (struct drm_connector *)connector;
1281
1282 drm_connector->polled = DRM_CONNECTOR_POLL_HPD;
1283
1284 drm_connector_init(drm_dev, drm_connector,
1285 &sti_hdmi_connector_funcs, DRM_MODE_CONNECTOR_HDMIA);
1286 drm_connector_helper_add(drm_connector,
1287 &sti_hdmi_connector_helper_funcs);
1288
1289 /* initialise property */
1290 sti_hdmi_connector_init_property(drm_dev, drm_connector);
1291
1292 hdmi->drm_connector = drm_connector;
1293
1294 err = drm_connector_attach_encoder(drm_connector, encoder);
1295 if (err) {
1296 DRM_ERROR("Failed to attach a connector to a encoder\n");
1297 goto err_sysfs;
1298 }
1299
1300 err = sti_hdmi_register_audio_driver(dev, hdmi);
1301 if (err) {
1302 DRM_ERROR("Failed to attach an audio codec\n");
1303 goto err_sysfs;
1304 }
1305
1306 /* Initialize audio infoframe */
1307 err = hdmi_audio_infoframe_init(&hdmi->audio.cea);
1308 if (err) {
1309 DRM_ERROR("Failed to init audio infoframe\n");
1310 goto err_sysfs;
1311 }
1312
1313 /* Enable default interrupts */
1314 hdmi_write(hdmi, HDMI_DEFAULT_INT, HDMI_INT_EN);
1315
1316 return 0;
1317
1318 err_sysfs:
1319 hdmi->drm_connector = NULL;
1320 return -EINVAL;
1321 }
1322
1323 static void sti_hdmi_unbind(struct device *dev,
1324 struct device *master, void *data)
1325 {
1326 }
1327
1328 static const struct component_ops sti_hdmi_ops = {
1329 .bind = sti_hdmi_bind,
1330 .unbind = sti_hdmi_unbind,
1331 };
1332
1333 static const struct of_device_id hdmi_of_match[] = {
1334 {
1335 .compatible = "st,stih407-hdmi",
1336 .data = &tx3g4c28phy_ops,
1337 }, {
1338 /* end node */
1339 }
1340 };
1341 MODULE_DEVICE_TABLE(of, hdmi_of_match);
1342
1343 static int sti_hdmi_probe(struct platform_device *pdev)
1344 {
1345 struct device *dev = &pdev->dev;
1346 struct sti_hdmi *hdmi;
1347 struct device_node *np = dev->of_node;
1348 struct resource *res;
1349 struct device_node *ddc;
1350 int ret;
1351
1352 DRM_INFO("%s\n", __func__);
1353
1354 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
1355 if (!hdmi)
1356 return -ENOMEM;
1357
1358 ddc = of_parse_phandle(pdev->dev.of_node, "ddc", 0);
1359 if (ddc) {
1360 hdmi->ddc_adapt = of_get_i2c_adapter_by_node(ddc);
1361 of_node_put(ddc);
1362 if (!hdmi->ddc_adapt)
1363 return -EPROBE_DEFER;
1364 }
1365
1366 hdmi->dev = pdev->dev;
1367
1368 /* Get resources */
1369 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi-reg");
1370 if (!res) {
1371 DRM_ERROR("Invalid hdmi resource\n");
1372 ret = -ENOMEM;
1373 goto release_adapter;
1374 }
1375 hdmi->regs = devm_ioremap_nocache(dev, res->start, resource_size(res));
1376 if (!hdmi->regs) {
1377 ret = -ENOMEM;
1378 goto release_adapter;
1379 }
1380
1381 hdmi->phy_ops = (struct hdmi_phy_ops *)
1382 of_match_node(hdmi_of_match, np)->data;
1383
1384 /* Get clock resources */
1385 hdmi->clk_pix = devm_clk_get(dev, "pix");
1386 if (IS_ERR(hdmi->clk_pix)) {
1387 DRM_ERROR("Cannot get hdmi_pix clock\n");
1388 ret = PTR_ERR(hdmi->clk_pix);
1389 goto release_adapter;
1390 }
1391
1392 hdmi->clk_tmds = devm_clk_get(dev, "tmds");
1393 if (IS_ERR(hdmi->clk_tmds)) {
1394 DRM_ERROR("Cannot get hdmi_tmds clock\n");
1395 ret = PTR_ERR(hdmi->clk_tmds);
1396 goto release_adapter;
1397 }
1398
1399 hdmi->clk_phy = devm_clk_get(dev, "phy");
1400 if (IS_ERR(hdmi->clk_phy)) {
1401 DRM_ERROR("Cannot get hdmi_phy clock\n");
1402 ret = PTR_ERR(hdmi->clk_phy);
1403 goto release_adapter;
1404 }
1405
1406 hdmi->clk_audio = devm_clk_get(dev, "audio");
1407 if (IS_ERR(hdmi->clk_audio)) {
1408 DRM_ERROR("Cannot get hdmi_audio clock\n");
1409 ret = PTR_ERR(hdmi->clk_audio);
1410 goto release_adapter;
1411 }
1412
1413 hdmi->hpd = readl(hdmi->regs + HDMI_STA) & HDMI_STA_HOT_PLUG;
1414
1415 init_waitqueue_head(&hdmi->wait_event);
1416
1417 hdmi->irq = platform_get_irq_byname(pdev, "irq");
1418 if (hdmi->irq < 0) {
1419 DRM_ERROR("Cannot get HDMI irq\n");
1420 ret = hdmi->irq;
1421 goto release_adapter;
1422 }
1423
1424 ret = devm_request_threaded_irq(dev, hdmi->irq, hdmi_irq,
1425 hdmi_irq_thread, IRQF_ONESHOT, dev_name(dev), hdmi);
1426 if (ret) {
1427 DRM_ERROR("Failed to register HDMI interrupt\n");
1428 goto release_adapter;
1429 }
1430
1431 hdmi->notifier = cec_notifier_get(&pdev->dev);
1432 if (!hdmi->notifier)
1433 goto release_adapter;
1434
1435 hdmi->reset = devm_reset_control_get(dev, "hdmi");
1436 /* Take hdmi out of reset */
1437 if (!IS_ERR(hdmi->reset))
1438 reset_control_deassert(hdmi->reset);
1439
1440 platform_set_drvdata(pdev, hdmi);
1441
1442 return component_add(&pdev->dev, &sti_hdmi_ops);
1443
1444 release_adapter:
1445 i2c_put_adapter(hdmi->ddc_adapt);
1446
1447 return ret;
1448 }
1449
1450 static int sti_hdmi_remove(struct platform_device *pdev)
1451 {
1452 struct sti_hdmi *hdmi = dev_get_drvdata(&pdev->dev);
1453
1454 cec_notifier_set_phys_addr(hdmi->notifier, CEC_PHYS_ADDR_INVALID);
1455
1456 i2c_put_adapter(hdmi->ddc_adapt);
1457 if (hdmi->audio_pdev)
1458 platform_device_unregister(hdmi->audio_pdev);
1459 component_del(&pdev->dev, &sti_hdmi_ops);
1460
1461 cec_notifier_put(hdmi->notifier);
1462 return 0;
1463 }
1464
1465 struct platform_driver sti_hdmi_driver = {
1466 .driver = {
1467 .name = "sti-hdmi",
1468 .owner = THIS_MODULE,
1469 .of_match_table = hdmi_of_match,
1470 },
1471 .probe = sti_hdmi_probe,
1472 .remove = sti_hdmi_remove,
1473 };
1474
1475 MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@st.com>");
1476 MODULE_DESCRIPTION("STMicroelectronics SoC DRM driver");
1477 MODULE_LICENSE("GPL");
Linux with added FPC-III support