?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
dt-bindings: mtd: ingenic: Use standard ecc-engine property
[linux/fpc-iii.git] / drivers / gpu / drm / vc4 / vc4_hdmi.c
blob88fd5df7e7dc65fe1cbd23fe4d40e42253a052f3
1 /*
2 * Copyright (C) 2015 Broadcom
3 * Copyright (c) 2014 The Linux Foundation. All rights reserved.
4 * Copyright (C) 2013 Red Hat
5 * Author: Rob Clark <robdclark@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20 /**
21 * DOC: VC4 Falcon HDMI module
22 *
23 * The HDMI core has a state machine and a PHY. On BCM2835, most of
24 * the unit operates off of the HSM clock from CPRMAN. It also
25 * internally uses the PLLH_PIX clock for the PHY.
26 *
27 * HDMI infoframes are kept within a small packet ram, where each
28 * packet can be individually enabled for including in a frame.
29 *
30 * HDMI audio is implemented entirely within the HDMI IP block. A
31 * register in the HDMI encoder takes SPDIF frames from the DMA engine
32 * and transfers them over an internal MAI (multi-channel audio
33 * interconnect) bus to the encoder side for insertion into the video
34 * blank regions.
35 *
36 * The driver's HDMI encoder does not yet support power management.
37 * The HDMI encoder's power domain and the HSM/pixel clocks are kept
38 * continuously running, and only the HDMI logic and packet ram are
39 * powered off/on at disable/enable time.
40 *
41 * The driver does not yet support CEC control, though the HDMI
42 * encoder block has CEC support.
43 */
44
45 #include <drm/drm_atomic_helper.h>
46 #include <drm/drm_edid.h>
47 #include <drm/drm_probe_helper.h>
48 #include <linux/clk.h>
49 #include <linux/component.h>
50 #include <linux/i2c.h>
51 #include <linux/of_address.h>
52 #include <linux/of_gpio.h>
53 #include <linux/of_platform.h>
54 #include <linux/pm_runtime.h>
55 #include <linux/rational.h>
56 #include <sound/dmaengine_pcm.h>
57 #include <sound/pcm_drm_eld.h>
58 #include <sound/pcm_params.h>
59 #include <sound/soc.h>
60 #include "media/cec.h"
61 #include "vc4_drv.h"
62 #include "vc4_regs.h"
63
64 #define HSM_CLOCK_FREQ 163682864
65 #define CEC_CLOCK_FREQ 40000
66 #define CEC_CLOCK_DIV (HSM_CLOCK_FREQ / CEC_CLOCK_FREQ)
67
68 /* HDMI audio information */
69 struct vc4_hdmi_audio {
70 struct snd_soc_card card;
71 struct snd_soc_dai_link link;
72 int samplerate;
73 int channels;
74 struct snd_dmaengine_dai_dma_data dma_data;
75 struct snd_pcm_substream *substream;
76 };
77
78 /* General HDMI hardware state. */
79 struct vc4_hdmi {
80 struct platform_device *pdev;
81
82 struct drm_encoder *encoder;
83 struct drm_connector *connector;
84
85 struct vc4_hdmi_audio audio;
86
87 struct i2c_adapter *ddc;
88 void __iomem *hdmicore_regs;
89 void __iomem *hd_regs;
90 int hpd_gpio;
91 bool hpd_active_low;
92
93 struct cec_adapter *cec_adap;
94 struct cec_msg cec_rx_msg;
95 bool cec_tx_ok;
96 bool cec_irq_was_rx;
97
98 struct clk *pixel_clock;
99 struct clk *hsm_clock;
100 };
101
102 #define HDMI_READ(offset) readl(vc4->hdmi->hdmicore_regs + offset)
103 #define HDMI_WRITE(offset, val) writel(val, vc4->hdmi->hdmicore_regs + offset)
104 #define HD_READ(offset) readl(vc4->hdmi->hd_regs + offset)
105 #define HD_WRITE(offset, val) writel(val, vc4->hdmi->hd_regs + offset)
106
107 /* VC4 HDMI encoder KMS struct */
108 struct vc4_hdmi_encoder {
109 struct vc4_encoder base;
110 bool hdmi_monitor;
111 bool limited_rgb_range;
112 };
113
114 static inline struct vc4_hdmi_encoder *
115 to_vc4_hdmi_encoder(struct drm_encoder *encoder)
116 {
117 return container_of(encoder, struct vc4_hdmi_encoder, base.base);
118 }
119
120 /* VC4 HDMI connector KMS struct */
121 struct vc4_hdmi_connector {
122 struct drm_connector base;
123
124 /* Since the connector is attached to just the one encoder,
125 * this is the reference to it so we can do the best_encoder()
126 * hook.
127 */
128 struct drm_encoder *encoder;
129 };
130
131 static inline struct vc4_hdmi_connector *
132 to_vc4_hdmi_connector(struct drm_connector *connector)
133 {
134 return container_of(connector, struct vc4_hdmi_connector, base);
135 }
136
137 #define HDMI_REG(reg) { reg, #reg }
138 static const struct {
139 u32 reg;
140 const char *name;
141 } hdmi_regs[] = {
142 HDMI_REG(VC4_HDMI_CORE_REV),
143 HDMI_REG(VC4_HDMI_SW_RESET_CONTROL),
144 HDMI_REG(VC4_HDMI_HOTPLUG_INT),
145 HDMI_REG(VC4_HDMI_HOTPLUG),
146 HDMI_REG(VC4_HDMI_MAI_CHANNEL_MAP),
147 HDMI_REG(VC4_HDMI_MAI_CONFIG),
148 HDMI_REG(VC4_HDMI_MAI_FORMAT),
149 HDMI_REG(VC4_HDMI_AUDIO_PACKET_CONFIG),
150 HDMI_REG(VC4_HDMI_RAM_PACKET_CONFIG),
151 HDMI_REG(VC4_HDMI_HORZA),
152 HDMI_REG(VC4_HDMI_HORZB),
153 HDMI_REG(VC4_HDMI_FIFO_CTL),
154 HDMI_REG(VC4_HDMI_SCHEDULER_CONTROL),
155 HDMI_REG(VC4_HDMI_VERTA0),
156 HDMI_REG(VC4_HDMI_VERTA1),
157 HDMI_REG(VC4_HDMI_VERTB0),
158 HDMI_REG(VC4_HDMI_VERTB1),
159 HDMI_REG(VC4_HDMI_TX_PHY_RESET_CTL),
160 HDMI_REG(VC4_HDMI_TX_PHY_CTL0),
161
162 HDMI_REG(VC4_HDMI_CEC_CNTRL_1),
163 HDMI_REG(VC4_HDMI_CEC_CNTRL_2),
164 HDMI_REG(VC4_HDMI_CEC_CNTRL_3),
165 HDMI_REG(VC4_HDMI_CEC_CNTRL_4),
166 HDMI_REG(VC4_HDMI_CEC_CNTRL_5),
167 HDMI_REG(VC4_HDMI_CPU_STATUS),
168 HDMI_REG(VC4_HDMI_CPU_MASK_STATUS),
169
170 HDMI_REG(VC4_HDMI_CEC_RX_DATA_1),
171 HDMI_REG(VC4_HDMI_CEC_RX_DATA_2),
172 HDMI_REG(VC4_HDMI_CEC_RX_DATA_3),
173 HDMI_REG(VC4_HDMI_CEC_RX_DATA_4),
174 HDMI_REG(VC4_HDMI_CEC_TX_DATA_1),
175 HDMI_REG(VC4_HDMI_CEC_TX_DATA_2),
176 HDMI_REG(VC4_HDMI_CEC_TX_DATA_3),
177 HDMI_REG(VC4_HDMI_CEC_TX_DATA_4),
178 };
179
180 static const struct {
181 u32 reg;
182 const char *name;
183 } hd_regs[] = {
184 HDMI_REG(VC4_HD_M_CTL),
185 HDMI_REG(VC4_HD_MAI_CTL),
186 HDMI_REG(VC4_HD_MAI_THR),
187 HDMI_REG(VC4_HD_MAI_FMT),
188 HDMI_REG(VC4_HD_MAI_SMP),
189 HDMI_REG(VC4_HD_VID_CTL),
190 HDMI_REG(VC4_HD_CSC_CTL),
191 HDMI_REG(VC4_HD_FRAME_COUNT),
192 };
193
194 #ifdef CONFIG_DEBUG_FS
195 int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)
196 {
197 struct drm_info_node *node = (struct drm_info_node *)m->private;
198 struct drm_device *dev = node->minor->dev;
199 struct vc4_dev *vc4 = to_vc4_dev(dev);
200 int i;
201
202 for (i = 0; i < ARRAY_SIZE(hdmi_regs); i++) {
203 seq_printf(m, "%s (0x%04x): 0x%08x\n",
204 hdmi_regs[i].name, hdmi_regs[i].reg,
205 HDMI_READ(hdmi_regs[i].reg));
206 }
207
208 for (i = 0; i < ARRAY_SIZE(hd_regs); i++) {
209 seq_printf(m, "%s (0x%04x): 0x%08x\n",
210 hd_regs[i].name, hd_regs[i].reg,
211 HD_READ(hd_regs[i].reg));
212 }
213
214 return 0;
215 }
216 #endif /* CONFIG_DEBUG_FS */
217
218 static void vc4_hdmi_dump_regs(struct drm_device *dev)
219 {
220 struct vc4_dev *vc4 = to_vc4_dev(dev);
221 int i;
222
223 for (i = 0; i < ARRAY_SIZE(hdmi_regs); i++) {
224 DRM_INFO("0x%04x (%s): 0x%08x\n",
225 hdmi_regs[i].reg, hdmi_regs[i].name,
226 HDMI_READ(hdmi_regs[i].reg));
227 }
228 for (i = 0; i < ARRAY_SIZE(hd_regs); i++) {
229 DRM_INFO("0x%04x (%s): 0x%08x\n",
230 hd_regs[i].reg, hd_regs[i].name,
231 HD_READ(hd_regs[i].reg));
232 }
233 }
234
235 static enum drm_connector_status
236 vc4_hdmi_connector_detect(struct drm_connector *connector, bool force)
237 {
238 struct drm_device *dev = connector->dev;
239 struct vc4_dev *vc4 = to_vc4_dev(dev);
240
241 if (vc4->hdmi->hpd_gpio) {
242 if (gpio_get_value_cansleep(vc4->hdmi->hpd_gpio) ^
243 vc4->hdmi->hpd_active_low)
244 return connector_status_connected;
245 cec_phys_addr_invalidate(vc4->hdmi->cec_adap);
246 return connector_status_disconnected;
247 }
248
249 if (drm_probe_ddc(vc4->hdmi->ddc))
250 return connector_status_connected;
251
252 if (HDMI_READ(VC4_HDMI_HOTPLUG) & VC4_HDMI_HOTPLUG_CONNECTED)
253 return connector_status_connected;
254 cec_phys_addr_invalidate(vc4->hdmi->cec_adap);
255 return connector_status_disconnected;
256 }
257
258 static void vc4_hdmi_connector_destroy(struct drm_connector *connector)
259 {
260 drm_connector_unregister(connector);
261 drm_connector_cleanup(connector);
262 }
263
264 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector)
265 {
266 struct vc4_hdmi_connector *vc4_connector =
267 to_vc4_hdmi_connector(connector);
268 struct drm_encoder *encoder = vc4_connector->encoder;
269 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
270 struct drm_device *dev = connector->dev;
271 struct vc4_dev *vc4 = to_vc4_dev(dev);
272 int ret = 0;
273 struct edid *edid;
274
275 edid = drm_get_edid(connector, vc4->hdmi->ddc);
276 cec_s_phys_addr_from_edid(vc4->hdmi->cec_adap, edid);
277 if (!edid)
278 return -ENODEV;
279
280 vc4_encoder->hdmi_monitor = drm_detect_hdmi_monitor(edid);
281
282 drm_connector_update_edid_property(connector, edid);
283 ret = drm_add_edid_modes(connector, edid);
284 kfree(edid);
285
286 return ret;
287 }
288
289 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = {
290 .detect = vc4_hdmi_connector_detect,
291 .fill_modes = drm_helper_probe_single_connector_modes,
292 .destroy = vc4_hdmi_connector_destroy,
293 .reset = drm_atomic_helper_connector_reset,
294 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
295 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
296 };
297
298 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = {
299 .get_modes = vc4_hdmi_connector_get_modes,
300 };
301
302 static struct drm_connector *vc4_hdmi_connector_init(struct drm_device *dev,
303 struct drm_encoder *encoder)
304 {
305 struct drm_connector *connector;
306 struct vc4_hdmi_connector *hdmi_connector;
307 int ret;
308
309 hdmi_connector = devm_kzalloc(dev->dev, sizeof(*hdmi_connector),
310 GFP_KERNEL);
311 if (!hdmi_connector)
312 return ERR_PTR(-ENOMEM);
313 connector = &hdmi_connector->base;
314
315 hdmi_connector->encoder = encoder;
316
317 drm_connector_init(dev, connector, &vc4_hdmi_connector_funcs,
318 DRM_MODE_CONNECTOR_HDMIA);
319 drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs);
320
321 /* Create and attach TV margin props to this connector. */
322 ret = drm_mode_create_tv_margin_properties(dev);
323 if (ret)
324 return ERR_PTR(ret);
325
326 drm_connector_attach_tv_margin_properties(connector);
327
328 connector->polled = (DRM_CONNECTOR_POLL_CONNECT |
329 DRM_CONNECTOR_POLL_DISCONNECT);
330
331 connector->interlace_allowed = 1;
332 connector->doublescan_allowed = 0;
333
334 drm_connector_attach_encoder(connector, encoder);
335
336 return connector;
337 }
338
339 static void vc4_hdmi_encoder_destroy(struct drm_encoder *encoder)
340 {
341 drm_encoder_cleanup(encoder);
342 }
343
344 static const struct drm_encoder_funcs vc4_hdmi_encoder_funcs = {
345 .destroy = vc4_hdmi_encoder_destroy,
346 };
347
348 static int vc4_hdmi_stop_packet(struct drm_encoder *encoder,
349 enum hdmi_infoframe_type type)
350 {
351 struct drm_device *dev = encoder->dev;
352 struct vc4_dev *vc4 = to_vc4_dev(dev);
353 u32 packet_id = type - 0x80;
354
355 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG,
356 HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id));
357
358 return wait_for(!(HDMI_READ(VC4_HDMI_RAM_PACKET_STATUS) &
359 BIT(packet_id)), 100);
360 }
361
362 static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder,
363 union hdmi_infoframe *frame)
364 {
365 struct drm_device *dev = encoder->dev;
366 struct vc4_dev *vc4 = to_vc4_dev(dev);
367 u32 packet_id = frame->any.type - 0x80;
368 u32 packet_reg = VC4_HDMI_RAM_PACKET(packet_id);
369 uint8_t buffer[VC4_HDMI_PACKET_STRIDE];
370 ssize_t len, i;
371 int ret;
372
373 WARN_ONCE(!(HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) &
374 VC4_HDMI_RAM_PACKET_ENABLE),
375 "Packet RAM has to be on to store the packet.");
376
377 len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer));
378 if (len < 0)
379 return;
380
381 ret = vc4_hdmi_stop_packet(encoder, frame->any.type);
382 if (ret) {
383 DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret);
384 return;
385 }
386
387 for (i = 0; i < len; i += 7) {
388 HDMI_WRITE(packet_reg,
389 buffer[i + 0] << 0 |
390 buffer[i + 1] << 8 |
391 buffer[i + 2] << 16);
392 packet_reg += 4;
393
394 HDMI_WRITE(packet_reg,
395 buffer[i + 3] << 0 |
396 buffer[i + 4] << 8 |
397 buffer[i + 5] << 16 |
398 buffer[i + 6] << 24);
399 packet_reg += 4;
400 }
401
402 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG,
403 HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) | BIT(packet_id));
404 ret = wait_for((HDMI_READ(VC4_HDMI_RAM_PACKET_STATUS) &
405 BIT(packet_id)), 100);
406 if (ret)
407 DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret);
408 }
409
410 static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder)
411 {
412 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
413 struct vc4_dev *vc4 = encoder->dev->dev_private;
414 struct vc4_hdmi *hdmi = vc4->hdmi;
415 struct drm_connector_state *cstate = hdmi->connector->state;
416 struct drm_crtc *crtc = encoder->crtc;
417 const struct drm_display_mode *mode = &crtc->state->adjusted_mode;
418 union hdmi_infoframe frame;
419 int ret;
420
421 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
422 hdmi->connector, mode);
423 if (ret < 0) {
424 DRM_ERROR("couldn't fill AVI infoframe\n");
425 return;
426 }
427
428 drm_hdmi_avi_infoframe_quant_range(&frame.avi,
429 hdmi->connector, mode,
430 vc4_encoder->limited_rgb_range ?
431 HDMI_QUANTIZATION_RANGE_LIMITED :
432 HDMI_QUANTIZATION_RANGE_FULL);
433
434 frame.avi.right_bar = cstate->tv.margins.right;
435 frame.avi.left_bar = cstate->tv.margins.left;
436 frame.avi.top_bar = cstate->tv.margins.top;
437 frame.avi.bottom_bar = cstate->tv.margins.bottom;
438
439 vc4_hdmi_write_infoframe(encoder, &frame);
440 }
441
442 static void vc4_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
443 {
444 union hdmi_infoframe frame;
445 int ret;
446
447 ret = hdmi_spd_infoframe_init(&frame.spd, "Broadcom", "Videocore");
448 if (ret < 0) {
449 DRM_ERROR("couldn't fill SPD infoframe\n");
450 return;
451 }
452
453 frame.spd.sdi = HDMI_SPD_SDI_PC;
454
455 vc4_hdmi_write_infoframe(encoder, &frame);
456 }
457
458 static void vc4_hdmi_set_audio_infoframe(struct drm_encoder *encoder)
459 {
460 struct drm_device *drm = encoder->dev;
461 struct vc4_dev *vc4 = drm->dev_private;
462 struct vc4_hdmi *hdmi = vc4->hdmi;
463 union hdmi_infoframe frame;
464 int ret;
465
466 ret = hdmi_audio_infoframe_init(&frame.audio);
467
468 frame.audio.coding_type = HDMI_AUDIO_CODING_TYPE_STREAM;
469 frame.audio.sample_frequency = HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM;
470 frame.audio.sample_size = HDMI_AUDIO_SAMPLE_SIZE_STREAM;
471 frame.audio.channels = hdmi->audio.channels;
472
473 vc4_hdmi_write_infoframe(encoder, &frame);
474 }
475
476 static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder)
477 {
478 vc4_hdmi_set_avi_infoframe(encoder);
479 vc4_hdmi_set_spd_infoframe(encoder);
480 }
481
482 static void vc4_hdmi_encoder_disable(struct drm_encoder *encoder)
483 {
484 struct drm_device *dev = encoder->dev;
485 struct vc4_dev *vc4 = to_vc4_dev(dev);
486 struct vc4_hdmi *hdmi = vc4->hdmi;
487 int ret;
488
489 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG, 0);
490
491 HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0xf << 16);
492 HD_WRITE(VC4_HD_VID_CTL,
493 HD_READ(VC4_HD_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
494
495 clk_disable_unprepare(hdmi->pixel_clock);
496
497 ret = pm_runtime_put(&hdmi->pdev->dev);
498 if (ret < 0)
499 DRM_ERROR("Failed to release power domain: %d\n", ret);
500 }
501
502 static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder)
503 {
504 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
505 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
506 struct drm_device *dev = encoder->dev;
507 struct vc4_dev *vc4 = to_vc4_dev(dev);
508 struct vc4_hdmi *hdmi = vc4->hdmi;
509 bool debug_dump_regs = false;
510 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
511 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
512 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
513 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
514 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
515 VC4_HDMI_VERTA_VSP) |
516 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
517 VC4_HDMI_VERTA_VFP) |
518 VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL));
519 u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
520 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
521 VC4_HDMI_VERTB_VBP));
522 u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
523 VC4_SET_FIELD(mode->crtc_vtotal -
524 mode->crtc_vsync_end -
525 interlaced,
526 VC4_HDMI_VERTB_VBP));
527 u32 csc_ctl;
528 int ret;
529
530 ret = pm_runtime_get_sync(&hdmi->pdev->dev);
531 if (ret < 0) {
532 DRM_ERROR("Failed to retain power domain: %d\n", ret);
533 return;
534 }
535
536 ret = clk_set_rate(hdmi->pixel_clock,
537 mode->clock * 1000 *
538 ((mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1));
539 if (ret) {
540 DRM_ERROR("Failed to set pixel clock rate: %d\n", ret);
541 return;
542 }
543
544 ret = clk_prepare_enable(hdmi->pixel_clock);
545 if (ret) {
546 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret);
547 return;
548 }
549
550 HDMI_WRITE(VC4_HDMI_SW_RESET_CONTROL,
551 VC4_HDMI_SW_RESET_HDMI |
552 VC4_HDMI_SW_RESET_FORMAT_DETECT);
553
554 HDMI_WRITE(VC4_HDMI_SW_RESET_CONTROL, 0);
555
556 /* PHY should be in reset, like
557 * vc4_hdmi_encoder_disable() does.
558 */
559 HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0xf << 16);
560
561 HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0);
562
563 if (debug_dump_regs) {
564 DRM_INFO("HDMI regs before:\n");
565 vc4_hdmi_dump_regs(dev);
566 }
567
568 HD_WRITE(VC4_HD_VID_CTL, 0);
569
570 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL,
571 HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) |
572 VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT |
573 VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS);
574
575 HDMI_WRITE(VC4_HDMI_HORZA,
576 (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) |
577 (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) |
578 VC4_SET_FIELD(mode->hdisplay * pixel_rep,
579 VC4_HDMI_HORZA_HAP));
580
581 HDMI_WRITE(VC4_HDMI_HORZB,
582 VC4_SET_FIELD((mode->htotal -
583 mode->hsync_end) * pixel_rep,
584 VC4_HDMI_HORZB_HBP) |
585 VC4_SET_FIELD((mode->hsync_end -
586 mode->hsync_start) * pixel_rep,
587 VC4_HDMI_HORZB_HSP) |
588 VC4_SET_FIELD((mode->hsync_start -
589 mode->hdisplay) * pixel_rep,
590 VC4_HDMI_HORZB_HFP));
591
592 HDMI_WRITE(VC4_HDMI_VERTA0, verta);
593 HDMI_WRITE(VC4_HDMI_VERTA1, verta);
594
595 HDMI_WRITE(VC4_HDMI_VERTB0, vertb_even);
596 HDMI_WRITE(VC4_HDMI_VERTB1, vertb);
597
598 HD_WRITE(VC4_HD_VID_CTL,
599 (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
600 (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
601
602 csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR,
603 VC4_HD_CSC_CTL_ORDER);
604
605 if (vc4_encoder->hdmi_monitor &&
606 drm_default_rgb_quant_range(mode) ==
607 HDMI_QUANTIZATION_RANGE_LIMITED) {
608 /* CEA VICs other than #1 requre limited range RGB
609 * output unless overridden by an AVI infoframe.
610 * Apply a colorspace conversion to squash 0-255 down
611 * to 16-235. The matrix here is:
612 *
613 * [ 0 0 0.8594 16]
614 * [ 0 0.8594 0 16]
615 * [ 0.8594 0 0 16]
616 * [ 0 0 0 1]
617 */
618 csc_ctl |= VC4_HD_CSC_CTL_ENABLE;
619 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC;
620 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
621 VC4_HD_CSC_CTL_MODE);
622
623 HD_WRITE(VC4_HD_CSC_12_11, (0x000 << 16) | 0x000);
624 HD_WRITE(VC4_HD_CSC_14_13, (0x100 << 16) | 0x6e0);
625 HD_WRITE(VC4_HD_CSC_22_21, (0x6e0 << 16) | 0x000);
626 HD_WRITE(VC4_HD_CSC_24_23, (0x100 << 16) | 0x000);
627 HD_WRITE(VC4_HD_CSC_32_31, (0x000 << 16) | 0x6e0);
628 HD_WRITE(VC4_HD_CSC_34_33, (0x100 << 16) | 0x000);
629 vc4_encoder->limited_rgb_range = true;
630 } else {
631 vc4_encoder->limited_rgb_range = false;
632 }
633
634 /* The RGB order applies even when CSC is disabled. */
635 HD_WRITE(VC4_HD_CSC_CTL, csc_ctl);
636
637 HDMI_WRITE(VC4_HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N);
638
639 if (debug_dump_regs) {
640 DRM_INFO("HDMI regs after:\n");
641 vc4_hdmi_dump_regs(dev);
642 }
643
644 HD_WRITE(VC4_HD_VID_CTL,
645 HD_READ(VC4_HD_VID_CTL) |
646 VC4_HD_VID_CTL_ENABLE |
647 VC4_HD_VID_CTL_UNDERFLOW_ENABLE |
648 VC4_HD_VID_CTL_FRAME_COUNTER_RESET);
649
650 if (vc4_encoder->hdmi_monitor) {
651 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL,
652 HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) |
653 VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
654
655 ret = wait_for(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) &
656 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000);
657 WARN_ONCE(ret, "Timeout waiting for "
658 "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
659 } else {
660 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG,
661 HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) &
662 ~(VC4_HDMI_RAM_PACKET_ENABLE));
663 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL,
664 HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) &
665 ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
666
667 ret = wait_for(!(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) &
668 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000);
669 WARN_ONCE(ret, "Timeout waiting for "
670 "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
671 }
672
673 if (vc4_encoder->hdmi_monitor) {
674 u32 drift;
675
676 WARN_ON(!(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) &
677 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE));
678 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL,
679 HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) |
680 VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT);
681
682 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG,
683 VC4_HDMI_RAM_PACKET_ENABLE);
684
685 vc4_hdmi_set_infoframes(encoder);
686
687 drift = HDMI_READ(VC4_HDMI_FIFO_CTL);
688 drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK;
689
690 HDMI_WRITE(VC4_HDMI_FIFO_CTL,
691 drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
692 HDMI_WRITE(VC4_HDMI_FIFO_CTL,
693 drift | VC4_HDMI_FIFO_CTL_RECENTER);
694 usleep_range(1000, 1100);
695 HDMI_WRITE(VC4_HDMI_FIFO_CTL,
696 drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
697 HDMI_WRITE(VC4_HDMI_FIFO_CTL,
698 drift | VC4_HDMI_FIFO_CTL_RECENTER);
699
700 ret = wait_for(HDMI_READ(VC4_HDMI_FIFO_CTL) &
701 VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1);
702 WARN_ONCE(ret, "Timeout waiting for "
703 "VC4_HDMI_FIFO_CTL_RECENTER_DONE");
704 }
705 }
706
707 static enum drm_mode_status
708 vc4_hdmi_encoder_mode_valid(struct drm_encoder *crtc,
709 const struct drm_display_mode *mode)
710 {
711 /* HSM clock must be 108% of the pixel clock. Additionally,
712 * the AXI clock needs to be at least 25% of pixel clock, but
713 * HSM ends up being the limiting factor.
714 */
715 if (mode->clock > HSM_CLOCK_FREQ / (1000 * 108 / 100))
716 return MODE_CLOCK_HIGH;
717
718 return MODE_OK;
719 }
720
721 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = {
722 .mode_valid = vc4_hdmi_encoder_mode_valid,
723 .disable = vc4_hdmi_encoder_disable,
724 .enable = vc4_hdmi_encoder_enable,
725 };
726
727 /* HDMI audio codec callbacks */
728 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *hdmi)
729 {
730 struct drm_device *drm = hdmi->encoder->dev;
731 struct vc4_dev *vc4 = to_vc4_dev(drm);
732 u32 hsm_clock = clk_get_rate(hdmi->hsm_clock);
733 unsigned long n, m;
734
735 rational_best_approximation(hsm_clock, hdmi->audio.samplerate,
736 VC4_HD_MAI_SMP_N_MASK >>
737 VC4_HD_MAI_SMP_N_SHIFT,
738 (VC4_HD_MAI_SMP_M_MASK >>
739 VC4_HD_MAI_SMP_M_SHIFT) + 1,
740 &n, &m);
741
742 HD_WRITE(VC4_HD_MAI_SMP,
743 VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) |
744 VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M));
745 }
746
747 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *hdmi)
748 {
749 struct drm_encoder *encoder = hdmi->encoder;
750 struct drm_crtc *crtc = encoder->crtc;
751 struct drm_device *drm = encoder->dev;
752 struct vc4_dev *vc4 = to_vc4_dev(drm);
753 const struct drm_display_mode *mode = &crtc->state->adjusted_mode;
754 u32 samplerate = hdmi->audio.samplerate;
755 u32 n, cts;
756 u64 tmp;
757
758 n = 128 * samplerate / 1000;
759 tmp = (u64)(mode->clock * 1000) * n;
760 do_div(tmp, 128 * samplerate);
761 cts = tmp;
762
763 HDMI_WRITE(VC4_HDMI_CRP_CFG,
764 VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN |
765 VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N));
766
767 /*
768 * We could get slightly more accurate clocks in some cases by
769 * providing a CTS_1 value. The two CTS values are alternated
770 * between based on the period fields
771 */
772 HDMI_WRITE(VC4_HDMI_CTS_0, cts);
773 HDMI_WRITE(VC4_HDMI_CTS_1, cts);
774 }
775
776 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai)
777 {
778 struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai);
779
780 return snd_soc_card_get_drvdata(card);
781 }
782
783 static int vc4_hdmi_audio_startup(struct snd_pcm_substream *substream,
784 struct snd_soc_dai *dai)
785 {
786 struct vc4_hdmi *hdmi = dai_to_hdmi(dai);
787 struct drm_encoder *encoder = hdmi->encoder;
788 struct vc4_dev *vc4 = to_vc4_dev(encoder->dev);
789 int ret;
790
791 if (hdmi->audio.substream && hdmi->audio.substream != substream)
792 return -EINVAL;
793
794 hdmi->audio.substream = substream;
795
796 /*
797 * If the HDMI encoder hasn't probed, or the encoder is
798 * currently in DVI mode, treat the codec dai as missing.
799 */
800 if (!encoder->crtc || !(HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) &
801 VC4_HDMI_RAM_PACKET_ENABLE))
802 return -ENODEV;
803
804 ret = snd_pcm_hw_constraint_eld(substream->runtime,
805 hdmi->connector->eld);
806 if (ret)
807 return ret;
808
809 return 0;
810 }
811
812 static int vc4_hdmi_audio_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
813 {
814 return 0;
815 }
816
817 static void vc4_hdmi_audio_reset(struct vc4_hdmi *hdmi)
818 {
819 struct drm_encoder *encoder = hdmi->encoder;
820 struct drm_device *drm = encoder->dev;
821 struct device *dev = &hdmi->pdev->dev;
822 struct vc4_dev *vc4 = to_vc4_dev(drm);
823 int ret;
824
825 ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO);
826 if (ret)
827 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret);
828
829 HD_WRITE(VC4_HD_MAI_CTL, VC4_HD_MAI_CTL_RESET);
830 HD_WRITE(VC4_HD_MAI_CTL, VC4_HD_MAI_CTL_ERRORF);
831 HD_WRITE(VC4_HD_MAI_CTL, VC4_HD_MAI_CTL_FLUSH);
832 }
833
834 static void vc4_hdmi_audio_shutdown(struct snd_pcm_substream *substream,
835 struct snd_soc_dai *dai)
836 {
837 struct vc4_hdmi *hdmi = dai_to_hdmi(dai);
838
839 if (substream != hdmi->audio.substream)
840 return;
841
842 vc4_hdmi_audio_reset(hdmi);
843
844 hdmi->audio.substream = NULL;
845 }
846
847 /* HDMI audio codec callbacks */
848 static int vc4_hdmi_audio_hw_params(struct snd_pcm_substream *substream,
849 struct snd_pcm_hw_params *params,
850 struct snd_soc_dai *dai)
851 {
852 struct vc4_hdmi *hdmi = dai_to_hdmi(dai);
853 struct drm_encoder *encoder = hdmi->encoder;
854 struct drm_device *drm = encoder->dev;
855 struct device *dev = &hdmi->pdev->dev;
856 struct vc4_dev *vc4 = to_vc4_dev(drm);
857 u32 audio_packet_config, channel_mask;
858 u32 channel_map, i;
859
860 if (substream != hdmi->audio.substream)
861 return -EINVAL;
862
863 dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
864 params_rate(params), params_width(params),
865 params_channels(params));
866
867 hdmi->audio.channels = params_channels(params);
868 hdmi->audio.samplerate = params_rate(params);
869
870 HD_WRITE(VC4_HD_MAI_CTL,
871 VC4_HD_MAI_CTL_RESET |
872 VC4_HD_MAI_CTL_FLUSH |
873 VC4_HD_MAI_CTL_DLATE |
874 VC4_HD_MAI_CTL_ERRORE |
875 VC4_HD_MAI_CTL_ERRORF);
876
877 vc4_hdmi_audio_set_mai_clock(hdmi);
878
879 audio_packet_config =
880 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT |
881 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS |
882 VC4_SET_FIELD(0xf, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER);
883
884 channel_mask = GENMASK(hdmi->audio.channels - 1, 0);
885 audio_packet_config |= VC4_SET_FIELD(channel_mask,
886 VC4_HDMI_AUDIO_PACKET_CEA_MASK);
887
888 /* Set the MAI threshold. This logic mimics the firmware's. */
889 if (hdmi->audio.samplerate > 96000) {
890 HD_WRITE(VC4_HD_MAI_THR,
891 VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQHIGH) |
892 VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQLOW));
893 } else if (hdmi->audio.samplerate > 48000) {
894 HD_WRITE(VC4_HD_MAI_THR,
895 VC4_SET_FIELD(0x14, VC4_HD_MAI_THR_DREQHIGH) |
896 VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQLOW));
897 } else {
898 HD_WRITE(VC4_HD_MAI_THR,
899 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH) |
900 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW) |
901 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQHIGH) |
902 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQLOW));
903 }
904
905 HDMI_WRITE(VC4_HDMI_MAI_CONFIG,
906 VC4_HDMI_MAI_CONFIG_BIT_REVERSE |
907 VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK));
908
909 channel_map = 0;
910 for (i = 0; i < 8; i++) {
911 if (channel_mask & BIT(i))
912 channel_map |= i << (3 * i);
913 }
914
915 HDMI_WRITE(VC4_HDMI_MAI_CHANNEL_MAP, channel_map);
916 HDMI_WRITE(VC4_HDMI_AUDIO_PACKET_CONFIG, audio_packet_config);
917 vc4_hdmi_set_n_cts(hdmi);
918
919 return 0;
920 }
921
922 static int vc4_hdmi_audio_trigger(struct snd_pcm_substream *substream, int cmd,
923 struct snd_soc_dai *dai)
924 {
925 struct vc4_hdmi *hdmi = dai_to_hdmi(dai);
926 struct drm_encoder *encoder = hdmi->encoder;
927 struct drm_device *drm = encoder->dev;
928 struct vc4_dev *vc4 = to_vc4_dev(drm);
929
930 switch (cmd) {
931 case SNDRV_PCM_TRIGGER_START:
932 vc4_hdmi_set_audio_infoframe(encoder);
933 HDMI_WRITE(VC4_HDMI_TX_PHY_CTL0,
934 HDMI_READ(VC4_HDMI_TX_PHY_CTL0) &
935 ~VC4_HDMI_TX_PHY_RNG_PWRDN);
936 HD_WRITE(VC4_HD_MAI_CTL,
937 VC4_SET_FIELD(hdmi->audio.channels,
938 VC4_HD_MAI_CTL_CHNUM) |
939 VC4_HD_MAI_CTL_ENABLE);
940 break;
941 case SNDRV_PCM_TRIGGER_STOP:
942 HD_WRITE(VC4_HD_MAI_CTL,
943 VC4_HD_MAI_CTL_DLATE |
944 VC4_HD_MAI_CTL_ERRORE |
945 VC4_HD_MAI_CTL_ERRORF);
946 HDMI_WRITE(VC4_HDMI_TX_PHY_CTL0,
947 HDMI_READ(VC4_HDMI_TX_PHY_CTL0) |
948 VC4_HDMI_TX_PHY_RNG_PWRDN);
949 break;
950 default:
951 break;
952 }
953
954 return 0;
955 }
956
957 static inline struct vc4_hdmi *
958 snd_component_to_hdmi(struct snd_soc_component *component)
959 {
960 struct snd_soc_card *card = snd_soc_component_get_drvdata(component);
961
962 return snd_soc_card_get_drvdata(card);
963 }
964
965 static int vc4_hdmi_audio_eld_ctl_info(struct snd_kcontrol *kcontrol,
966 struct snd_ctl_elem_info *uinfo)
967 {
968 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
969 struct vc4_hdmi *hdmi = snd_component_to_hdmi(component);
970
971 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
972 uinfo->count = sizeof(hdmi->connector->eld);
973
974 return 0;
975 }
976
977 static int vc4_hdmi_audio_eld_ctl_get(struct snd_kcontrol *kcontrol,
978 struct snd_ctl_elem_value *ucontrol)
979 {
980 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
981 struct vc4_hdmi *hdmi = snd_component_to_hdmi(component);
982
983 memcpy(ucontrol->value.bytes.data, hdmi->connector->eld,
984 sizeof(hdmi->connector->eld));
985
986 return 0;
987 }
988
989 static const struct snd_kcontrol_new vc4_hdmi_audio_controls[] = {
990 {
991 .access = SNDRV_CTL_ELEM_ACCESS_READ |
992 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
993 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
994 .name = "ELD",
995 .info = vc4_hdmi_audio_eld_ctl_info,
996 .get = vc4_hdmi_audio_eld_ctl_get,
997 },
998 };
999
1000 static const struct snd_soc_dapm_widget vc4_hdmi_audio_widgets[] = {
1001 SND_SOC_DAPM_OUTPUT("TX"),
1002 };
1003
1004 static const struct snd_soc_dapm_route vc4_hdmi_audio_routes[] = {
1005 { "TX", NULL, "Playback" },
1006 };
1007
1008 static const struct snd_soc_component_driver vc4_hdmi_audio_component_drv = {
1009 .controls = vc4_hdmi_audio_controls,
1010 .num_controls = ARRAY_SIZE(vc4_hdmi_audio_controls),
1011 .dapm_widgets = vc4_hdmi_audio_widgets,
1012 .num_dapm_widgets = ARRAY_SIZE(vc4_hdmi_audio_widgets),
1013 .dapm_routes = vc4_hdmi_audio_routes,
1014 .num_dapm_routes = ARRAY_SIZE(vc4_hdmi_audio_routes),
1015 .idle_bias_on = 1,
1016 .use_pmdown_time = 1,
1017 .endianness = 1,
1018 .non_legacy_dai_naming = 1,
1019 };
1020
1021 static const struct snd_soc_dai_ops vc4_hdmi_audio_dai_ops = {
1022 .startup = vc4_hdmi_audio_startup,
1023 .shutdown = vc4_hdmi_audio_shutdown,
1024 .hw_params = vc4_hdmi_audio_hw_params,
1025 .set_fmt = vc4_hdmi_audio_set_fmt,
1026 .trigger = vc4_hdmi_audio_trigger,
1027 };
1028
1029 static struct snd_soc_dai_driver vc4_hdmi_audio_codec_dai_drv = {
1030 .name = "vc4-hdmi-hifi",
1031 .playback = {
1032 .stream_name = "Playback",
1033 .channels_min = 2,
1034 .channels_max = 8,
1035 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
1036 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
1037 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
1038 SNDRV_PCM_RATE_192000,
1039 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1040 },
1041 };
1042
1043 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = {
1044 .name = "vc4-hdmi-cpu-dai-component",
1045 };
1046
1047 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai)
1048 {
1049 struct vc4_hdmi *hdmi = dai_to_hdmi(dai);
1050
1051 snd_soc_dai_init_dma_data(dai, &hdmi->audio.dma_data, NULL);
1052
1053 return 0;
1054 }
1055
1056 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = {
1057 .name = "vc4-hdmi-cpu-dai",
1058 .probe = vc4_hdmi_audio_cpu_dai_probe,
1059 .playback = {
1060 .stream_name = "Playback",
1061 .channels_min = 1,
1062 .channels_max = 8,
1063 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
1064 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
1065 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
1066 SNDRV_PCM_RATE_192000,
1067 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1068 },
1069 .ops = &vc4_hdmi_audio_dai_ops,
1070 };
1071
1072 static const struct snd_dmaengine_pcm_config pcm_conf = {
1073 .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx",
1074 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
1075 };
1076
1077 static int vc4_hdmi_audio_init(struct vc4_hdmi *hdmi)
1078 {
1079 struct snd_soc_dai_link *dai_link = &hdmi->audio.link;
1080 struct snd_soc_card *card = &hdmi->audio.card;
1081 struct device *dev = &hdmi->pdev->dev;
1082 const __be32 *addr;
1083 int ret;
1084
1085 if (!of_find_property(dev->of_node, "dmas", NULL)) {
1086 dev_warn(dev,
1087 "'dmas' DT property is missing, no HDMI audio\n");
1088 return 0;
1089 }
1090
1091 /*
1092 * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve
1093 * the bus address specified in the DT, because the physical address
1094 * (the one returned by platform_get_resource()) is not appropriate
1095 * for DMA transfers.
1096 * This VC/MMU should probably be exposed to avoid this kind of hacks.
1097 */
1098 addr = of_get_address(dev->of_node, 1, NULL, NULL);
1099 hdmi->audio.dma_data.addr = be32_to_cpup(addr) + VC4_HD_MAI_DATA;
1100 hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1101 hdmi->audio.dma_data.maxburst = 2;
1102
1103 ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0);
1104 if (ret) {
1105 dev_err(dev, "Could not register PCM component: %d\n", ret);
1106 return ret;
1107 }
1108
1109 ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp,
1110 &vc4_hdmi_audio_cpu_dai_drv, 1);
1111 if (ret) {
1112 dev_err(dev, "Could not register CPU DAI: %d\n", ret);
1113 return ret;
1114 }
1115
1116 /* register component and codec dai */
1117 ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_component_drv,
1118 &vc4_hdmi_audio_codec_dai_drv, 1);
1119 if (ret) {
1120 dev_err(dev, "Could not register component: %d\n", ret);
1121 return ret;
1122 }
1123
1124 dai_link->name = "MAI";
1125 dai_link->stream_name = "MAI PCM";
1126 dai_link->codec_dai_name = vc4_hdmi_audio_codec_dai_drv.name;
1127 dai_link->cpu_dai_name = dev_name(dev);
1128 dai_link->codec_name = dev_name(dev);
1129 dai_link->platform_name = dev_name(dev);
1130
1131 card->dai_link = dai_link;
1132 card->num_links = 1;
1133 card->name = "vc4-hdmi";
1134 card->dev = dev;
1135
1136 /*
1137 * Be careful, snd_soc_register_card() calls dev_set_drvdata() and
1138 * stores a pointer to the snd card object in dev->driver_data. This
1139 * means we cannot use it for something else. The hdmi back-pointer is
1140 * now stored in card->drvdata and should be retrieved with
1141 * snd_soc_card_get_drvdata() if needed.
1142 */
1143 snd_soc_card_set_drvdata(card, hdmi);
1144 ret = devm_snd_soc_register_card(dev, card);
1145 if (ret)
1146 dev_err(dev, "Could not register sound card: %d\n", ret);
1147
1148 return ret;
1149
1150 }
1151
1152 #ifdef CONFIG_DRM_VC4_HDMI_CEC
1153 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv)
1154 {
1155 struct vc4_dev *vc4 = priv;
1156 struct vc4_hdmi *hdmi = vc4->hdmi;
1157
1158 if (hdmi->cec_irq_was_rx) {
1159 if (hdmi->cec_rx_msg.len)
1160 cec_received_msg(hdmi->cec_adap, &hdmi->cec_rx_msg);
1161 } else if (hdmi->cec_tx_ok) {
1162 cec_transmit_done(hdmi->cec_adap, CEC_TX_STATUS_OK,
1163 0, 0, 0, 0);
1164 } else {
1165 /*
1166 * This CEC implementation makes 1 retry, so if we
1167 * get a NACK, then that means it made 2 attempts.
1168 */
1169 cec_transmit_done(hdmi->cec_adap, CEC_TX_STATUS_NACK,
1170 0, 2, 0, 0);
1171 }
1172 return IRQ_HANDLED;
1173 }
1174
1175 static void vc4_cec_read_msg(struct vc4_dev *vc4, u32 cntrl1)
1176 {
1177 struct cec_msg *msg = &vc4->hdmi->cec_rx_msg;
1178 unsigned int i;
1179
1180 msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >>
1181 VC4_HDMI_CEC_REC_WRD_CNT_SHIFT);
1182 for (i = 0; i < msg->len; i += 4) {
1183 u32 val = HDMI_READ(VC4_HDMI_CEC_RX_DATA_1 + i);
1184
1185 msg->msg[i] = val & 0xff;
1186 msg->msg[i + 1] = (val >> 8) & 0xff;
1187 msg->msg[i + 2] = (val >> 16) & 0xff;
1188 msg->msg[i + 3] = (val >> 24) & 0xff;
1189 }
1190 }
1191
1192 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv)
1193 {
1194 struct vc4_dev *vc4 = priv;
1195 struct vc4_hdmi *hdmi = vc4->hdmi;
1196 u32 stat = HDMI_READ(VC4_HDMI_CPU_STATUS);
1197 u32 cntrl1, cntrl5;
1198
1199 if (!(stat & VC4_HDMI_CPU_CEC))
1200 return IRQ_NONE;
1201 hdmi->cec_rx_msg.len = 0;
1202 cntrl1 = HDMI_READ(VC4_HDMI_CEC_CNTRL_1);
1203 cntrl5 = HDMI_READ(VC4_HDMI_CEC_CNTRL_5);
1204 hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT;
1205 if (hdmi->cec_irq_was_rx) {
1206 vc4_cec_read_msg(vc4, cntrl1);
1207 cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
1208 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, cntrl1);
1209 cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
1210 } else {
1211 hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD;
1212 cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
1213 }
1214 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, cntrl1);
1215 HDMI_WRITE(VC4_HDMI_CPU_CLEAR, VC4_HDMI_CPU_CEC);
1216
1217 return IRQ_WAKE_THREAD;
1218 }
1219
1220 static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable)
1221 {
1222 struct vc4_dev *vc4 = cec_get_drvdata(adap);
1223 /* clock period in microseconds */
1224 const u32 usecs = 1000000 / CEC_CLOCK_FREQ;
1225 u32 val = HDMI_READ(VC4_HDMI_CEC_CNTRL_5);
1226
1227 val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET |
1228 VC4_HDMI_CEC_CNT_TO_4700_US_MASK |
1229 VC4_HDMI_CEC_CNT_TO_4500_US_MASK);
1230 val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) |
1231 ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT);
1232
1233 if (enable) {
1234 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_5, val |
1235 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
1236 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_5, val);
1237 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_2,
1238 ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) |
1239 ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) |
1240 ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) |
1241 ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) |
1242 ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT));
1243 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_3,
1244 ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) |
1245 ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) |
1246 ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) |
1247 ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT));
1248 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_4,
1249 ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) |
1250 ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) |
1251 ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) |
1252 ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT));
1253
1254 HDMI_WRITE(VC4_HDMI_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC);
1255 } else {
1256 HDMI_WRITE(VC4_HDMI_CPU_MASK_SET, VC4_HDMI_CPU_CEC);
1257 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_5, val |
1258 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
1259 }
1260 return 0;
1261 }
1262
1263 static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr)
1264 {
1265 struct vc4_dev *vc4 = cec_get_drvdata(adap);
1266
1267 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1,
1268 (HDMI_READ(VC4_HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) |
1269 (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT);
1270 return 0;
1271 }
1272
1273 static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
1274 u32 signal_free_time, struct cec_msg *msg)
1275 {
1276 struct vc4_dev *vc4 = cec_get_drvdata(adap);
1277 u32 val;
1278 unsigned int i;
1279
1280 for (i = 0; i < msg->len; i += 4)
1281 HDMI_WRITE(VC4_HDMI_CEC_TX_DATA_1 + i,
1282 (msg->msg[i]) |
1283 (msg->msg[i + 1] << 8) |
1284 (msg->msg[i + 2] << 16) |
1285 (msg->msg[i + 3] << 24));
1286
1287 val = HDMI_READ(VC4_HDMI_CEC_CNTRL_1);
1288 val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
1289 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, val);
1290 val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK;
1291 val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT;
1292 val |= VC4_HDMI_CEC_START_XMIT_BEGIN;
1293
1294 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, val);
1295 return 0;
1296 }
1297
1298 static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = {
1299 .adap_enable = vc4_hdmi_cec_adap_enable,
1300 .adap_log_addr = vc4_hdmi_cec_adap_log_addr,
1301 .adap_transmit = vc4_hdmi_cec_adap_transmit,
1302 };
1303 #endif
1304
1305 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data)
1306 {
1307 struct platform_device *pdev = to_platform_device(dev);
1308 struct drm_device *drm = dev_get_drvdata(master);
1309 struct vc4_dev *vc4 = drm->dev_private;
1310 struct vc4_hdmi *hdmi;
1311 struct vc4_hdmi_encoder *vc4_hdmi_encoder;
1312 struct device_node *ddc_node;
1313 u32 value;
1314 int ret;
1315
1316 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
1317 if (!hdmi)
1318 return -ENOMEM;
1319
1320 vc4_hdmi_encoder = devm_kzalloc(dev, sizeof(*vc4_hdmi_encoder),
1321 GFP_KERNEL);
1322 if (!vc4_hdmi_encoder)
1323 return -ENOMEM;
1324 vc4_hdmi_encoder->base.type = VC4_ENCODER_TYPE_HDMI;
1325 hdmi->encoder = &vc4_hdmi_encoder->base.base;
1326
1327 hdmi->pdev = pdev;
1328 hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0);
1329 if (IS_ERR(hdmi->hdmicore_regs))
1330 return PTR_ERR(hdmi->hdmicore_regs);
1331
1332 hdmi->hd_regs = vc4_ioremap_regs(pdev, 1);
1333 if (IS_ERR(hdmi->hd_regs))
1334 return PTR_ERR(hdmi->hd_regs);
1335
1336 hdmi->pixel_clock = devm_clk_get(dev, "pixel");
1337 if (IS_ERR(hdmi->pixel_clock)) {
1338 DRM_ERROR("Failed to get pixel clock\n");
1339 return PTR_ERR(hdmi->pixel_clock);
1340 }
1341 hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
1342 if (IS_ERR(hdmi->hsm_clock)) {
1343 DRM_ERROR("Failed to get HDMI state machine clock\n");
1344 return PTR_ERR(hdmi->hsm_clock);
1345 }
1346
1347 ddc_node = of_parse_phandle(dev->of_node, "ddc", 0);
1348 if (!ddc_node) {
1349 DRM_ERROR("Failed to find ddc node in device tree\n");
1350 return -ENODEV;
1351 }
1352
1353 hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
1354 of_node_put(ddc_node);
1355 if (!hdmi->ddc) {
1356 DRM_DEBUG("Failed to get ddc i2c adapter by node\n");
1357 return -EPROBE_DEFER;
1358 }
1359
1360 /* This is the rate that is set by the firmware. The number
1361 * needs to be a bit higher than the pixel clock rate
1362 * (generally 148.5Mhz).
1363 */
1364 ret = clk_set_rate(hdmi->hsm_clock, HSM_CLOCK_FREQ);
1365 if (ret) {
1366 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret);
1367 goto err_put_i2c;
1368 }
1369
1370 ret = clk_prepare_enable(hdmi->hsm_clock);
1371 if (ret) {
1372 DRM_ERROR("Failed to turn on HDMI state machine clock: %d\n",
1373 ret);
1374 goto err_put_i2c;
1375 }
1376
1377 /* Only use the GPIO HPD pin if present in the DT, otherwise
1378 * we'll use the HDMI core's register.
1379 */
1380 if (of_find_property(dev->of_node, "hpd-gpios", &value)) {
1381 enum of_gpio_flags hpd_gpio_flags;
1382
1383 hdmi->hpd_gpio = of_get_named_gpio_flags(dev->of_node,
1384 "hpd-gpios", 0,
1385 &hpd_gpio_flags);
1386 if (hdmi->hpd_gpio < 0) {
1387 ret = hdmi->hpd_gpio;
1388 goto err_unprepare_hsm;
1389 }
1390
1391 hdmi->hpd_active_low = hpd_gpio_flags & OF_GPIO_ACTIVE_LOW;
1392 }
1393
1394 vc4->hdmi = hdmi;
1395
1396 /* HDMI core must be enabled. */
1397 if (!(HD_READ(VC4_HD_M_CTL) & VC4_HD_M_ENABLE)) {
1398 HD_WRITE(VC4_HD_M_CTL, VC4_HD_M_SW_RST);
1399 udelay(1);
1400 HD_WRITE(VC4_HD_M_CTL, 0);
1401
1402 HD_WRITE(VC4_HD_M_CTL, VC4_HD_M_ENABLE);
1403 }
1404 pm_runtime_enable(dev);
1405
1406 drm_encoder_init(drm, hdmi->encoder, &vc4_hdmi_encoder_funcs,
1407 DRM_MODE_ENCODER_TMDS, NULL);
1408 drm_encoder_helper_add(hdmi->encoder, &vc4_hdmi_encoder_helper_funcs);
1409
1410 hdmi->connector = vc4_hdmi_connector_init(drm, hdmi->encoder);
1411 if (IS_ERR(hdmi->connector)) {
1412 ret = PTR_ERR(hdmi->connector);
1413 goto err_destroy_encoder;
1414 }
1415 #ifdef CONFIG_DRM_VC4_HDMI_CEC
1416 hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops,
1417 vc4, "vc4",
1418 CEC_CAP_TRANSMIT |
1419 CEC_CAP_LOG_ADDRS |
1420 CEC_CAP_PASSTHROUGH |
1421 CEC_CAP_RC, 1);
1422 ret = PTR_ERR_OR_ZERO(hdmi->cec_adap);
1423 if (ret < 0)
1424 goto err_destroy_conn;
1425 HDMI_WRITE(VC4_HDMI_CPU_MASK_SET, 0xffffffff);
1426 value = HDMI_READ(VC4_HDMI_CEC_CNTRL_1);
1427 value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK;
1428 /*
1429 * Set the logical address to Unregistered and set the clock
1430 * divider: the hsm_clock rate and this divider setting will
1431 * give a 40 kHz CEC clock.
1432 */
1433 value |= VC4_HDMI_CEC_ADDR_MASK |
1434 (4091 << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT);
1435 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, value);
1436 ret = devm_request_threaded_irq(dev, platform_get_irq(pdev, 0),
1437 vc4_cec_irq_handler,
1438 vc4_cec_irq_handler_thread, 0,
1439 "vc4 hdmi cec", vc4);
1440 if (ret)
1441 goto err_delete_cec_adap;
1442 ret = cec_register_adapter(hdmi->cec_adap, dev);
1443 if (ret < 0)
1444 goto err_delete_cec_adap;
1445 #endif
1446
1447 ret = vc4_hdmi_audio_init(hdmi);
1448 if (ret)
1449 goto err_destroy_encoder;
1450
1451 return 0;
1452
1453 #ifdef CONFIG_DRM_VC4_HDMI_CEC
1454 err_delete_cec_adap:
1455 cec_delete_adapter(hdmi->cec_adap);
1456 err_destroy_conn:
1457 vc4_hdmi_connector_destroy(hdmi->connector);
1458 #endif
1459 err_destroy_encoder:
1460 vc4_hdmi_encoder_destroy(hdmi->encoder);
1461 err_unprepare_hsm:
1462 clk_disable_unprepare(hdmi->hsm_clock);
1463 pm_runtime_disable(dev);
1464 err_put_i2c:
1465 put_device(&hdmi->ddc->dev);
1466
1467 return ret;
1468 }
1469
1470 static void vc4_hdmi_unbind(struct device *dev, struct device *master,
1471 void *data)
1472 {
1473 struct drm_device *drm = dev_get_drvdata(master);
1474 struct vc4_dev *vc4 = drm->dev_private;
1475 struct vc4_hdmi *hdmi = vc4->hdmi;
1476
1477 cec_unregister_adapter(hdmi->cec_adap);
1478 vc4_hdmi_connector_destroy(hdmi->connector);
1479 vc4_hdmi_encoder_destroy(hdmi->encoder);
1480
1481 clk_disable_unprepare(hdmi->hsm_clock);
1482 pm_runtime_disable(dev);
1483
1484 put_device(&hdmi->ddc->dev);
1485
1486 vc4->hdmi = NULL;
1487 }
1488
1489 static const struct component_ops vc4_hdmi_ops = {
1490 .bind = vc4_hdmi_bind,
1491 .unbind = vc4_hdmi_unbind,
1492 };
1493
1494 static int vc4_hdmi_dev_probe(struct platform_device *pdev)
1495 {
1496 return component_add(&pdev->dev, &vc4_hdmi_ops);
1497 }
1498
1499 static int vc4_hdmi_dev_remove(struct platform_device *pdev)
1500 {
1501 component_del(&pdev->dev, &vc4_hdmi_ops);
1502 return 0;
1503 }
1504
1505 static const struct of_device_id vc4_hdmi_dt_match[] = {
1506 { .compatible = "brcm,bcm2835-hdmi" },
1507 {}
1508 };
1509
1510 struct platform_driver vc4_hdmi_driver = {
1511 .probe = vc4_hdmi_dev_probe,
1512 .remove = vc4_hdmi_dev_remove,
1513 .driver = {
1514 .name = "vc4_hdmi",
1515 .of_match_table = vc4_hdmi_dt_match,
1516 },
1517 };
Linux with added FPC-III support