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dt-bindings: mtd: ingenic: Use standard ecc-engine property
[linux/fpc-iii.git] / drivers / iio / accel / bmc150-accel-core.c
blob383c802eb5b86a3d4865d28cecde8fba5319fdff
1 /*
2 * 3-axis accelerometer driver supporting following Bosch-Sensortec chips:
3 * - BMC150
4 * - BMI055
5 * - BMA255
6 * - BMA250E
7 * - BMA222E
8 * - BMA280
9 *
10 * Copyright (c) 2014, Intel Corporation.
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms and conditions of the GNU General Public License,
14 * version 2, as published by the Free Software Foundation.
15 *
16 * This program is distributed in the hope it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 */
21
22 #include <linux/module.h>
23 #include <linux/i2c.h>
24 #include <linux/interrupt.h>
25 #include <linux/delay.h>
26 #include <linux/slab.h>
27 #include <linux/acpi.h>
28 #include <linux/pm.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/iio/iio.h>
31 #include <linux/iio/sysfs.h>
32 #include <linux/iio/buffer.h>
33 #include <linux/iio/events.h>
34 #include <linux/iio/trigger.h>
35 #include <linux/iio/trigger_consumer.h>
36 #include <linux/iio/triggered_buffer.h>
37 #include <linux/regmap.h>
38
39 #include "bmc150-accel.h"
40
41 #define BMC150_ACCEL_DRV_NAME "bmc150_accel"
42 #define BMC150_ACCEL_IRQ_NAME "bmc150_accel_event"
43
44 #define BMC150_ACCEL_REG_CHIP_ID 0x00
45
46 #define BMC150_ACCEL_REG_INT_STATUS_2 0x0B
47 #define BMC150_ACCEL_ANY_MOTION_MASK 0x07
48 #define BMC150_ACCEL_ANY_MOTION_BIT_X BIT(0)
49 #define BMC150_ACCEL_ANY_MOTION_BIT_Y BIT(1)
50 #define BMC150_ACCEL_ANY_MOTION_BIT_Z BIT(2)
51 #define BMC150_ACCEL_ANY_MOTION_BIT_SIGN BIT(3)
52
53 #define BMC150_ACCEL_REG_PMU_LPW 0x11
54 #define BMC150_ACCEL_PMU_MODE_MASK 0xE0
55 #define BMC150_ACCEL_PMU_MODE_SHIFT 5
56 #define BMC150_ACCEL_PMU_BIT_SLEEP_DUR_MASK 0x17
57 #define BMC150_ACCEL_PMU_BIT_SLEEP_DUR_SHIFT 1
58
59 #define BMC150_ACCEL_REG_PMU_RANGE 0x0F
60
61 #define BMC150_ACCEL_DEF_RANGE_2G 0x03
62 #define BMC150_ACCEL_DEF_RANGE_4G 0x05
63 #define BMC150_ACCEL_DEF_RANGE_8G 0x08
64 #define BMC150_ACCEL_DEF_RANGE_16G 0x0C
65
66 /* Default BW: 125Hz */
67 #define BMC150_ACCEL_REG_PMU_BW 0x10
68 #define BMC150_ACCEL_DEF_BW 125
69
70 #define BMC150_ACCEL_REG_RESET 0x14
71 #define BMC150_ACCEL_RESET_VAL 0xB6
72
73 #define BMC150_ACCEL_REG_INT_MAP_0 0x19
74 #define BMC150_ACCEL_INT_MAP_0_BIT_SLOPE BIT(2)
75
76 #define BMC150_ACCEL_REG_INT_MAP_1 0x1A
77 #define BMC150_ACCEL_INT_MAP_1_BIT_DATA BIT(0)
78 #define BMC150_ACCEL_INT_MAP_1_BIT_FWM BIT(1)
79 #define BMC150_ACCEL_INT_MAP_1_BIT_FFULL BIT(2)
80
81 #define BMC150_ACCEL_REG_INT_RST_LATCH 0x21
82 #define BMC150_ACCEL_INT_MODE_LATCH_RESET 0x80
83 #define BMC150_ACCEL_INT_MODE_LATCH_INT 0x0F
84 #define BMC150_ACCEL_INT_MODE_NON_LATCH_INT 0x00
85
86 #define BMC150_ACCEL_REG_INT_EN_0 0x16
87 #define BMC150_ACCEL_INT_EN_BIT_SLP_X BIT(0)
88 #define BMC150_ACCEL_INT_EN_BIT_SLP_Y BIT(1)
89 #define BMC150_ACCEL_INT_EN_BIT_SLP_Z BIT(2)
90
91 #define BMC150_ACCEL_REG_INT_EN_1 0x17
92 #define BMC150_ACCEL_INT_EN_BIT_DATA_EN BIT(4)
93 #define BMC150_ACCEL_INT_EN_BIT_FFULL_EN BIT(5)
94 #define BMC150_ACCEL_INT_EN_BIT_FWM_EN BIT(6)
95
96 #define BMC150_ACCEL_REG_INT_OUT_CTRL 0x20
97 #define BMC150_ACCEL_INT_OUT_CTRL_INT1_LVL BIT(0)
98
99 #define BMC150_ACCEL_REG_INT_5 0x27
100 #define BMC150_ACCEL_SLOPE_DUR_MASK 0x03
101
102 #define BMC150_ACCEL_REG_INT_6 0x28
103 #define BMC150_ACCEL_SLOPE_THRES_MASK 0xFF
104
105 /* Slope duration in terms of number of samples */
106 #define BMC150_ACCEL_DEF_SLOPE_DURATION 1
107 /* in terms of multiples of g's/LSB, based on range */
108 #define BMC150_ACCEL_DEF_SLOPE_THRESHOLD 1
109
110 #define BMC150_ACCEL_REG_XOUT_L 0x02
111
112 #define BMC150_ACCEL_MAX_STARTUP_TIME_MS 100
113
114 /* Sleep Duration values */
115 #define BMC150_ACCEL_SLEEP_500_MICRO 0x05
116 #define BMC150_ACCEL_SLEEP_1_MS 0x06
117 #define BMC150_ACCEL_SLEEP_2_MS 0x07
118 #define BMC150_ACCEL_SLEEP_4_MS 0x08
119 #define BMC150_ACCEL_SLEEP_6_MS 0x09
120 #define BMC150_ACCEL_SLEEP_10_MS 0x0A
121 #define BMC150_ACCEL_SLEEP_25_MS 0x0B
122 #define BMC150_ACCEL_SLEEP_50_MS 0x0C
123 #define BMC150_ACCEL_SLEEP_100_MS 0x0D
124 #define BMC150_ACCEL_SLEEP_500_MS 0x0E
125 #define BMC150_ACCEL_SLEEP_1_SEC 0x0F
126
127 #define BMC150_ACCEL_REG_TEMP 0x08
128 #define BMC150_ACCEL_TEMP_CENTER_VAL 24
129
130 #define BMC150_ACCEL_AXIS_TO_REG(axis) (BMC150_ACCEL_REG_XOUT_L + (axis * 2))
131 #define BMC150_AUTO_SUSPEND_DELAY_MS 2000
132
133 #define BMC150_ACCEL_REG_FIFO_STATUS 0x0E
134 #define BMC150_ACCEL_REG_FIFO_CONFIG0 0x30
135 #define BMC150_ACCEL_REG_FIFO_CONFIG1 0x3E
136 #define BMC150_ACCEL_REG_FIFO_DATA 0x3F
137 #define BMC150_ACCEL_FIFO_LENGTH 32
138
139 enum bmc150_accel_axis {
140 AXIS_X,
141 AXIS_Y,
142 AXIS_Z,
143 AXIS_MAX,
144 };
145
146 enum bmc150_power_modes {
147 BMC150_ACCEL_SLEEP_MODE_NORMAL,
148 BMC150_ACCEL_SLEEP_MODE_DEEP_SUSPEND,
149 BMC150_ACCEL_SLEEP_MODE_LPM,
150 BMC150_ACCEL_SLEEP_MODE_SUSPEND = 0x04,
151 };
152
153 struct bmc150_scale_info {
154 int scale;
155 u8 reg_range;
156 };
157
158 struct bmc150_accel_chip_info {
159 const char *name;
160 u8 chip_id;
161 const struct iio_chan_spec *channels;
162 int num_channels;
163 const struct bmc150_scale_info scale_table[4];
164 };
165
166 struct bmc150_accel_interrupt {
167 const struct bmc150_accel_interrupt_info *info;
168 atomic_t users;
169 };
170
171 struct bmc150_accel_trigger {
172 struct bmc150_accel_data *data;
173 struct iio_trigger *indio_trig;
174 int (*setup)(struct bmc150_accel_trigger *t, bool state);
175 int intr;
176 bool enabled;
177 };
178
179 enum bmc150_accel_interrupt_id {
180 BMC150_ACCEL_INT_DATA_READY,
181 BMC150_ACCEL_INT_ANY_MOTION,
182 BMC150_ACCEL_INT_WATERMARK,
183 BMC150_ACCEL_INTERRUPTS,
184 };
185
186 enum bmc150_accel_trigger_id {
187 BMC150_ACCEL_TRIGGER_DATA_READY,
188 BMC150_ACCEL_TRIGGER_ANY_MOTION,
189 BMC150_ACCEL_TRIGGERS,
190 };
191
192 struct bmc150_accel_data {
193 struct regmap *regmap;
194 int irq;
195 struct bmc150_accel_interrupt interrupts[BMC150_ACCEL_INTERRUPTS];
196 struct bmc150_accel_trigger triggers[BMC150_ACCEL_TRIGGERS];
197 struct mutex mutex;
198 u8 fifo_mode, watermark;
199 s16 buffer[8];
200 u8 bw_bits;
201 u32 slope_dur;
202 u32 slope_thres;
203 u32 range;
204 int ev_enable_state;
205 int64_t timestamp, old_timestamp; /* Only used in hw fifo mode. */
206 const struct bmc150_accel_chip_info *chip_info;
207 };
208
209 static const struct {
210 int val;
211 int val2;
212 u8 bw_bits;
213 } bmc150_accel_samp_freq_table[] = { {15, 620000, 0x08},
214 {31, 260000, 0x09},
215 {62, 500000, 0x0A},
216 {125, 0, 0x0B},
217 {250, 0, 0x0C},
218 {500, 0, 0x0D},
219 {1000, 0, 0x0E},
220 {2000, 0, 0x0F} };
221
222 static const struct {
223 int bw_bits;
224 int msec;
225 } bmc150_accel_sample_upd_time[] = { {0x08, 64},
226 {0x09, 32},
227 {0x0A, 16},
228 {0x0B, 8},
229 {0x0C, 4},
230 {0x0D, 2},
231 {0x0E, 1},
232 {0x0F, 1} };
233
234 static const struct {
235 int sleep_dur;
236 u8 reg_value;
237 } bmc150_accel_sleep_value_table[] = { {0, 0},
238 {500, BMC150_ACCEL_SLEEP_500_MICRO},
239 {1000, BMC150_ACCEL_SLEEP_1_MS},
240 {2000, BMC150_ACCEL_SLEEP_2_MS},
241 {4000, BMC150_ACCEL_SLEEP_4_MS},
242 {6000, BMC150_ACCEL_SLEEP_6_MS},
243 {10000, BMC150_ACCEL_SLEEP_10_MS},
244 {25000, BMC150_ACCEL_SLEEP_25_MS},
245 {50000, BMC150_ACCEL_SLEEP_50_MS},
246 {100000, BMC150_ACCEL_SLEEP_100_MS},
247 {500000, BMC150_ACCEL_SLEEP_500_MS},
248 {1000000, BMC150_ACCEL_SLEEP_1_SEC} };
249
250 const struct regmap_config bmc150_regmap_conf = {
251 .reg_bits = 8,
252 .val_bits = 8,
253 .max_register = 0x3f,
254 };
255 EXPORT_SYMBOL_GPL(bmc150_regmap_conf);
256
257 static int bmc150_accel_set_mode(struct bmc150_accel_data *data,
258 enum bmc150_power_modes mode,
259 int dur_us)
260 {
261 struct device *dev = regmap_get_device(data->regmap);
262 int i;
263 int ret;
264 u8 lpw_bits;
265 int dur_val = -1;
266
267 if (dur_us > 0) {
268 for (i = 0; i < ARRAY_SIZE(bmc150_accel_sleep_value_table);
269 ++i) {
270 if (bmc150_accel_sleep_value_table[i].sleep_dur ==
271 dur_us)
272 dur_val =
273 bmc150_accel_sleep_value_table[i].reg_value;
274 }
275 } else {
276 dur_val = 0;
277 }
278
279 if (dur_val < 0)
280 return -EINVAL;
281
282 lpw_bits = mode << BMC150_ACCEL_PMU_MODE_SHIFT;
283 lpw_bits |= (dur_val << BMC150_ACCEL_PMU_BIT_SLEEP_DUR_SHIFT);
284
285 dev_dbg(dev, "Set Mode bits %x\n", lpw_bits);
286
287 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_PMU_LPW, lpw_bits);
288 if (ret < 0) {
289 dev_err(dev, "Error writing reg_pmu_lpw\n");
290 return ret;
291 }
292
293 return 0;
294 }
295
296 static int bmc150_accel_set_bw(struct bmc150_accel_data *data, int val,
297 int val2)
298 {
299 int i;
300 int ret;
301
302 for (i = 0; i < ARRAY_SIZE(bmc150_accel_samp_freq_table); ++i) {
303 if (bmc150_accel_samp_freq_table[i].val == val &&
304 bmc150_accel_samp_freq_table[i].val2 == val2) {
305 ret = regmap_write(data->regmap,
306 BMC150_ACCEL_REG_PMU_BW,
307 bmc150_accel_samp_freq_table[i].bw_bits);
308 if (ret < 0)
309 return ret;
310
311 data->bw_bits =
312 bmc150_accel_samp_freq_table[i].bw_bits;
313 return 0;
314 }
315 }
316
317 return -EINVAL;
318 }
319
320 static int bmc150_accel_update_slope(struct bmc150_accel_data *data)
321 {
322 struct device *dev = regmap_get_device(data->regmap);
323 int ret;
324
325 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_6,
326 data->slope_thres);
327 if (ret < 0) {
328 dev_err(dev, "Error writing reg_int_6\n");
329 return ret;
330 }
331
332 ret = regmap_update_bits(data->regmap, BMC150_ACCEL_REG_INT_5,
333 BMC150_ACCEL_SLOPE_DUR_MASK, data->slope_dur);
334 if (ret < 0) {
335 dev_err(dev, "Error updating reg_int_5\n");
336 return ret;
337 }
338
339 dev_dbg(dev, "%x %x\n", data->slope_thres, data->slope_dur);
340
341 return ret;
342 }
343
344 static int bmc150_accel_any_motion_setup(struct bmc150_accel_trigger *t,
345 bool state)
346 {
347 if (state)
348 return bmc150_accel_update_slope(t->data);
349
350 return 0;
351 }
352
353 static int bmc150_accel_get_bw(struct bmc150_accel_data *data, int *val,
354 int *val2)
355 {
356 int i;
357
358 for (i = 0; i < ARRAY_SIZE(bmc150_accel_samp_freq_table); ++i) {
359 if (bmc150_accel_samp_freq_table[i].bw_bits == data->bw_bits) {
360 *val = bmc150_accel_samp_freq_table[i].val;
361 *val2 = bmc150_accel_samp_freq_table[i].val2;
362 return IIO_VAL_INT_PLUS_MICRO;
363 }
364 }
365
366 return -EINVAL;
367 }
368
369 #ifdef CONFIG_PM
370 static int bmc150_accel_get_startup_times(struct bmc150_accel_data *data)
371 {
372 int i;
373
374 for (i = 0; i < ARRAY_SIZE(bmc150_accel_sample_upd_time); ++i) {
375 if (bmc150_accel_sample_upd_time[i].bw_bits == data->bw_bits)
376 return bmc150_accel_sample_upd_time[i].msec;
377 }
378
379 return BMC150_ACCEL_MAX_STARTUP_TIME_MS;
380 }
381
382 static int bmc150_accel_set_power_state(struct bmc150_accel_data *data, bool on)
383 {
384 struct device *dev = regmap_get_device(data->regmap);
385 int ret;
386
387 if (on) {
388 ret = pm_runtime_get_sync(dev);
389 } else {
390 pm_runtime_mark_last_busy(dev);
391 ret = pm_runtime_put_autosuspend(dev);
392 }
393
394 if (ret < 0) {
395 dev_err(dev,
396 "Failed: bmc150_accel_set_power_state for %d\n", on);
397 if (on)
398 pm_runtime_put_noidle(dev);
399
400 return ret;
401 }
402
403 return 0;
404 }
405 #else
406 static int bmc150_accel_set_power_state(struct bmc150_accel_data *data, bool on)
407 {
408 return 0;
409 }
410 #endif
411
412 static const struct bmc150_accel_interrupt_info {
413 u8 map_reg;
414 u8 map_bitmask;
415 u8 en_reg;
416 u8 en_bitmask;
417 } bmc150_accel_interrupts[BMC150_ACCEL_INTERRUPTS] = {
418 { /* data ready interrupt */
419 .map_reg = BMC150_ACCEL_REG_INT_MAP_1,
420 .map_bitmask = BMC150_ACCEL_INT_MAP_1_BIT_DATA,
421 .en_reg = BMC150_ACCEL_REG_INT_EN_1,
422 .en_bitmask = BMC150_ACCEL_INT_EN_BIT_DATA_EN,
423 },
424 { /* motion interrupt */
425 .map_reg = BMC150_ACCEL_REG_INT_MAP_0,
426 .map_bitmask = BMC150_ACCEL_INT_MAP_0_BIT_SLOPE,
427 .en_reg = BMC150_ACCEL_REG_INT_EN_0,
428 .en_bitmask = BMC150_ACCEL_INT_EN_BIT_SLP_X |
429 BMC150_ACCEL_INT_EN_BIT_SLP_Y |
430 BMC150_ACCEL_INT_EN_BIT_SLP_Z
431 },
432 { /* fifo watermark interrupt */
433 .map_reg = BMC150_ACCEL_REG_INT_MAP_1,
434 .map_bitmask = BMC150_ACCEL_INT_MAP_1_BIT_FWM,
435 .en_reg = BMC150_ACCEL_REG_INT_EN_1,
436 .en_bitmask = BMC150_ACCEL_INT_EN_BIT_FWM_EN,
437 },
438 };
439
440 static void bmc150_accel_interrupts_setup(struct iio_dev *indio_dev,
441 struct bmc150_accel_data *data)
442 {
443 int i;
444
445 for (i = 0; i < BMC150_ACCEL_INTERRUPTS; i++)
446 data->interrupts[i].info = &bmc150_accel_interrupts[i];
447 }
448
449 static int bmc150_accel_set_interrupt(struct bmc150_accel_data *data, int i,
450 bool state)
451 {
452 struct device *dev = regmap_get_device(data->regmap);
453 struct bmc150_accel_interrupt *intr = &data->interrupts[i];
454 const struct bmc150_accel_interrupt_info *info = intr->info;
455 int ret;
456
457 if (state) {
458 if (atomic_inc_return(&intr->users) > 1)
459 return 0;
460 } else {
461 if (atomic_dec_return(&intr->users) > 0)
462 return 0;
463 }
464
465 /*
466 * We will expect the enable and disable to do operation in reverse
467 * order. This will happen here anyway, as our resume operation uses
468 * sync mode runtime pm calls. The suspend operation will be delayed
469 * by autosuspend delay.
470 * So the disable operation will still happen in reverse order of
471 * enable operation. When runtime pm is disabled the mode is always on,
472 * so sequence doesn't matter.
473 */
474 ret = bmc150_accel_set_power_state(data, state);
475 if (ret < 0)
476 return ret;
477
478 /* map the interrupt to the appropriate pins */
479 ret = regmap_update_bits(data->regmap, info->map_reg, info->map_bitmask,
480 (state ? info->map_bitmask : 0));
481 if (ret < 0) {
482 dev_err(dev, "Error updating reg_int_map\n");
483 goto out_fix_power_state;
484 }
485
486 /* enable/disable the interrupt */
487 ret = regmap_update_bits(data->regmap, info->en_reg, info->en_bitmask,
488 (state ? info->en_bitmask : 0));
489 if (ret < 0) {
490 dev_err(dev, "Error updating reg_int_en\n");
491 goto out_fix_power_state;
492 }
493
494 return 0;
495
496 out_fix_power_state:
497 bmc150_accel_set_power_state(data, false);
498 return ret;
499 }
500
501 static int bmc150_accel_set_scale(struct bmc150_accel_data *data, int val)
502 {
503 struct device *dev = regmap_get_device(data->regmap);
504 int ret, i;
505
506 for (i = 0; i < ARRAY_SIZE(data->chip_info->scale_table); ++i) {
507 if (data->chip_info->scale_table[i].scale == val) {
508 ret = regmap_write(data->regmap,
509 BMC150_ACCEL_REG_PMU_RANGE,
510 data->chip_info->scale_table[i].reg_range);
511 if (ret < 0) {
512 dev_err(dev, "Error writing pmu_range\n");
513 return ret;
514 }
515
516 data->range = data->chip_info->scale_table[i].reg_range;
517 return 0;
518 }
519 }
520
521 return -EINVAL;
522 }
523
524 static int bmc150_accel_get_temp(struct bmc150_accel_data *data, int *val)
525 {
526 struct device *dev = regmap_get_device(data->regmap);
527 int ret;
528 unsigned int value;
529
530 mutex_lock(&data->mutex);
531
532 ret = regmap_read(data->regmap, BMC150_ACCEL_REG_TEMP, &value);
533 if (ret < 0) {
534 dev_err(dev, "Error reading reg_temp\n");
535 mutex_unlock(&data->mutex);
536 return ret;
537 }
538 *val = sign_extend32(value, 7);
539
540 mutex_unlock(&data->mutex);
541
542 return IIO_VAL_INT;
543 }
544
545 static int bmc150_accel_get_axis(struct bmc150_accel_data *data,
546 struct iio_chan_spec const *chan,
547 int *val)
548 {
549 struct device *dev = regmap_get_device(data->regmap);
550 int ret;
551 int axis = chan->scan_index;
552 __le16 raw_val;
553
554 mutex_lock(&data->mutex);
555 ret = bmc150_accel_set_power_state(data, true);
556 if (ret < 0) {
557 mutex_unlock(&data->mutex);
558 return ret;
559 }
560
561 ret = regmap_bulk_read(data->regmap, BMC150_ACCEL_AXIS_TO_REG(axis),
562 &raw_val, sizeof(raw_val));
563 if (ret < 0) {
564 dev_err(dev, "Error reading axis %d\n", axis);
565 bmc150_accel_set_power_state(data, false);
566 mutex_unlock(&data->mutex);
567 return ret;
568 }
569 *val = sign_extend32(le16_to_cpu(raw_val) >> chan->scan_type.shift,
570 chan->scan_type.realbits - 1);
571 ret = bmc150_accel_set_power_state(data, false);
572 mutex_unlock(&data->mutex);
573 if (ret < 0)
574 return ret;
575
576 return IIO_VAL_INT;
577 }
578
579 static int bmc150_accel_read_raw(struct iio_dev *indio_dev,
580 struct iio_chan_spec const *chan,
581 int *val, int *val2, long mask)
582 {
583 struct bmc150_accel_data *data = iio_priv(indio_dev);
584 int ret;
585
586 switch (mask) {
587 case IIO_CHAN_INFO_RAW:
588 switch (chan->type) {
589 case IIO_TEMP:
590 return bmc150_accel_get_temp(data, val);
591 case IIO_ACCEL:
592 if (iio_buffer_enabled(indio_dev))
593 return -EBUSY;
594 else
595 return bmc150_accel_get_axis(data, chan, val);
596 default:
597 return -EINVAL;
598 }
599 case IIO_CHAN_INFO_OFFSET:
600 if (chan->type == IIO_TEMP) {
601 *val = BMC150_ACCEL_TEMP_CENTER_VAL;
602 return IIO_VAL_INT;
603 } else {
604 return -EINVAL;
605 }
606 case IIO_CHAN_INFO_SCALE:
607 *val = 0;
608 switch (chan->type) {
609 case IIO_TEMP:
610 *val2 = 500000;
611 return IIO_VAL_INT_PLUS_MICRO;
612 case IIO_ACCEL:
613 {
614 int i;
615 const struct bmc150_scale_info *si;
616 int st_size = ARRAY_SIZE(data->chip_info->scale_table);
617
618 for (i = 0; i < st_size; ++i) {
619 si = &data->chip_info->scale_table[i];
620 if (si->reg_range == data->range) {
621 *val2 = si->scale;
622 return IIO_VAL_INT_PLUS_MICRO;
623 }
624 }
625 return -EINVAL;
626 }
627 default:
628 return -EINVAL;
629 }
630 case IIO_CHAN_INFO_SAMP_FREQ:
631 mutex_lock(&data->mutex);
632 ret = bmc150_accel_get_bw(data, val, val2);
633 mutex_unlock(&data->mutex);
634 return ret;
635 default:
636 return -EINVAL;
637 }
638 }
639
640 static int bmc150_accel_write_raw(struct iio_dev *indio_dev,
641 struct iio_chan_spec const *chan,
642 int val, int val2, long mask)
643 {
644 struct bmc150_accel_data *data = iio_priv(indio_dev);
645 int ret;
646
647 switch (mask) {
648 case IIO_CHAN_INFO_SAMP_FREQ:
649 mutex_lock(&data->mutex);
650 ret = bmc150_accel_set_bw(data, val, val2);
651 mutex_unlock(&data->mutex);
652 break;
653 case IIO_CHAN_INFO_SCALE:
654 if (val)
655 return -EINVAL;
656
657 mutex_lock(&data->mutex);
658 ret = bmc150_accel_set_scale(data, val2);
659 mutex_unlock(&data->mutex);
660 return ret;
661 default:
662 ret = -EINVAL;
663 }
664
665 return ret;
666 }
667
668 static int bmc150_accel_read_event(struct iio_dev *indio_dev,
669 const struct iio_chan_spec *chan,
670 enum iio_event_type type,
671 enum iio_event_direction dir,
672 enum iio_event_info info,
673 int *val, int *val2)
674 {
675 struct bmc150_accel_data *data = iio_priv(indio_dev);
676
677 *val2 = 0;
678 switch (info) {
679 case IIO_EV_INFO_VALUE:
680 *val = data->slope_thres;
681 break;
682 case IIO_EV_INFO_PERIOD:
683 *val = data->slope_dur;
684 break;
685 default:
686 return -EINVAL;
687 }
688
689 return IIO_VAL_INT;
690 }
691
692 static int bmc150_accel_write_event(struct iio_dev *indio_dev,
693 const struct iio_chan_spec *chan,
694 enum iio_event_type type,
695 enum iio_event_direction dir,
696 enum iio_event_info info,
697 int val, int val2)
698 {
699 struct bmc150_accel_data *data = iio_priv(indio_dev);
700
701 if (data->ev_enable_state)
702 return -EBUSY;
703
704 switch (info) {
705 case IIO_EV_INFO_VALUE:
706 data->slope_thres = val & BMC150_ACCEL_SLOPE_THRES_MASK;
707 break;
708 case IIO_EV_INFO_PERIOD:
709 data->slope_dur = val & BMC150_ACCEL_SLOPE_DUR_MASK;
710 break;
711 default:
712 return -EINVAL;
713 }
714
715 return 0;
716 }
717
718 static int bmc150_accel_read_event_config(struct iio_dev *indio_dev,
719 const struct iio_chan_spec *chan,
720 enum iio_event_type type,
721 enum iio_event_direction dir)
722 {
723 struct bmc150_accel_data *data = iio_priv(indio_dev);
724
725 return data->ev_enable_state;
726 }
727
728 static int bmc150_accel_write_event_config(struct iio_dev *indio_dev,
729 const struct iio_chan_spec *chan,
730 enum iio_event_type type,
731 enum iio_event_direction dir,
732 int state)
733 {
734 struct bmc150_accel_data *data = iio_priv(indio_dev);
735 int ret;
736
737 if (state == data->ev_enable_state)
738 return 0;
739
740 mutex_lock(&data->mutex);
741
742 ret = bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_ANY_MOTION,
743 state);
744 if (ret < 0) {
745 mutex_unlock(&data->mutex);
746 return ret;
747 }
748
749 data->ev_enable_state = state;
750 mutex_unlock(&data->mutex);
751
752 return 0;
753 }
754
755 static int bmc150_accel_validate_trigger(struct iio_dev *indio_dev,
756 struct iio_trigger *trig)
757 {
758 struct bmc150_accel_data *data = iio_priv(indio_dev);
759 int i;
760
761 for (i = 0; i < BMC150_ACCEL_TRIGGERS; i++) {
762 if (data->triggers[i].indio_trig == trig)
763 return 0;
764 }
765
766 return -EINVAL;
767 }
768
769 static ssize_t bmc150_accel_get_fifo_watermark(struct device *dev,
770 struct device_attribute *attr,
771 char *buf)
772 {
773 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
774 struct bmc150_accel_data *data = iio_priv(indio_dev);
775 int wm;
776
777 mutex_lock(&data->mutex);
778 wm = data->watermark;
779 mutex_unlock(&data->mutex);
780
781 return sprintf(buf, "%d\n", wm);
782 }
783
784 static ssize_t bmc150_accel_get_fifo_state(struct device *dev,
785 struct device_attribute *attr,
786 char *buf)
787 {
788 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
789 struct bmc150_accel_data *data = iio_priv(indio_dev);
790 bool state;
791
792 mutex_lock(&data->mutex);
793 state = data->fifo_mode;
794 mutex_unlock(&data->mutex);
795
796 return sprintf(buf, "%d\n", state);
797 }
798
799 static IIO_CONST_ATTR(hwfifo_watermark_min, "1");
800 static IIO_CONST_ATTR(hwfifo_watermark_max,
801 __stringify(BMC150_ACCEL_FIFO_LENGTH));
802 static IIO_DEVICE_ATTR(hwfifo_enabled, S_IRUGO,
803 bmc150_accel_get_fifo_state, NULL, 0);
804 static IIO_DEVICE_ATTR(hwfifo_watermark, S_IRUGO,
805 bmc150_accel_get_fifo_watermark, NULL, 0);
806
807 static const struct attribute *bmc150_accel_fifo_attributes[] = {
808 &iio_const_attr_hwfifo_watermark_min.dev_attr.attr,
809 &iio_const_attr_hwfifo_watermark_max.dev_attr.attr,
810 &iio_dev_attr_hwfifo_watermark.dev_attr.attr,
811 &iio_dev_attr_hwfifo_enabled.dev_attr.attr,
812 NULL,
813 };
814
815 static int bmc150_accel_set_watermark(struct iio_dev *indio_dev, unsigned val)
816 {
817 struct bmc150_accel_data *data = iio_priv(indio_dev);
818
819 if (val > BMC150_ACCEL_FIFO_LENGTH)
820 val = BMC150_ACCEL_FIFO_LENGTH;
821
822 mutex_lock(&data->mutex);
823 data->watermark = val;
824 mutex_unlock(&data->mutex);
825
826 return 0;
827 }
828
829 /*
830 * We must read at least one full frame in one burst, otherwise the rest of the
831 * frame data is discarded.
832 */
833 static int bmc150_accel_fifo_transfer(struct bmc150_accel_data *data,
834 char *buffer, int samples)
835 {
836 struct device *dev = regmap_get_device(data->regmap);
837 int sample_length = 3 * 2;
838 int ret;
839 int total_length = samples * sample_length;
840
841 ret = regmap_raw_read(data->regmap, BMC150_ACCEL_REG_FIFO_DATA,
842 buffer, total_length);
843 if (ret)
844 dev_err(dev,
845 "Error transferring data from fifo: %d\n", ret);
846
847 return ret;
848 }
849
850 static int __bmc150_accel_fifo_flush(struct iio_dev *indio_dev,
851 unsigned samples, bool irq)
852 {
853 struct bmc150_accel_data *data = iio_priv(indio_dev);
854 struct device *dev = regmap_get_device(data->regmap);
855 int ret, i;
856 u8 count;
857 u16 buffer[BMC150_ACCEL_FIFO_LENGTH * 3];
858 int64_t tstamp;
859 uint64_t sample_period;
860 unsigned int val;
861
862 ret = regmap_read(data->regmap, BMC150_ACCEL_REG_FIFO_STATUS, &val);
863 if (ret < 0) {
864 dev_err(dev, "Error reading reg_fifo_status\n");
865 return ret;
866 }
867
868 count = val & 0x7F;
869
870 if (!count)
871 return 0;
872
873 /*
874 * If we getting called from IRQ handler we know the stored timestamp is
875 * fairly accurate for the last stored sample. Otherwise, if we are
876 * called as a result of a read operation from userspace and hence
877 * before the watermark interrupt was triggered, take a timestamp
878 * now. We can fall anywhere in between two samples so the error in this
879 * case is at most one sample period.
880 */
881 if (!irq) {
882 data->old_timestamp = data->timestamp;
883 data->timestamp = iio_get_time_ns(indio_dev);
884 }
885
886 /*
887 * Approximate timestamps for each of the sample based on the sampling
888 * frequency, timestamp for last sample and number of samples.
889 *
890 * Note that we can't use the current bandwidth settings to compute the
891 * sample period because the sample rate varies with the device
892 * (e.g. between 31.70ms to 32.20ms for a bandwidth of 15.63HZ). That
893 * small variation adds when we store a large number of samples and
894 * creates significant jitter between the last and first samples in
895 * different batches (e.g. 32ms vs 21ms).
896 *
897 * To avoid this issue we compute the actual sample period ourselves
898 * based on the timestamp delta between the last two flush operations.
899 */
900 sample_period = (data->timestamp - data->old_timestamp);
901 do_div(sample_period, count);
902 tstamp = data->timestamp - (count - 1) * sample_period;
903
904 if (samples && count > samples)
905 count = samples;
906
907 ret = bmc150_accel_fifo_transfer(data, (u8 *)buffer, count);
908 if (ret)
909 return ret;
910
911 /*
912 * Ideally we want the IIO core to handle the demux when running in fifo
913 * mode but not when running in triggered buffer mode. Unfortunately
914 * this does not seem to be possible, so stick with driver demux for
915 * now.
916 */
917 for (i = 0; i < count; i++) {
918 u16 sample[8];
919 int j, bit;
920
921 j = 0;
922 for_each_set_bit(bit, indio_dev->active_scan_mask,
923 indio_dev->masklength)
924 memcpy(&sample[j++], &buffer[i * 3 + bit], 2);
925
926 iio_push_to_buffers_with_timestamp(indio_dev, sample, tstamp);
927
928 tstamp += sample_period;
929 }
930
931 return count;
932 }
933
934 static int bmc150_accel_fifo_flush(struct iio_dev *indio_dev, unsigned samples)
935 {
936 struct bmc150_accel_data *data = iio_priv(indio_dev);
937 int ret;
938
939 mutex_lock(&data->mutex);
940 ret = __bmc150_accel_fifo_flush(indio_dev, samples, false);
941 mutex_unlock(&data->mutex);
942
943 return ret;
944 }
945
946 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL(
947 "15.620000 31.260000 62.50000 125 250 500 1000 2000");
948
949 static struct attribute *bmc150_accel_attributes[] = {
950 &iio_const_attr_sampling_frequency_available.dev_attr.attr,
951 NULL,
952 };
953
954 static const struct attribute_group bmc150_accel_attrs_group = {
955 .attrs = bmc150_accel_attributes,
956 };
957
958 static const struct iio_event_spec bmc150_accel_event = {
959 .type = IIO_EV_TYPE_ROC,
960 .dir = IIO_EV_DIR_EITHER,
961 .mask_separate = BIT(IIO_EV_INFO_VALUE) |
962 BIT(IIO_EV_INFO_ENABLE) |
963 BIT(IIO_EV_INFO_PERIOD)
964 };
965
966 #define BMC150_ACCEL_CHANNEL(_axis, bits) { \
967 .type = IIO_ACCEL, \
968 .modified = 1, \
969 .channel2 = IIO_MOD_##_axis, \
970 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
971 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
972 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
973 .scan_index = AXIS_##_axis, \
974 .scan_type = { \
975 .sign = 's', \
976 .realbits = (bits), \
977 .storagebits = 16, \
978 .shift = 16 - (bits), \
979 .endianness = IIO_LE, \
980 }, \
981 .event_spec = &bmc150_accel_event, \
982 .num_event_specs = 1 \
983 }
984
985 #define BMC150_ACCEL_CHANNELS(bits) { \
986 { \
987 .type = IIO_TEMP, \
988 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
989 BIT(IIO_CHAN_INFO_SCALE) | \
990 BIT(IIO_CHAN_INFO_OFFSET), \
991 .scan_index = -1, \
992 }, \
993 BMC150_ACCEL_CHANNEL(X, bits), \
994 BMC150_ACCEL_CHANNEL(Y, bits), \
995 BMC150_ACCEL_CHANNEL(Z, bits), \
996 IIO_CHAN_SOFT_TIMESTAMP(3), \
997 }
998
999 static const struct iio_chan_spec bma222e_accel_channels[] =
1000 BMC150_ACCEL_CHANNELS(8);
1001 static const struct iio_chan_spec bma250e_accel_channels[] =
1002 BMC150_ACCEL_CHANNELS(10);
1003 static const struct iio_chan_spec bmc150_accel_channels[] =
1004 BMC150_ACCEL_CHANNELS(12);
1005 static const struct iio_chan_spec bma280_accel_channels[] =
1006 BMC150_ACCEL_CHANNELS(14);
1007
1008 static const struct bmc150_accel_chip_info bmc150_accel_chip_info_tbl[] = {
1009 [bmc150] = {
1010 .name = "BMC150A",
1011 .chip_id = 0xFA,
1012 .channels = bmc150_accel_channels,
1013 .num_channels = ARRAY_SIZE(bmc150_accel_channels),
1014 .scale_table = { {9610, BMC150_ACCEL_DEF_RANGE_2G},
1015 {19122, BMC150_ACCEL_DEF_RANGE_4G},
1016 {38344, BMC150_ACCEL_DEF_RANGE_8G},
1017 {76590, BMC150_ACCEL_DEF_RANGE_16G} },
1018 },
1019 [bmi055] = {
1020 .name = "BMI055A",
1021 .chip_id = 0xFA,
1022 .channels = bmc150_accel_channels,
1023 .num_channels = ARRAY_SIZE(bmc150_accel_channels),
1024 .scale_table = { {9610, BMC150_ACCEL_DEF_RANGE_2G},
1025 {19122, BMC150_ACCEL_DEF_RANGE_4G},
1026 {38344, BMC150_ACCEL_DEF_RANGE_8G},
1027 {76590, BMC150_ACCEL_DEF_RANGE_16G} },
1028 },
1029 [bma255] = {
1030 .name = "BMA0255",
1031 .chip_id = 0xFA,
1032 .channels = bmc150_accel_channels,
1033 .num_channels = ARRAY_SIZE(bmc150_accel_channels),
1034 .scale_table = { {9610, BMC150_ACCEL_DEF_RANGE_2G},
1035 {19122, BMC150_ACCEL_DEF_RANGE_4G},
1036 {38344, BMC150_ACCEL_DEF_RANGE_8G},
1037 {76590, BMC150_ACCEL_DEF_RANGE_16G} },
1038 },
1039 [bma250e] = {
1040 .name = "BMA250E",
1041 .chip_id = 0xF9,
1042 .channels = bma250e_accel_channels,
1043 .num_channels = ARRAY_SIZE(bma250e_accel_channels),
1044 .scale_table = { {38344, BMC150_ACCEL_DEF_RANGE_2G},
1045 {76590, BMC150_ACCEL_DEF_RANGE_4G},
1046 {153277, BMC150_ACCEL_DEF_RANGE_8G},
1047 {306457, BMC150_ACCEL_DEF_RANGE_16G} },
1048 },
1049 [bma222e] = {
1050 .name = "BMA222E",
1051 .chip_id = 0xF8,
1052 .channels = bma222e_accel_channels,
1053 .num_channels = ARRAY_SIZE(bma222e_accel_channels),
1054 .scale_table = { {153277, BMC150_ACCEL_DEF_RANGE_2G},
1055 {306457, BMC150_ACCEL_DEF_RANGE_4G},
1056 {612915, BMC150_ACCEL_DEF_RANGE_8G},
1057 {1225831, BMC150_ACCEL_DEF_RANGE_16G} },
1058 },
1059 [bma280] = {
1060 .name = "BMA0280",
1061 .chip_id = 0xFB,
1062 .channels = bma280_accel_channels,
1063 .num_channels = ARRAY_SIZE(bma280_accel_channels),
1064 .scale_table = { {2392, BMC150_ACCEL_DEF_RANGE_2G},
1065 {4785, BMC150_ACCEL_DEF_RANGE_4G},
1066 {9581, BMC150_ACCEL_DEF_RANGE_8G},
1067 {19152, BMC150_ACCEL_DEF_RANGE_16G} },
1068 },
1069 };
1070
1071 static const struct iio_info bmc150_accel_info = {
1072 .attrs = &bmc150_accel_attrs_group,
1073 .read_raw = bmc150_accel_read_raw,
1074 .write_raw = bmc150_accel_write_raw,
1075 .read_event_value = bmc150_accel_read_event,
1076 .write_event_value = bmc150_accel_write_event,
1077 .write_event_config = bmc150_accel_write_event_config,
1078 .read_event_config = bmc150_accel_read_event_config,
1079 };
1080
1081 static const struct iio_info bmc150_accel_info_fifo = {
1082 .attrs = &bmc150_accel_attrs_group,
1083 .read_raw = bmc150_accel_read_raw,
1084 .write_raw = bmc150_accel_write_raw,
1085 .read_event_value = bmc150_accel_read_event,
1086 .write_event_value = bmc150_accel_write_event,
1087 .write_event_config = bmc150_accel_write_event_config,
1088 .read_event_config = bmc150_accel_read_event_config,
1089 .validate_trigger = bmc150_accel_validate_trigger,
1090 .hwfifo_set_watermark = bmc150_accel_set_watermark,
1091 .hwfifo_flush_to_buffer = bmc150_accel_fifo_flush,
1092 };
1093
1094 static const unsigned long bmc150_accel_scan_masks[] = {
1095 BIT(AXIS_X) | BIT(AXIS_Y) | BIT(AXIS_Z),
1096 0};
1097
1098 static irqreturn_t bmc150_accel_trigger_handler(int irq, void *p)
1099 {
1100 struct iio_poll_func *pf = p;
1101 struct iio_dev *indio_dev = pf->indio_dev;
1102 struct bmc150_accel_data *data = iio_priv(indio_dev);
1103 int ret;
1104
1105 mutex_lock(&data->mutex);
1106 ret = regmap_bulk_read(data->regmap, BMC150_ACCEL_REG_XOUT_L,
1107 data->buffer, AXIS_MAX * 2);
1108 mutex_unlock(&data->mutex);
1109 if (ret < 0)
1110 goto err_read;
1111
1112 iio_push_to_buffers_with_timestamp(indio_dev, data->buffer,
1113 pf->timestamp);
1114 err_read:
1115 iio_trigger_notify_done(indio_dev->trig);
1116
1117 return IRQ_HANDLED;
1118 }
1119
1120 static int bmc150_accel_trig_try_reen(struct iio_trigger *trig)
1121 {
1122 struct bmc150_accel_trigger *t = iio_trigger_get_drvdata(trig);
1123 struct bmc150_accel_data *data = t->data;
1124 struct device *dev = regmap_get_device(data->regmap);
1125 int ret;
1126
1127 /* new data interrupts don't need ack */
1128 if (t == &t->data->triggers[BMC150_ACCEL_TRIGGER_DATA_READY])
1129 return 0;
1130
1131 mutex_lock(&data->mutex);
1132 /* clear any latched interrupt */
1133 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH,
1134 BMC150_ACCEL_INT_MODE_LATCH_INT |
1135 BMC150_ACCEL_INT_MODE_LATCH_RESET);
1136 mutex_unlock(&data->mutex);
1137 if (ret < 0) {
1138 dev_err(dev, "Error writing reg_int_rst_latch\n");
1139 return ret;
1140 }
1141
1142 return 0;
1143 }
1144
1145 static int bmc150_accel_trigger_set_state(struct iio_trigger *trig,
1146 bool state)
1147 {
1148 struct bmc150_accel_trigger *t = iio_trigger_get_drvdata(trig);
1149 struct bmc150_accel_data *data = t->data;
1150 int ret;
1151
1152 mutex_lock(&data->mutex);
1153
1154 if (t->enabled == state) {
1155 mutex_unlock(&data->mutex);
1156 return 0;
1157 }
1158
1159 if (t->setup) {
1160 ret = t->setup(t, state);
1161 if (ret < 0) {
1162 mutex_unlock(&data->mutex);
1163 return ret;
1164 }
1165 }
1166
1167 ret = bmc150_accel_set_interrupt(data, t->intr, state);
1168 if (ret < 0) {
1169 mutex_unlock(&data->mutex);
1170 return ret;
1171 }
1172
1173 t->enabled = state;
1174
1175 mutex_unlock(&data->mutex);
1176
1177 return ret;
1178 }
1179
1180 static const struct iio_trigger_ops bmc150_accel_trigger_ops = {
1181 .set_trigger_state = bmc150_accel_trigger_set_state,
1182 .try_reenable = bmc150_accel_trig_try_reen,
1183 };
1184
1185 static int bmc150_accel_handle_roc_event(struct iio_dev *indio_dev)
1186 {
1187 struct bmc150_accel_data *data = iio_priv(indio_dev);
1188 struct device *dev = regmap_get_device(data->regmap);
1189 int dir;
1190 int ret;
1191 unsigned int val;
1192
1193 ret = regmap_read(data->regmap, BMC150_ACCEL_REG_INT_STATUS_2, &val);
1194 if (ret < 0) {
1195 dev_err(dev, "Error reading reg_int_status_2\n");
1196 return ret;
1197 }
1198
1199 if (val & BMC150_ACCEL_ANY_MOTION_BIT_SIGN)
1200 dir = IIO_EV_DIR_FALLING;
1201 else
1202 dir = IIO_EV_DIR_RISING;
1203
1204 if (val & BMC150_ACCEL_ANY_MOTION_BIT_X)
1205 iio_push_event(indio_dev,
1206 IIO_MOD_EVENT_CODE(IIO_ACCEL,
1207 0,
1208 IIO_MOD_X,
1209 IIO_EV_TYPE_ROC,
1210 dir),
1211 data->timestamp);
1212
1213 if (val & BMC150_ACCEL_ANY_MOTION_BIT_Y)
1214 iio_push_event(indio_dev,
1215 IIO_MOD_EVENT_CODE(IIO_ACCEL,
1216 0,
1217 IIO_MOD_Y,
1218 IIO_EV_TYPE_ROC,
1219 dir),
1220 data->timestamp);
1221
1222 if (val & BMC150_ACCEL_ANY_MOTION_BIT_Z)
1223 iio_push_event(indio_dev,
1224 IIO_MOD_EVENT_CODE(IIO_ACCEL,
1225 0,
1226 IIO_MOD_Z,
1227 IIO_EV_TYPE_ROC,
1228 dir),
1229 data->timestamp);
1230
1231 return ret;
1232 }
1233
1234 static irqreturn_t bmc150_accel_irq_thread_handler(int irq, void *private)
1235 {
1236 struct iio_dev *indio_dev = private;
1237 struct bmc150_accel_data *data = iio_priv(indio_dev);
1238 struct device *dev = regmap_get_device(data->regmap);
1239 bool ack = false;
1240 int ret;
1241
1242 mutex_lock(&data->mutex);
1243
1244 if (data->fifo_mode) {
1245 ret = __bmc150_accel_fifo_flush(indio_dev,
1246 BMC150_ACCEL_FIFO_LENGTH, true);
1247 if (ret > 0)
1248 ack = true;
1249 }
1250
1251 if (data->ev_enable_state) {
1252 ret = bmc150_accel_handle_roc_event(indio_dev);
1253 if (ret > 0)
1254 ack = true;
1255 }
1256
1257 if (ack) {
1258 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH,
1259 BMC150_ACCEL_INT_MODE_LATCH_INT |
1260 BMC150_ACCEL_INT_MODE_LATCH_RESET);
1261 if (ret)
1262 dev_err(dev, "Error writing reg_int_rst_latch\n");
1263
1264 ret = IRQ_HANDLED;
1265 } else {
1266 ret = IRQ_NONE;
1267 }
1268
1269 mutex_unlock(&data->mutex);
1270
1271 return ret;
1272 }
1273
1274 static irqreturn_t bmc150_accel_irq_handler(int irq, void *private)
1275 {
1276 struct iio_dev *indio_dev = private;
1277 struct bmc150_accel_data *data = iio_priv(indio_dev);
1278 bool ack = false;
1279 int i;
1280
1281 data->old_timestamp = data->timestamp;
1282 data->timestamp = iio_get_time_ns(indio_dev);
1283
1284 for (i = 0; i < BMC150_ACCEL_TRIGGERS; i++) {
1285 if (data->triggers[i].enabled) {
1286 iio_trigger_poll(data->triggers[i].indio_trig);
1287 ack = true;
1288 break;
1289 }
1290 }
1291
1292 if (data->ev_enable_state || data->fifo_mode)
1293 return IRQ_WAKE_THREAD;
1294
1295 if (ack)
1296 return IRQ_HANDLED;
1297
1298 return IRQ_NONE;
1299 }
1300
1301 static const struct {
1302 int intr;
1303 const char *name;
1304 int (*setup)(struct bmc150_accel_trigger *t, bool state);
1305 } bmc150_accel_triggers[BMC150_ACCEL_TRIGGERS] = {
1306 {
1307 .intr = 0,
1308 .name = "%s-dev%d",
1309 },
1310 {
1311 .intr = 1,
1312 .name = "%s-any-motion-dev%d",
1313 .setup = bmc150_accel_any_motion_setup,
1314 },
1315 };
1316
1317 static void bmc150_accel_unregister_triggers(struct bmc150_accel_data *data,
1318 int from)
1319 {
1320 int i;
1321
1322 for (i = from; i >= 0; i--) {
1323 if (data->triggers[i].indio_trig) {
1324 iio_trigger_unregister(data->triggers[i].indio_trig);
1325 data->triggers[i].indio_trig = NULL;
1326 }
1327 }
1328 }
1329
1330 static int bmc150_accel_triggers_setup(struct iio_dev *indio_dev,
1331 struct bmc150_accel_data *data)
1332 {
1333 struct device *dev = regmap_get_device(data->regmap);
1334 int i, ret;
1335
1336 for (i = 0; i < BMC150_ACCEL_TRIGGERS; i++) {
1337 struct bmc150_accel_trigger *t = &data->triggers[i];
1338
1339 t->indio_trig = devm_iio_trigger_alloc(dev,
1340 bmc150_accel_triggers[i].name,
1341 indio_dev->name,
1342 indio_dev->id);
1343 if (!t->indio_trig) {
1344 ret = -ENOMEM;
1345 break;
1346 }
1347
1348 t->indio_trig->dev.parent = dev;
1349 t->indio_trig->ops = &bmc150_accel_trigger_ops;
1350 t->intr = bmc150_accel_triggers[i].intr;
1351 t->data = data;
1352 t->setup = bmc150_accel_triggers[i].setup;
1353 iio_trigger_set_drvdata(t->indio_trig, t);
1354
1355 ret = iio_trigger_register(t->indio_trig);
1356 if (ret)
1357 break;
1358 }
1359
1360 if (ret)
1361 bmc150_accel_unregister_triggers(data, i - 1);
1362
1363 return ret;
1364 }
1365
1366 #define BMC150_ACCEL_FIFO_MODE_STREAM 0x80
1367 #define BMC150_ACCEL_FIFO_MODE_FIFO 0x40
1368 #define BMC150_ACCEL_FIFO_MODE_BYPASS 0x00
1369
1370 static int bmc150_accel_fifo_set_mode(struct bmc150_accel_data *data)
1371 {
1372 struct device *dev = regmap_get_device(data->regmap);
1373 u8 reg = BMC150_ACCEL_REG_FIFO_CONFIG1;
1374 int ret;
1375
1376 ret = regmap_write(data->regmap, reg, data->fifo_mode);
1377 if (ret < 0) {
1378 dev_err(dev, "Error writing reg_fifo_config1\n");
1379 return ret;
1380 }
1381
1382 if (!data->fifo_mode)
1383 return 0;
1384
1385 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_FIFO_CONFIG0,
1386 data->watermark);
1387 if (ret < 0)
1388 dev_err(dev, "Error writing reg_fifo_config0\n");
1389
1390 return ret;
1391 }
1392
1393 static int bmc150_accel_buffer_preenable(struct iio_dev *indio_dev)
1394 {
1395 struct bmc150_accel_data *data = iio_priv(indio_dev);
1396
1397 return bmc150_accel_set_power_state(data, true);
1398 }
1399
1400 static int bmc150_accel_buffer_postenable(struct iio_dev *indio_dev)
1401 {
1402 struct bmc150_accel_data *data = iio_priv(indio_dev);
1403 int ret = 0;
1404
1405 if (indio_dev->currentmode == INDIO_BUFFER_TRIGGERED)
1406 return iio_triggered_buffer_postenable(indio_dev);
1407
1408 mutex_lock(&data->mutex);
1409
1410 if (!data->watermark)
1411 goto out;
1412
1413 ret = bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_WATERMARK,
1414 true);
1415 if (ret)
1416 goto out;
1417
1418 data->fifo_mode = BMC150_ACCEL_FIFO_MODE_FIFO;
1419
1420 ret = bmc150_accel_fifo_set_mode(data);
1421 if (ret) {
1422 data->fifo_mode = 0;
1423 bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_WATERMARK,
1424 false);
1425 }
1426
1427 out:
1428 mutex_unlock(&data->mutex);
1429
1430 return ret;
1431 }
1432
1433 static int bmc150_accel_buffer_predisable(struct iio_dev *indio_dev)
1434 {
1435 struct bmc150_accel_data *data = iio_priv(indio_dev);
1436
1437 if (indio_dev->currentmode == INDIO_BUFFER_TRIGGERED)
1438 return iio_triggered_buffer_predisable(indio_dev);
1439
1440 mutex_lock(&data->mutex);
1441
1442 if (!data->fifo_mode)
1443 goto out;
1444
1445 bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_WATERMARK, false);
1446 __bmc150_accel_fifo_flush(indio_dev, BMC150_ACCEL_FIFO_LENGTH, false);
1447 data->fifo_mode = 0;
1448 bmc150_accel_fifo_set_mode(data);
1449
1450 out:
1451 mutex_unlock(&data->mutex);
1452
1453 return 0;
1454 }
1455
1456 static int bmc150_accel_buffer_postdisable(struct iio_dev *indio_dev)
1457 {
1458 struct bmc150_accel_data *data = iio_priv(indio_dev);
1459
1460 return bmc150_accel_set_power_state(data, false);
1461 }
1462
1463 static const struct iio_buffer_setup_ops bmc150_accel_buffer_ops = {
1464 .preenable = bmc150_accel_buffer_preenable,
1465 .postenable = bmc150_accel_buffer_postenable,
1466 .predisable = bmc150_accel_buffer_predisable,
1467 .postdisable = bmc150_accel_buffer_postdisable,
1468 };
1469
1470 static int bmc150_accel_chip_init(struct bmc150_accel_data *data)
1471 {
1472 struct device *dev = regmap_get_device(data->regmap);
1473 int ret, i;
1474 unsigned int val;
1475
1476 /*
1477 * Reset chip to get it in a known good state. A delay of 1.8ms after
1478 * reset is required according to the data sheets of supported chips.
1479 */
1480 regmap_write(data->regmap, BMC150_ACCEL_REG_RESET,
1481 BMC150_ACCEL_RESET_VAL);
1482 usleep_range(1800, 2500);
1483
1484 ret = regmap_read(data->regmap, BMC150_ACCEL_REG_CHIP_ID, &val);
1485 if (ret < 0) {
1486 dev_err(dev, "Error: Reading chip id\n");
1487 return ret;
1488 }
1489
1490 dev_dbg(dev, "Chip Id %x\n", val);
1491 for (i = 0; i < ARRAY_SIZE(bmc150_accel_chip_info_tbl); i++) {
1492 if (bmc150_accel_chip_info_tbl[i].chip_id == val) {
1493 data->chip_info = &bmc150_accel_chip_info_tbl[i];
1494 break;
1495 }
1496 }
1497
1498 if (!data->chip_info) {
1499 dev_err(dev, "Invalid chip %x\n", val);
1500 return -ENODEV;
1501 }
1502
1503 ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0);
1504 if (ret < 0)
1505 return ret;
1506
1507 /* Set Bandwidth */
1508 ret = bmc150_accel_set_bw(data, BMC150_ACCEL_DEF_BW, 0);
1509 if (ret < 0)
1510 return ret;
1511
1512 /* Set Default Range */
1513 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_PMU_RANGE,
1514 BMC150_ACCEL_DEF_RANGE_4G);
1515 if (ret < 0) {
1516 dev_err(dev, "Error writing reg_pmu_range\n");
1517 return ret;
1518 }
1519
1520 data->range = BMC150_ACCEL_DEF_RANGE_4G;
1521
1522 /* Set default slope duration and thresholds */
1523 data->slope_thres = BMC150_ACCEL_DEF_SLOPE_THRESHOLD;
1524 data->slope_dur = BMC150_ACCEL_DEF_SLOPE_DURATION;
1525 ret = bmc150_accel_update_slope(data);
1526 if (ret < 0)
1527 return ret;
1528
1529 /* Set default as latched interrupts */
1530 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH,
1531 BMC150_ACCEL_INT_MODE_LATCH_INT |
1532 BMC150_ACCEL_INT_MODE_LATCH_RESET);
1533 if (ret < 0) {
1534 dev_err(dev, "Error writing reg_int_rst_latch\n");
1535 return ret;
1536 }
1537
1538 return 0;
1539 }
1540
1541 int bmc150_accel_core_probe(struct device *dev, struct regmap *regmap, int irq,
1542 const char *name, bool block_supported)
1543 {
1544 struct bmc150_accel_data *data;
1545 struct iio_dev *indio_dev;
1546 int ret;
1547
1548 indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
1549 if (!indio_dev)
1550 return -ENOMEM;
1551
1552 data = iio_priv(indio_dev);
1553 dev_set_drvdata(dev, indio_dev);
1554 data->irq = irq;
1555
1556 data->regmap = regmap;
1557
1558 ret = bmc150_accel_chip_init(data);
1559 if (ret < 0)
1560 return ret;
1561
1562 mutex_init(&data->mutex);
1563
1564 indio_dev->dev.parent = dev;
1565 indio_dev->channels = data->chip_info->channels;
1566 indio_dev->num_channels = data->chip_info->num_channels;
1567 indio_dev->name = name ? name : data->chip_info->name;
1568 indio_dev->available_scan_masks = bmc150_accel_scan_masks;
1569 indio_dev->modes = INDIO_DIRECT_MODE;
1570 indio_dev->info = &bmc150_accel_info;
1571
1572 ret = iio_triggered_buffer_setup(indio_dev,
1573 &iio_pollfunc_store_time,
1574 bmc150_accel_trigger_handler,
1575 &bmc150_accel_buffer_ops);
1576 if (ret < 0) {
1577 dev_err(dev, "Failed: iio triggered buffer setup\n");
1578 return ret;
1579 }
1580
1581 if (data->irq > 0) {
1582 ret = devm_request_threaded_irq(
1583 dev, data->irq,
1584 bmc150_accel_irq_handler,
1585 bmc150_accel_irq_thread_handler,
1586 IRQF_TRIGGER_RISING,
1587 BMC150_ACCEL_IRQ_NAME,
1588 indio_dev);
1589 if (ret)
1590 goto err_buffer_cleanup;
1591
1592 /*
1593 * Set latched mode interrupt. While certain interrupts are
1594 * non-latched regardless of this settings (e.g. new data) we
1595 * want to use latch mode when we can to prevent interrupt
1596 * flooding.
1597 */
1598 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH,
1599 BMC150_ACCEL_INT_MODE_LATCH_RESET);
1600 if (ret < 0) {
1601 dev_err(dev, "Error writing reg_int_rst_latch\n");
1602 goto err_buffer_cleanup;
1603 }
1604
1605 bmc150_accel_interrupts_setup(indio_dev, data);
1606
1607 ret = bmc150_accel_triggers_setup(indio_dev, data);
1608 if (ret)
1609 goto err_buffer_cleanup;
1610
1611 if (block_supported) {
1612 indio_dev->modes |= INDIO_BUFFER_SOFTWARE;
1613 indio_dev->info = &bmc150_accel_info_fifo;
1614 iio_buffer_set_attrs(indio_dev->buffer,
1615 bmc150_accel_fifo_attributes);
1616 }
1617 }
1618
1619 ret = pm_runtime_set_active(dev);
1620 if (ret)
1621 goto err_trigger_unregister;
1622
1623 pm_runtime_enable(dev);
1624 pm_runtime_set_autosuspend_delay(dev, BMC150_AUTO_SUSPEND_DELAY_MS);
1625 pm_runtime_use_autosuspend(dev);
1626
1627 ret = iio_device_register(indio_dev);
1628 if (ret < 0) {
1629 dev_err(dev, "Unable to register iio device\n");
1630 goto err_trigger_unregister;
1631 }
1632
1633 return 0;
1634
1635 err_trigger_unregister:
1636 bmc150_accel_unregister_triggers(data, BMC150_ACCEL_TRIGGERS - 1);
1637 err_buffer_cleanup:
1638 iio_triggered_buffer_cleanup(indio_dev);
1639
1640 return ret;
1641 }
1642 EXPORT_SYMBOL_GPL(bmc150_accel_core_probe);
1643
1644 int bmc150_accel_core_remove(struct device *dev)
1645 {
1646 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1647 struct bmc150_accel_data *data = iio_priv(indio_dev);
1648
1649 iio_device_unregister(indio_dev);
1650
1651 pm_runtime_disable(dev);
1652 pm_runtime_set_suspended(dev);
1653 pm_runtime_put_noidle(dev);
1654
1655 bmc150_accel_unregister_triggers(data, BMC150_ACCEL_TRIGGERS - 1);
1656
1657 iio_triggered_buffer_cleanup(indio_dev);
1658
1659 mutex_lock(&data->mutex);
1660 bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_DEEP_SUSPEND, 0);
1661 mutex_unlock(&data->mutex);
1662
1663 return 0;
1664 }
1665 EXPORT_SYMBOL_GPL(bmc150_accel_core_remove);
1666
1667 #ifdef CONFIG_PM_SLEEP
1668 static int bmc150_accel_suspend(struct device *dev)
1669 {
1670 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1671 struct bmc150_accel_data *data = iio_priv(indio_dev);
1672
1673 mutex_lock(&data->mutex);
1674 bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_SUSPEND, 0);
1675 mutex_unlock(&data->mutex);
1676
1677 return 0;
1678 }
1679
1680 static int bmc150_accel_resume(struct device *dev)
1681 {
1682 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1683 struct bmc150_accel_data *data = iio_priv(indio_dev);
1684
1685 mutex_lock(&data->mutex);
1686 bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0);
1687 bmc150_accel_fifo_set_mode(data);
1688 mutex_unlock(&data->mutex);
1689
1690 return 0;
1691 }
1692 #endif
1693
1694 #ifdef CONFIG_PM
1695 static int bmc150_accel_runtime_suspend(struct device *dev)
1696 {
1697 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1698 struct bmc150_accel_data *data = iio_priv(indio_dev);
1699 int ret;
1700
1701 ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_SUSPEND, 0);
1702 if (ret < 0)
1703 return -EAGAIN;
1704
1705 return 0;
1706 }
1707
1708 static int bmc150_accel_runtime_resume(struct device *dev)
1709 {
1710 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1711 struct bmc150_accel_data *data = iio_priv(indio_dev);
1712 int ret;
1713 int sleep_val;
1714
1715 ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0);
1716 if (ret < 0)
1717 return ret;
1718 ret = bmc150_accel_fifo_set_mode(data);
1719 if (ret < 0)
1720 return ret;
1721
1722 sleep_val = bmc150_accel_get_startup_times(data);
1723 if (sleep_val < 20)
1724 usleep_range(sleep_val * 1000, 20000);
1725 else
1726 msleep_interruptible(sleep_val);
1727
1728 return 0;
1729 }
1730 #endif
1731
1732 const struct dev_pm_ops bmc150_accel_pm_ops = {
1733 SET_SYSTEM_SLEEP_PM_OPS(bmc150_accel_suspend, bmc150_accel_resume)
1734 SET_RUNTIME_PM_OPS(bmc150_accel_runtime_suspend,
1735 bmc150_accel_runtime_resume, NULL)
1736 };
1737 EXPORT_SYMBOL_GPL(bmc150_accel_pm_ops);
1738
1739 MODULE_AUTHOR("Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>");
1740 MODULE_LICENSE("GPL v2");
1741 MODULE_DESCRIPTION("BMC150 accelerometer driver");
Linux with added FPC-III support