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dt-bindings: mtd: ingenic: Use standard ecc-engine property
[linux/fpc-iii.git] / drivers / net / dsa / vitesse-vsc73xx.c
blobd4780610ea8a320696d13d3928156eac4915e9ae
1 // SPDX-License-Identifier: GPL-2.0
2 /* DSA driver for:
3 * Vitesse VSC7385 SparX-G5 5+1-port Integrated Gigabit Ethernet Switch
4 * Vitesse VSC7388 SparX-G8 8-port Integrated Gigabit Ethernet Switch
5 * Vitesse VSC7395 SparX-G5e 5+1-port Integrated Gigabit Ethernet Switch
6 * Vitesse VSC7398 SparX-G8e 8-port Integrated Gigabit Ethernet Switch
7 *
8 * These switches have a built-in 8051 CPU and can download and execute a
9 * firmware in this CPU. They can also be configured to use an external CPU
10 * handling the switch in a memory-mapped manner by connecting to that external
11 * CPU's memory bus.
12 *
13 * This driver (currently) only takes control of the switch chip over SPI and
14 * configures it to route packages around when connected to a CPU port. The
15 * chip has embedded PHYs and VLAN support so we model it using DSA.
16 *
17 * Copyright (C) 2018 Linus Wallej <linus.walleij@linaro.org>
18 * Includes portions of code from the firmware uploader by:
19 * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
20 */
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/device.h>
24 #include <linux/of.h>
25 #include <linux/of_device.h>
26 #include <linux/of_mdio.h>
27 #include <linux/platform_device.h>
28 #include <linux/spi/spi.h>
29 #include <linux/bitops.h>
30 #include <linux/if_bridge.h>
31 #include <linux/etherdevice.h>
32 #include <linux/gpio/consumer.h>
33 #include <linux/gpio/driver.h>
34 #include <linux/random.h>
35 #include <net/dsa.h>
36
37 #define VSC73XX_BLOCK_MAC 0x1 /* Subblocks 0-4, 6 (CPU port) */
38 #define VSC73XX_BLOCK_ANALYZER 0x2 /* Only subblock 0 */
39 #define VSC73XX_BLOCK_MII 0x3 /* Subblocks 0 and 1 */
40 #define VSC73XX_BLOCK_MEMINIT 0x3 /* Only subblock 2 */
41 #define VSC73XX_BLOCK_CAPTURE 0x4 /* Only subblock 2 */
42 #define VSC73XX_BLOCK_ARBITER 0x5 /* Only subblock 0 */
43 #define VSC73XX_BLOCK_SYSTEM 0x7 /* Only subblock 0 */
44
45 #define CPU_PORT 6 /* CPU port */
46
47 /* MAC Block registers */
48 #define VSC73XX_MAC_CFG 0x00
49 #define VSC73XX_MACHDXGAP 0x02
50 #define VSC73XX_FCCONF 0x04
51 #define VSC73XX_FCMACHI 0x08
52 #define VSC73XX_FCMACLO 0x0c
53 #define VSC73XX_MAXLEN 0x10
54 #define VSC73XX_ADVPORTM 0x19
55 #define VSC73XX_TXUPDCFG 0x24
56 #define VSC73XX_TXQ_SELECT_CFG 0x28
57 #define VSC73XX_RXOCT 0x50
58 #define VSC73XX_TXOCT 0x51
59 #define VSC73XX_C_RX0 0x52
60 #define VSC73XX_C_RX1 0x53
61 #define VSC73XX_C_RX2 0x54
62 #define VSC73XX_C_TX0 0x55
63 #define VSC73XX_C_TX1 0x56
64 #define VSC73XX_C_TX2 0x57
65 #define VSC73XX_C_CFG 0x58
66 #define VSC73XX_CAT_DROP 0x6e
67 #define VSC73XX_CAT_PR_MISC_L2 0x6f
68 #define VSC73XX_CAT_PR_USR_PRIO 0x75
69 #define VSC73XX_Q_MISC_CONF 0xdf
70
71 /* MAC_CFG register bits */
72 #define VSC73XX_MAC_CFG_WEXC_DIS BIT(31)
73 #define VSC73XX_MAC_CFG_PORT_RST BIT(29)
74 #define VSC73XX_MAC_CFG_TX_EN BIT(28)
75 #define VSC73XX_MAC_CFG_SEED_LOAD BIT(27)
76 #define VSC73XX_MAC_CFG_SEED_MASK GENMASK(26, 19)
77 #define VSC73XX_MAC_CFG_SEED_OFFSET 19
78 #define VSC73XX_MAC_CFG_FDX BIT(18)
79 #define VSC73XX_MAC_CFG_GIGA_MODE BIT(17)
80 #define VSC73XX_MAC_CFG_RX_EN BIT(16)
81 #define VSC73XX_MAC_CFG_VLAN_DBLAWR BIT(15)
82 #define VSC73XX_MAC_CFG_VLAN_AWR BIT(14)
83 #define VSC73XX_MAC_CFG_100_BASE_T BIT(13) /* Not in manual */
84 #define VSC73XX_MAC_CFG_TX_IPG_MASK GENMASK(10, 6)
85 #define VSC73XX_MAC_CFG_TX_IPG_OFFSET 6
86 #define VSC73XX_MAC_CFG_TX_IPG_1000M (6 << VSC73XX_MAC_CFG_TX_IPG_OFFSET)
87 #define VSC73XX_MAC_CFG_TX_IPG_100_10M (17 << VSC73XX_MAC_CFG_TX_IPG_OFFSET)
88 #define VSC73XX_MAC_CFG_MAC_RX_RST BIT(5)
89 #define VSC73XX_MAC_CFG_MAC_TX_RST BIT(4)
90 #define VSC73XX_MAC_CFG_CLK_SEL_MASK GENMASK(2, 0)
91 #define VSC73XX_MAC_CFG_CLK_SEL_OFFSET 0
92 #define VSC73XX_MAC_CFG_CLK_SEL_1000M 1
93 #define VSC73XX_MAC_CFG_CLK_SEL_100M 2
94 #define VSC73XX_MAC_CFG_CLK_SEL_10M 3
95 #define VSC73XX_MAC_CFG_CLK_SEL_EXT 4
96
97 #define VSC73XX_MAC_CFG_1000M_F_PHY (VSC73XX_MAC_CFG_FDX | \
98 VSC73XX_MAC_CFG_GIGA_MODE | \
99 VSC73XX_MAC_CFG_TX_IPG_1000M | \
100 VSC73XX_MAC_CFG_CLK_SEL_EXT)
101 #define VSC73XX_MAC_CFG_100_10M_F_PHY (VSC73XX_MAC_CFG_FDX | \
102 VSC73XX_MAC_CFG_TX_IPG_100_10M | \
103 VSC73XX_MAC_CFG_CLK_SEL_EXT)
104 #define VSC73XX_MAC_CFG_100_10M_H_PHY (VSC73XX_MAC_CFG_TX_IPG_100_10M | \
105 VSC73XX_MAC_CFG_CLK_SEL_EXT)
106 #define VSC73XX_MAC_CFG_1000M_F_RGMII (VSC73XX_MAC_CFG_FDX | \
107 VSC73XX_MAC_CFG_GIGA_MODE | \
108 VSC73XX_MAC_CFG_TX_IPG_1000M | \
109 VSC73XX_MAC_CFG_CLK_SEL_1000M)
110 #define VSC73XX_MAC_CFG_RESET (VSC73XX_MAC_CFG_PORT_RST | \
111 VSC73XX_MAC_CFG_MAC_RX_RST | \
112 VSC73XX_MAC_CFG_MAC_TX_RST)
113
114 /* Flow control register bits */
115 #define VSC73XX_FCCONF_ZERO_PAUSE_EN BIT(17)
116 #define VSC73XX_FCCONF_FLOW_CTRL_OBEY BIT(16)
117 #define VSC73XX_FCCONF_PAUSE_VAL_MASK GENMASK(15, 0)
118
119 /* ADVPORTM advanced port setup register bits */
120 #define VSC73XX_ADVPORTM_IFG_PPM BIT(7)
121 #define VSC73XX_ADVPORTM_EXC_COL_CONT BIT(6)
122 #define VSC73XX_ADVPORTM_EXT_PORT BIT(5)
123 #define VSC73XX_ADVPORTM_INV_GTX BIT(4)
124 #define VSC73XX_ADVPORTM_ENA_GTX BIT(3)
125 #define VSC73XX_ADVPORTM_DDR_MODE BIT(2)
126 #define VSC73XX_ADVPORTM_IO_LOOPBACK BIT(1)
127 #define VSC73XX_ADVPORTM_HOST_LOOPBACK BIT(0)
128
129 /* CAT_DROP categorizer frame dropping register bits */
130 #define VSC73XX_CAT_DROP_DROP_MC_SMAC_ENA BIT(6)
131 #define VSC73XX_CAT_DROP_FWD_CTRL_ENA BIT(4)
132 #define VSC73XX_CAT_DROP_FWD_PAUSE_ENA BIT(3)
133 #define VSC73XX_CAT_DROP_UNTAGGED_ENA BIT(2)
134 #define VSC73XX_CAT_DROP_TAGGED_ENA BIT(1)
135 #define VSC73XX_CAT_DROP_NULL_MAC_ENA BIT(0)
136
137 #define VSC73XX_Q_MISC_CONF_EXTENT_MEM BIT(31)
138 #define VSC73XX_Q_MISC_CONF_EARLY_TX_MASK GENMASK(4, 1)
139 #define VSC73XX_Q_MISC_CONF_EARLY_TX_512 (1 << 1)
140 #define VSC73XX_Q_MISC_CONF_MAC_PAUSE_MODE BIT(0)
141
142 /* Frame analyzer block 2 registers */
143 #define VSC73XX_STORMLIMIT 0x02
144 #define VSC73XX_ADVLEARN 0x03
145 #define VSC73XX_IFLODMSK 0x04
146 #define VSC73XX_VLANMASK 0x05
147 #define VSC73XX_MACHDATA 0x06
148 #define VSC73XX_MACLDATA 0x07
149 #define VSC73XX_ANMOVED 0x08
150 #define VSC73XX_ANAGEFIL 0x09
151 #define VSC73XX_ANEVENTS 0x0a
152 #define VSC73XX_ANCNTMASK 0x0b
153 #define VSC73XX_ANCNTVAL 0x0c
154 #define VSC73XX_LEARNMASK 0x0d
155 #define VSC73XX_UFLODMASK 0x0e
156 #define VSC73XX_MFLODMASK 0x0f
157 #define VSC73XX_RECVMASK 0x10
158 #define VSC73XX_AGGRCTRL 0x20
159 #define VSC73XX_AGGRMSKS 0x30 /* Until 0x3f */
160 #define VSC73XX_DSTMASKS 0x40 /* Until 0x7f */
161 #define VSC73XX_SRCMASKS 0x80 /* Until 0x87 */
162 #define VSC73XX_CAPENAB 0xa0
163 #define VSC73XX_MACACCESS 0xb0
164 #define VSC73XX_IPMCACCESS 0xb1
165 #define VSC73XX_MACTINDX 0xc0
166 #define VSC73XX_VLANACCESS 0xd0
167 #define VSC73XX_VLANTIDX 0xe0
168 #define VSC73XX_AGENCTRL 0xf0
169 #define VSC73XX_CAPRST 0xff
170
171 #define VSC73XX_MACACCESS_CPU_COPY BIT(14)
172 #define VSC73XX_MACACCESS_FWD_KILL BIT(13)
173 #define VSC73XX_MACACCESS_IGNORE_VLAN BIT(12)
174 #define VSC73XX_MACACCESS_AGED_FLAG BIT(11)
175 #define VSC73XX_MACACCESS_VALID BIT(10)
176 #define VSC73XX_MACACCESS_LOCKED BIT(9)
177 #define VSC73XX_MACACCESS_DEST_IDX_MASK GENMASK(8, 3)
178 #define VSC73XX_MACACCESS_CMD_MASK GENMASK(2, 0)
179 #define VSC73XX_MACACCESS_CMD_IDLE 0
180 #define VSC73XX_MACACCESS_CMD_LEARN 1
181 #define VSC73XX_MACACCESS_CMD_FORGET 2
182 #define VSC73XX_MACACCESS_CMD_AGE_TABLE 3
183 #define VSC73XX_MACACCESS_CMD_FLUSH_TABLE 4
184 #define VSC73XX_MACACCESS_CMD_CLEAR_TABLE 5
185 #define VSC73XX_MACACCESS_CMD_READ_ENTRY 6
186 #define VSC73XX_MACACCESS_CMD_WRITE_ENTRY 7
187
188 #define VSC73XX_VLANACCESS_LEARN_DISABLED BIT(30)
189 #define VSC73XX_VLANACCESS_VLAN_MIRROR BIT(29)
190 #define VSC73XX_VLANACCESS_VLAN_SRC_CHECK BIT(28)
191 #define VSC73XX_VLANACCESS_VLAN_PORT_MASK GENMASK(9, 2)
192 #define VSC73XX_VLANACCESS_VLAN_TBL_CMD_MASK GENMASK(2, 0)
193 #define VSC73XX_VLANACCESS_VLAN_TBL_CMD_IDLE 0
194 #define VSC73XX_VLANACCESS_VLAN_TBL_CMD_READ_ENTRY 1
195 #define VSC73XX_VLANACCESS_VLAN_TBL_CMD_WRITE_ENTRY 2
196 #define VSC73XX_VLANACCESS_VLAN_TBL_CMD_CLEAR_TABLE 3
197
198 /* MII block 3 registers */
199 #define VSC73XX_MII_STAT 0x0
200 #define VSC73XX_MII_CMD 0x1
201 #define VSC73XX_MII_DATA 0x2
202
203 /* Arbiter block 5 registers */
204 #define VSC73XX_ARBEMPTY 0x0c
205 #define VSC73XX_ARBDISC 0x0e
206 #define VSC73XX_SBACKWDROP 0x12
207 #define VSC73XX_DBACKWDROP 0x13
208 #define VSC73XX_ARBBURSTPROB 0x15
209
210 /* System block 7 registers */
211 #define VSC73XX_ICPU_SIPAD 0x01
212 #define VSC73XX_GMIIDELAY 0x05
213 #define VSC73XX_ICPU_CTRL 0x10
214 #define VSC73XX_ICPU_ADDR 0x11
215 #define VSC73XX_ICPU_SRAM 0x12
216 #define VSC73XX_HWSEM 0x13
217 #define VSC73XX_GLORESET 0x14
218 #define VSC73XX_ICPU_MBOX_VAL 0x15
219 #define VSC73XX_ICPU_MBOX_SET 0x16
220 #define VSC73XX_ICPU_MBOX_CLR 0x17
221 #define VSC73XX_CHIPID 0x18
222 #define VSC73XX_GPIO 0x34
223
224 #define VSC73XX_GMIIDELAY_GMII0_GTXDELAY_NONE 0
225 #define VSC73XX_GMIIDELAY_GMII0_GTXDELAY_1_4_NS 1
226 #define VSC73XX_GMIIDELAY_GMII0_GTXDELAY_1_7_NS 2
227 #define VSC73XX_GMIIDELAY_GMII0_GTXDELAY_2_0_NS 3
228
229 #define VSC73XX_GMIIDELAY_GMII0_RXDELAY_NONE (0 << 4)
230 #define VSC73XX_GMIIDELAY_GMII0_RXDELAY_1_4_NS (1 << 4)
231 #define VSC73XX_GMIIDELAY_GMII0_RXDELAY_1_7_NS (2 << 4)
232 #define VSC73XX_GMIIDELAY_GMII0_RXDELAY_2_0_NS (3 << 4)
233
234 #define VSC73XX_ICPU_CTRL_WATCHDOG_RST BIT(31)
235 #define VSC73XX_ICPU_CTRL_CLK_DIV_MASK GENMASK(12, 8)
236 #define VSC73XX_ICPU_CTRL_SRST_HOLD BIT(7)
237 #define VSC73XX_ICPU_CTRL_ICPU_PI_EN BIT(6)
238 #define VSC73XX_ICPU_CTRL_BOOT_EN BIT(3)
239 #define VSC73XX_ICPU_CTRL_EXT_ACC_EN BIT(2)
240 #define VSC73XX_ICPU_CTRL_CLK_EN BIT(1)
241 #define VSC73XX_ICPU_CTRL_SRST BIT(0)
242
243 #define VSC73XX_CHIPID_ID_SHIFT 12
244 #define VSC73XX_CHIPID_ID_MASK 0xffff
245 #define VSC73XX_CHIPID_REV_SHIFT 28
246 #define VSC73XX_CHIPID_REV_MASK 0xf
247 #define VSC73XX_CHIPID_ID_7385 0x7385
248 #define VSC73XX_CHIPID_ID_7388 0x7388
249 #define VSC73XX_CHIPID_ID_7395 0x7395
250 #define VSC73XX_CHIPID_ID_7398 0x7398
251
252 #define VSC73XX_GLORESET_STROBE BIT(4)
253 #define VSC73XX_GLORESET_ICPU_LOCK BIT(3)
254 #define VSC73XX_GLORESET_MEM_LOCK BIT(2)
255 #define VSC73XX_GLORESET_PHY_RESET BIT(1)
256 #define VSC73XX_GLORESET_MASTER_RESET BIT(0)
257
258 #define VSC73XX_CMD_MODE_READ 0
259 #define VSC73XX_CMD_MODE_WRITE 1
260 #define VSC73XX_CMD_MODE_SHIFT 4
261 #define VSC73XX_CMD_BLOCK_SHIFT 5
262 #define VSC73XX_CMD_BLOCK_MASK 0x7
263 #define VSC73XX_CMD_SUBBLOCK_MASK 0xf
264
265 #define VSC7385_CLOCK_DELAY ((3 << 4) | 3)
266 #define VSC7385_CLOCK_DELAY_MASK ((3 << 4) | 3)
267
268 #define VSC73XX_ICPU_CTRL_STOP (VSC73XX_ICPU_CTRL_SRST_HOLD | \
269 VSC73XX_ICPU_CTRL_BOOT_EN | \
270 VSC73XX_ICPU_CTRL_EXT_ACC_EN)
271
272 #define VSC73XX_ICPU_CTRL_START (VSC73XX_ICPU_CTRL_CLK_DIV | \
273 VSC73XX_ICPU_CTRL_BOOT_EN | \
274 VSC73XX_ICPU_CTRL_CLK_EN | \
275 VSC73XX_ICPU_CTRL_SRST)
276
277 /**
278 * struct vsc73xx - VSC73xx state container
279 */
280 struct vsc73xx {
281 struct device *dev;
282 struct gpio_desc *reset;
283 struct spi_device *spi;
284 struct dsa_switch *ds;
285 struct gpio_chip gc;
286 u16 chipid;
287 u8 addr[ETH_ALEN];
288 struct mutex lock; /* Protects SPI traffic */
289 };
290
291 #define IS_7385(a) ((a)->chipid == VSC73XX_CHIPID_ID_7385)
292 #define IS_7388(a) ((a)->chipid == VSC73XX_CHIPID_ID_7388)
293 #define IS_7395(a) ((a)->chipid == VSC73XX_CHIPID_ID_7395)
294 #define IS_7398(a) ((a)->chipid == VSC73XX_CHIPID_ID_7398)
295 #define IS_739X(a) (IS_7395(a) || IS_7398(a))
296
297 struct vsc73xx_counter {
298 u8 counter;
299 const char *name;
300 };
301
302 /* Counters are named according to the MIB standards where applicable.
303 * Some counters are custom, non-standard. The standard counters are
304 * named in accordance with RFC2819, RFC2021 and IEEE Std 802.3-2002 Annex
305 * 30A Counters.
306 */
307 static const struct vsc73xx_counter vsc73xx_rx_counters[] = {
308 { 0, "RxEtherStatsPkts" },
309 { 1, "RxBroadcast+MulticastPkts" }, /* non-standard counter */
310 { 2, "RxTotalErrorPackets" }, /* non-standard counter */
311 { 3, "RxEtherStatsBroadcastPkts" },
312 { 4, "RxEtherStatsMulticastPkts" },
313 { 5, "RxEtherStatsPkts64Octets" },
314 { 6, "RxEtherStatsPkts65to127Octets" },
315 { 7, "RxEtherStatsPkts128to255Octets" },
316 { 8, "RxEtherStatsPkts256to511Octets" },
317 { 9, "RxEtherStatsPkts512to1023Octets" },
318 { 10, "RxEtherStatsPkts1024to1518Octets" },
319 { 11, "RxJumboFrames" }, /* non-standard counter */
320 { 12, "RxaPauseMACControlFramesTransmitted" },
321 { 13, "RxFIFODrops" }, /* non-standard counter */
322 { 14, "RxBackwardDrops" }, /* non-standard counter */
323 { 15, "RxClassifierDrops" }, /* non-standard counter */
324 { 16, "RxEtherStatsCRCAlignErrors" },
325 { 17, "RxEtherStatsUndersizePkts" },
326 { 18, "RxEtherStatsOversizePkts" },
327 { 19, "RxEtherStatsFragments" },
328 { 20, "RxEtherStatsJabbers" },
329 { 21, "RxaMACControlFramesReceived" },
330 /* 22-24 are undefined */
331 { 25, "RxaFramesReceivedOK" },
332 { 26, "RxQoSClass0" }, /* non-standard counter */
333 { 27, "RxQoSClass1" }, /* non-standard counter */
334 { 28, "RxQoSClass2" }, /* non-standard counter */
335 { 29, "RxQoSClass3" }, /* non-standard counter */
336 };
337
338 static const struct vsc73xx_counter vsc73xx_tx_counters[] = {
339 { 0, "TxEtherStatsPkts" },
340 { 1, "TxBroadcast+MulticastPkts" }, /* non-standard counter */
341 { 2, "TxTotalErrorPackets" }, /* non-standard counter */
342 { 3, "TxEtherStatsBroadcastPkts" },
343 { 4, "TxEtherStatsMulticastPkts" },
344 { 5, "TxEtherStatsPkts64Octets" },
345 { 6, "TxEtherStatsPkts65to127Octets" },
346 { 7, "TxEtherStatsPkts128to255Octets" },
347 { 8, "TxEtherStatsPkts256to511Octets" },
348 { 9, "TxEtherStatsPkts512to1023Octets" },
349 { 10, "TxEtherStatsPkts1024to1518Octets" },
350 { 11, "TxJumboFrames" }, /* non-standard counter */
351 { 12, "TxaPauseMACControlFramesTransmitted" },
352 { 13, "TxFIFODrops" }, /* non-standard counter */
353 { 14, "TxDrops" }, /* non-standard counter */
354 { 15, "TxEtherStatsCollisions" },
355 { 16, "TxEtherStatsCRCAlignErrors" },
356 { 17, "TxEtherStatsUndersizePkts" },
357 { 18, "TxEtherStatsOversizePkts" },
358 { 19, "TxEtherStatsFragments" },
359 { 20, "TxEtherStatsJabbers" },
360 /* 21-24 are undefined */
361 { 25, "TxaFramesReceivedOK" },
362 { 26, "TxQoSClass0" }, /* non-standard counter */
363 { 27, "TxQoSClass1" }, /* non-standard counter */
364 { 28, "TxQoSClass2" }, /* non-standard counter */
365 { 29, "TxQoSClass3" }, /* non-standard counter */
366 };
367
368 static int vsc73xx_is_addr_valid(u8 block, u8 subblock)
369 {
370 switch (block) {
371 case VSC73XX_BLOCK_MAC:
372 switch (subblock) {
373 case 0 ... 4:
374 case 6:
375 return 1;
376 }
377 break;
378
379 case VSC73XX_BLOCK_ANALYZER:
380 case VSC73XX_BLOCK_SYSTEM:
381 switch (subblock) {
382 case 0:
383 return 1;
384 }
385 break;
386
387 case VSC73XX_BLOCK_MII:
388 case VSC73XX_BLOCK_CAPTURE:
389 case VSC73XX_BLOCK_ARBITER:
390 switch (subblock) {
391 case 0 ... 1:
392 return 1;
393 }
394 break;
395 }
396
397 return 0;
398 }
399
400 static u8 vsc73xx_make_addr(u8 mode, u8 block, u8 subblock)
401 {
402 u8 ret;
403
404 ret = (block & VSC73XX_CMD_BLOCK_MASK) << VSC73XX_CMD_BLOCK_SHIFT;
405 ret |= (mode & 1) << VSC73XX_CMD_MODE_SHIFT;
406 ret |= subblock & VSC73XX_CMD_SUBBLOCK_MASK;
407
408 return ret;
409 }
410
411 static int vsc73xx_read(struct vsc73xx *vsc, u8 block, u8 subblock, u8 reg,
412 u32 *val)
413 {
414 struct spi_transfer t[2];
415 struct spi_message m;
416 u8 cmd[4];
417 u8 buf[4];
418 int ret;
419
420 if (!vsc73xx_is_addr_valid(block, subblock))
421 return -EINVAL;
422
423 spi_message_init(&m);
424
425 memset(&t, 0, sizeof(t));
426
427 t[0].tx_buf = cmd;
428 t[0].len = sizeof(cmd);
429 spi_message_add_tail(&t[0], &m);
430
431 t[1].rx_buf = buf;
432 t[1].len = sizeof(buf);
433 spi_message_add_tail(&t[1], &m);
434
435 cmd[0] = vsc73xx_make_addr(VSC73XX_CMD_MODE_READ, block, subblock);
436 cmd[1] = reg;
437 cmd[2] = 0;
438 cmd[3] = 0;
439
440 mutex_lock(&vsc->lock);
441 ret = spi_sync(vsc->spi, &m);
442 mutex_unlock(&vsc->lock);
443
444 if (ret)
445 return ret;
446
447 *val = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
448
449 return 0;
450 }
451
452 static int vsc73xx_write(struct vsc73xx *vsc, u8 block, u8 subblock, u8 reg,
453 u32 val)
454 {
455 struct spi_transfer t[2];
456 struct spi_message m;
457 u8 cmd[2];
458 u8 buf[4];
459 int ret;
460
461 if (!vsc73xx_is_addr_valid(block, subblock))
462 return -EINVAL;
463
464 spi_message_init(&m);
465
466 memset(&t, 0, sizeof(t));
467
468 t[0].tx_buf = cmd;
469 t[0].len = sizeof(cmd);
470 spi_message_add_tail(&t[0], &m);
471
472 t[1].tx_buf = buf;
473 t[1].len = sizeof(buf);
474 spi_message_add_tail(&t[1], &m);
475
476 cmd[0] = vsc73xx_make_addr(VSC73XX_CMD_MODE_WRITE, block, subblock);
477 cmd[1] = reg;
478
479 buf[0] = (val >> 24) & 0xff;
480 buf[1] = (val >> 16) & 0xff;
481 buf[2] = (val >> 8) & 0xff;
482 buf[3] = val & 0xff;
483
484 mutex_lock(&vsc->lock);
485 ret = spi_sync(vsc->spi, &m);
486 mutex_unlock(&vsc->lock);
487
488 return ret;
489 }
490
491 static int vsc73xx_update_bits(struct vsc73xx *vsc, u8 block, u8 subblock,
492 u8 reg, u32 mask, u32 val)
493 {
494 u32 tmp, orig;
495 int ret;
496
497 /* Same read-modify-write algorithm as e.g. regmap */
498 ret = vsc73xx_read(vsc, block, subblock, reg, &orig);
499 if (ret)
500 return ret;
501 tmp = orig & ~mask;
502 tmp |= val & mask;
503 return vsc73xx_write(vsc, block, subblock, reg, tmp);
504 }
505
506 static int vsc73xx_detect(struct vsc73xx *vsc)
507 {
508 bool icpu_si_boot_en;
509 bool icpu_pi_en;
510 u32 val;
511 u32 rev;
512 int ret;
513 u32 id;
514
515 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_SYSTEM, 0,
516 VSC73XX_ICPU_MBOX_VAL, &val);
517 if (ret) {
518 dev_err(vsc->dev, "unable to read mailbox (%d)\n", ret);
519 return ret;
520 }
521
522 if (val == 0xffffffff) {
523 dev_info(vsc->dev, "chip seems dead, assert reset\n");
524 gpiod_set_value_cansleep(vsc->reset, 1);
525 /* Reset pulse should be 20ns minimum, according to datasheet
526 * table 245, so 10us should be fine
527 */
528 usleep_range(10, 100);
529 gpiod_set_value_cansleep(vsc->reset, 0);
530 /* Wait 20ms according to datasheet table 245 */
531 msleep(20);
532
533 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_SYSTEM, 0,
534 VSC73XX_ICPU_MBOX_VAL, &val);
535 if (val == 0xffffffff) {
536 dev_err(vsc->dev, "seems not to help, giving up\n");
537 return -ENODEV;
538 }
539 }
540
541 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_SYSTEM, 0,
542 VSC73XX_CHIPID, &val);
543 if (ret) {
544 dev_err(vsc->dev, "unable to read chip id (%d)\n", ret);
545 return ret;
546 }
547
548 id = (val >> VSC73XX_CHIPID_ID_SHIFT) &
549 VSC73XX_CHIPID_ID_MASK;
550 switch (id) {
551 case VSC73XX_CHIPID_ID_7385:
552 case VSC73XX_CHIPID_ID_7388:
553 case VSC73XX_CHIPID_ID_7395:
554 case VSC73XX_CHIPID_ID_7398:
555 break;
556 default:
557 dev_err(vsc->dev, "unsupported chip, id=%04x\n", id);
558 return -ENODEV;
559 }
560
561 vsc->chipid = id;
562 rev = (val >> VSC73XX_CHIPID_REV_SHIFT) &
563 VSC73XX_CHIPID_REV_MASK;
564 dev_info(vsc->dev, "VSC%04X (rev: %d) switch found\n", id, rev);
565
566 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_SYSTEM, 0,
567 VSC73XX_ICPU_CTRL, &val);
568 if (ret) {
569 dev_err(vsc->dev, "unable to read iCPU control\n");
570 return ret;
571 }
572
573 /* The iCPU can always be used but can boot in different ways.
574 * If it is initially disabled and has no external memory,
575 * we are in control and can do whatever we like, else we
576 * are probably in trouble (we need some way to communicate
577 * with the running firmware) so we bail out for now.
578 */
579 icpu_pi_en = !!(val & VSC73XX_ICPU_CTRL_ICPU_PI_EN);
580 icpu_si_boot_en = !!(val & VSC73XX_ICPU_CTRL_BOOT_EN);
581 if (icpu_si_boot_en && icpu_pi_en) {
582 dev_err(vsc->dev,
583 "iCPU enabled boots from SI, has external memory\n");
584 dev_err(vsc->dev, "no idea how to deal with this\n");
585 return -ENODEV;
586 }
587 if (icpu_si_boot_en && !icpu_pi_en) {
588 dev_err(vsc->dev,
589 "iCPU enabled boots from SI, no external memory\n");
590 dev_err(vsc->dev, "no idea how to deal with this\n");
591 return -ENODEV;
592 }
593 if (!icpu_si_boot_en && icpu_pi_en) {
594 dev_err(vsc->dev,
595 "iCPU enabled, boots from PI external memory\n");
596 dev_err(vsc->dev, "no idea how to deal with this\n");
597 return -ENODEV;
598 }
599 /* !icpu_si_boot_en && !cpu_pi_en */
600 dev_info(vsc->dev, "iCPU disabled, no external memory\n");
601
602 return 0;
603 }
604
605 static int vsc73xx_phy_read(struct dsa_switch *ds, int phy, int regnum)
606 {
607 struct vsc73xx *vsc = ds->priv;
608 u32 cmd;
609 u32 val;
610 int ret;
611
612 /* Setting bit 26 means "read" */
613 cmd = BIT(26) | (phy << 21) | (regnum << 16);
614 ret = vsc73xx_write(vsc, VSC73XX_BLOCK_MII, 0, 1, cmd);
615 if (ret)
616 return ret;
617 msleep(2);
618 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_MII, 0, 2, &val);
619 if (ret)
620 return ret;
621 if (val & BIT(16)) {
622 dev_err(vsc->dev, "reading reg %02x from phy%d failed\n",
623 regnum, phy);
624 return -EIO;
625 }
626 val &= 0xFFFFU;
627
628 dev_dbg(vsc->dev, "read reg %02x from phy%d = %04x\n",
629 regnum, phy, val);
630
631 return val;
632 }
633
634 static int vsc73xx_phy_write(struct dsa_switch *ds, int phy, int regnum,
635 u16 val)
636 {
637 struct vsc73xx *vsc = ds->priv;
638 u32 cmd;
639 int ret;
640
641 /* It was found through tedious experiments that this router
642 * chip really hates to have it's PHYs reset. They
643 * never recover if that happens: autonegotiation stops
644 * working after a reset. Just filter out this command.
645 * (Resetting the whole chip is OK.)
646 */
647 if (regnum == 0 && (val & BIT(15))) {
648 dev_info(vsc->dev, "reset PHY - disallowed\n");
649 return 0;
650 }
651
652 cmd = (phy << 21) | (regnum << 16);
653 ret = vsc73xx_write(vsc, VSC73XX_BLOCK_MII, 0, 1, cmd);
654 if (ret)
655 return ret;
656
657 dev_dbg(vsc->dev, "write %04x to reg %02x in phy%d\n",
658 val, regnum, phy);
659 return 0;
660 }
661
662 static enum dsa_tag_protocol vsc73xx_get_tag_protocol(struct dsa_switch *ds,
663 int port)
664 {
665 /* The switch internally uses a 8 byte header with length,
666 * source port, tag, LPA and priority. This is supposedly
667 * only accessible when operating the switch using the internal
668 * CPU or with an external CPU mapping the device in, but not
669 * when operating the switch over SPI and putting frames in/out
670 * on port 6 (the CPU port). So far we must assume that we
671 * cannot access the tag. (See "Internal frame header" section
672 * 3.9.1 in the manual.)
673 */
674 return DSA_TAG_PROTO_NONE;
675 }
676
677 static int vsc73xx_setup(struct dsa_switch *ds)
678 {
679 struct vsc73xx *vsc = ds->priv;
680 int i;
681
682 dev_info(vsc->dev, "set up the switch\n");
683
684 /* Issue RESET */
685 vsc73xx_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, VSC73XX_GLORESET,
686 VSC73XX_GLORESET_MASTER_RESET);
687 usleep_range(125, 200);
688
689 /* Initialize memory, initialize RAM bank 0..15 except 6 and 7
690 * This sequence appears in the
691 * VSC7385 SparX-G5 datasheet section 6.6.1
692 * VSC7395 SparX-G5e datasheet section 6.6.1
693 * "initialization sequence".
694 * No explanation is given to the 0x1010400 magic number.
695 */
696 for (i = 0; i <= 15; i++) {
697 if (i != 6 && i != 7) {
698 vsc73xx_write(vsc, VSC73XX_BLOCK_MEMINIT,
699 2,
700 0, 0x1010400 + i);
701 mdelay(1);
702 }
703 }
704 mdelay(30);
705
706 /* Clear MAC table */
707 vsc73xx_write(vsc, VSC73XX_BLOCK_ANALYZER, 0,
708 VSC73XX_MACACCESS,
709 VSC73XX_MACACCESS_CMD_CLEAR_TABLE);
710
711 /* Clear VLAN table */
712 vsc73xx_write(vsc, VSC73XX_BLOCK_ANALYZER, 0,
713 VSC73XX_VLANACCESS,
714 VSC73XX_VLANACCESS_VLAN_TBL_CMD_CLEAR_TABLE);
715
716 msleep(40);
717
718 /* Use 20KiB buffers on all ports on VSC7395
719 * The VSC7385 has 16KiB buffers and that is the
720 * default if we don't set this up explicitly.
721 * Port "31" is "all ports".
722 */
723 if (IS_739X(vsc))
724 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 0x1f,
725 VSC73XX_Q_MISC_CONF,
726 VSC73XX_Q_MISC_CONF_EXTENT_MEM);
727
728 /* Put all ports into reset until enabled */
729 for (i = 0; i < 7; i++) {
730 if (i == 5)
731 continue;
732 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 4,
733 VSC73XX_MAC_CFG, VSC73XX_MAC_CFG_RESET);
734 }
735
736 /* MII delay, set both GTX and RX delay to 2 ns */
737 vsc73xx_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, VSC73XX_GMIIDELAY,
738 VSC73XX_GMIIDELAY_GMII0_GTXDELAY_2_0_NS |
739 VSC73XX_GMIIDELAY_GMII0_RXDELAY_2_0_NS);
740 /* Enable reception of frames on all ports */
741 vsc73xx_write(vsc, VSC73XX_BLOCK_ANALYZER, 0, VSC73XX_RECVMASK,
742 0x5f);
743 /* IP multicast flood mask (table 144) */
744 vsc73xx_write(vsc, VSC73XX_BLOCK_ANALYZER, 0, VSC73XX_IFLODMSK,
745 0xff);
746
747 mdelay(50);
748
749 /* Release reset from the internal PHYs */
750 vsc73xx_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, VSC73XX_GLORESET,
751 VSC73XX_GLORESET_PHY_RESET);
752
753 udelay(4);
754
755 return 0;
756 }
757
758 static void vsc73xx_init_port(struct vsc73xx *vsc, int port)
759 {
760 u32 val;
761
762 /* MAC configure, first reset the port and then write defaults */
763 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC,
764 port,
765 VSC73XX_MAC_CFG,
766 VSC73XX_MAC_CFG_RESET);
767
768 /* Take up the port in 1Gbit mode by default, this will be
769 * augmented after auto-negotiation on the PHY-facing
770 * ports.
771 */
772 if (port == CPU_PORT)
773 val = VSC73XX_MAC_CFG_1000M_F_RGMII;
774 else
775 val = VSC73XX_MAC_CFG_1000M_F_PHY;
776
777 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC,
778 port,
779 VSC73XX_MAC_CFG,
780 val |
781 VSC73XX_MAC_CFG_TX_EN |
782 VSC73XX_MAC_CFG_RX_EN);
783
784 /* Max length, we can do up to 9.6 KiB, so allow that.
785 * According to application not "VSC7398 Jumbo Frames" setting
786 * up the MTU to 9.6 KB does not affect the performance on standard
787 * frames, so just enable it. It is clear from the application note
788 * that "9.6 kilobytes" == 9600 bytes.
789 */
790 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC,
791 port,
792 VSC73XX_MAXLEN, 9600);
793
794 /* Flow control for the CPU port:
795 * Use a zero delay pause frame when pause condition is left
796 * Obey pause control frames
797 */
798 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC,
799 port,
800 VSC73XX_FCCONF,
801 VSC73XX_FCCONF_ZERO_PAUSE_EN |
802 VSC73XX_FCCONF_FLOW_CTRL_OBEY);
803
804 /* Issue pause control frames on PHY facing ports.
805 * Allow early initiation of MAC transmission if the amount
806 * of egress data is below 512 bytes on CPU port.
807 * FIXME: enable 20KiB buffers?
808 */
809 if (port == CPU_PORT)
810 val = VSC73XX_Q_MISC_CONF_EARLY_TX_512;
811 else
812 val = VSC73XX_Q_MISC_CONF_MAC_PAUSE_MODE;
813 val |= VSC73XX_Q_MISC_CONF_EXTENT_MEM;
814 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC,
815 port,
816 VSC73XX_Q_MISC_CONF,
817 val);
818
819 /* Flow control MAC: a MAC address used in flow control frames */
820 val = (vsc->addr[5] << 16) | (vsc->addr[4] << 8) | (vsc->addr[3]);
821 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC,
822 port,
823 VSC73XX_FCMACHI,
824 val);
825 val = (vsc->addr[2] << 16) | (vsc->addr[1] << 8) | (vsc->addr[0]);
826 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC,
827 port,
828 VSC73XX_FCMACLO,
829 val);
830
831 /* Tell the categorizer to forward pause frames, not control
832 * frame. Do not drop anything.
833 */
834 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC,
835 port,
836 VSC73XX_CAT_DROP,
837 VSC73XX_CAT_DROP_FWD_PAUSE_ENA);
838
839 /* Clear all counters */
840 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC,
841 port, VSC73XX_C_RX0, 0);
842 }
843
844 static void vsc73xx_adjust_enable_port(struct vsc73xx *vsc,
845 int port, struct phy_device *phydev,
846 u32 initval)
847 {
848 u32 val = initval;
849 u8 seed;
850
851 /* Reset this port FIXME: break out subroutine */
852 val |= VSC73XX_MAC_CFG_RESET;
853 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, port, VSC73XX_MAC_CFG, val);
854
855 /* Seed the port randomness with randomness */
856 get_random_bytes(&seed, 1);
857 val |= seed << VSC73XX_MAC_CFG_SEED_OFFSET;
858 val |= VSC73XX_MAC_CFG_SEED_LOAD;
859 val |= VSC73XX_MAC_CFG_WEXC_DIS;
860 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, port, VSC73XX_MAC_CFG, val);
861
862 /* Flow control for the PHY facing ports:
863 * Use a zero delay pause frame when pause condition is left
864 * Obey pause control frames
865 * When generating pause frames, use 0xff as pause value
866 */
867 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, port, VSC73XX_FCCONF,
868 VSC73XX_FCCONF_ZERO_PAUSE_EN |
869 VSC73XX_FCCONF_FLOW_CTRL_OBEY |
870 0xff);
871
872 /* Disallow backward dropping of frames from this port */
873 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ARBITER, 0,
874 VSC73XX_SBACKWDROP, BIT(port), 0);
875
876 /* Enable TX, RX, deassert reset, stop loading seed */
877 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_MAC, port,
878 VSC73XX_MAC_CFG,
879 VSC73XX_MAC_CFG_RESET | VSC73XX_MAC_CFG_SEED_LOAD |
880 VSC73XX_MAC_CFG_TX_EN | VSC73XX_MAC_CFG_RX_EN,
881 VSC73XX_MAC_CFG_TX_EN | VSC73XX_MAC_CFG_RX_EN);
882 }
883
884 static void vsc73xx_adjust_link(struct dsa_switch *ds, int port,
885 struct phy_device *phydev)
886 {
887 struct vsc73xx *vsc = ds->priv;
888 u32 val;
889
890 /* Special handling of the CPU-facing port */
891 if (port == CPU_PORT) {
892 /* Other ports are already initialized but not this one */
893 vsc73xx_init_port(vsc, CPU_PORT);
894 /* Select the external port for this interface (EXT_PORT)
895 * Enable the GMII GTX external clock
896 * Use double data rate (DDR mode)
897 */
898 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC,
899 CPU_PORT,
900 VSC73XX_ADVPORTM,
901 VSC73XX_ADVPORTM_EXT_PORT |
902 VSC73XX_ADVPORTM_ENA_GTX |
903 VSC73XX_ADVPORTM_DDR_MODE);
904 }
905
906 /* This is the MAC confiuration that always need to happen
907 * after a PHY or the CPU port comes up or down.
908 */
909 if (!phydev->link) {
910 int maxloop = 10;
911
912 dev_dbg(vsc->dev, "port %d: went down\n",
913 port);
914
915 /* Disable RX on this port */
916 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_MAC, port,
917 VSC73XX_MAC_CFG,
918 VSC73XX_MAC_CFG_RX_EN, 0);
919
920 /* Discard packets */
921 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ARBITER, 0,
922 VSC73XX_ARBDISC, BIT(port), BIT(port));
923
924 /* Wait until queue is empty */
925 vsc73xx_read(vsc, VSC73XX_BLOCK_ARBITER, 0,
926 VSC73XX_ARBEMPTY, &val);
927 while (!(val & BIT(port))) {
928 msleep(1);
929 vsc73xx_read(vsc, VSC73XX_BLOCK_ARBITER, 0,
930 VSC73XX_ARBEMPTY, &val);
931 if (--maxloop == 0) {
932 dev_err(vsc->dev,
933 "timeout waiting for block arbiter\n");
934 /* Continue anyway */
935 break;
936 }
937 }
938
939 /* Put this port into reset */
940 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, port, VSC73XX_MAC_CFG,
941 VSC73XX_MAC_CFG_RESET);
942
943 /* Accept packets again */
944 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ARBITER, 0,
945 VSC73XX_ARBDISC, BIT(port), 0);
946
947 /* Allow backward dropping of frames from this port */
948 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ARBITER, 0,
949 VSC73XX_SBACKWDROP, BIT(port), BIT(port));
950
951 /* Receive mask (disable forwarding) */
952 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0,
953 VSC73XX_RECVMASK, BIT(port), 0);
954
955 return;
956 }
957
958 /* Figure out what speed was negotiated */
959 if (phydev->speed == SPEED_1000) {
960 dev_dbg(vsc->dev, "port %d: 1000 Mbit mode full duplex\n",
961 port);
962
963 /* Set up default for internal port or external RGMII */
964 if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
965 val = VSC73XX_MAC_CFG_1000M_F_RGMII;
966 else
967 val = VSC73XX_MAC_CFG_1000M_F_PHY;
968 vsc73xx_adjust_enable_port(vsc, port, phydev, val);
969 } else if (phydev->speed == SPEED_100) {
970 if (phydev->duplex == DUPLEX_FULL) {
971 val = VSC73XX_MAC_CFG_100_10M_F_PHY;
972 dev_dbg(vsc->dev,
973 "port %d: 100 Mbit full duplex mode\n",
974 port);
975 } else {
976 val = VSC73XX_MAC_CFG_100_10M_H_PHY;
977 dev_dbg(vsc->dev,
978 "port %d: 100 Mbit half duplex mode\n",
979 port);
980 }
981 vsc73xx_adjust_enable_port(vsc, port, phydev, val);
982 } else if (phydev->speed == SPEED_10) {
983 if (phydev->duplex == DUPLEX_FULL) {
984 val = VSC73XX_MAC_CFG_100_10M_F_PHY;
985 dev_dbg(vsc->dev,
986 "port %d: 10 Mbit full duplex mode\n",
987 port);
988 } else {
989 val = VSC73XX_MAC_CFG_100_10M_H_PHY;
990 dev_dbg(vsc->dev,
991 "port %d: 10 Mbit half duplex mode\n",
992 port);
993 }
994 vsc73xx_adjust_enable_port(vsc, port, phydev, val);
995 } else {
996 dev_err(vsc->dev,
997 "could not adjust link: unknown speed\n");
998 }
999
1000 /* Enable port (forwarding) in the receieve mask */
1001 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0,
1002 VSC73XX_RECVMASK, BIT(port), BIT(port));
1003 }
1004
1005 static int vsc73xx_port_enable(struct dsa_switch *ds, int port,
1006 struct phy_device *phy)
1007 {
1008 struct vsc73xx *vsc = ds->priv;
1009
1010 dev_info(vsc->dev, "enable port %d\n", port);
1011 vsc73xx_init_port(vsc, port);
1012
1013 return 0;
1014 }
1015
1016 static void vsc73xx_port_disable(struct dsa_switch *ds, int port)
1017 {
1018 struct vsc73xx *vsc = ds->priv;
1019
1020 /* Just put the port into reset */
1021 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, port,
1022 VSC73XX_MAC_CFG, VSC73XX_MAC_CFG_RESET);
1023 }
1024
1025 static const struct vsc73xx_counter *
1026 vsc73xx_find_counter(struct vsc73xx *vsc,
1027 u8 counter,
1028 bool tx)
1029 {
1030 const struct vsc73xx_counter *cnts;
1031 int num_cnts;
1032 int i;
1033
1034 if (tx) {
1035 cnts = vsc73xx_tx_counters;
1036 num_cnts = ARRAY_SIZE(vsc73xx_tx_counters);
1037 } else {
1038 cnts = vsc73xx_rx_counters;
1039 num_cnts = ARRAY_SIZE(vsc73xx_rx_counters);
1040 }
1041
1042 for (i = 0; i < num_cnts; i++) {
1043 const struct vsc73xx_counter *cnt;
1044
1045 cnt = &cnts[i];
1046 if (cnt->counter == counter)
1047 return cnt;
1048 }
1049
1050 return NULL;
1051 }
1052
1053 static void vsc73xx_get_strings(struct dsa_switch *ds, int port, u32 stringset,
1054 uint8_t *data)
1055 {
1056 const struct vsc73xx_counter *cnt;
1057 struct vsc73xx *vsc = ds->priv;
1058 u8 indices[6];
1059 int i, j;
1060 u32 val;
1061 int ret;
1062
1063 if (stringset != ETH_SS_STATS)
1064 return;
1065
1066 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_MAC, port,
1067 VSC73XX_C_CFG, &val);
1068 if (ret)
1069 return;
1070
1071 indices[0] = (val & 0x1f); /* RX counter 0 */
1072 indices[1] = ((val >> 5) & 0x1f); /* RX counter 1 */
1073 indices[2] = ((val >> 10) & 0x1f); /* RX counter 2 */
1074 indices[3] = ((val >> 16) & 0x1f); /* TX counter 0 */
1075 indices[4] = ((val >> 21) & 0x1f); /* TX counter 1 */
1076 indices[5] = ((val >> 26) & 0x1f); /* TX counter 2 */
1077
1078 /* The first counters is the RX octets */
1079 j = 0;
1080 strncpy(data + j * ETH_GSTRING_LEN,
1081 "RxEtherStatsOctets", ETH_GSTRING_LEN);
1082 j++;
1083
1084 /* Each port supports recording 3 RX counters and 3 TX counters,
1085 * figure out what counters we use in this set-up and return the
1086 * names of them. The hardware default counters will be number of
1087 * packets on RX/TX, combined broadcast+multicast packets RX/TX and
1088 * total error packets RX/TX.
1089 */
1090 for (i = 0; i < 3; i++) {
1091 cnt = vsc73xx_find_counter(vsc, indices[i], false);
1092 if (cnt)
1093 strncpy(data + j * ETH_GSTRING_LEN,
1094 cnt->name, ETH_GSTRING_LEN);
1095 j++;
1096 }
1097
1098 /* TX stats begins with the number of TX octets */
1099 strncpy(data + j * ETH_GSTRING_LEN,
1100 "TxEtherStatsOctets", ETH_GSTRING_LEN);
1101 j++;
1102
1103 for (i = 3; i < 6; i++) {
1104 cnt = vsc73xx_find_counter(vsc, indices[i], true);
1105 if (cnt)
1106 strncpy(data + j * ETH_GSTRING_LEN,
1107 cnt->name, ETH_GSTRING_LEN);
1108 j++;
1109 }
1110 }
1111
1112 static int vsc73xx_get_sset_count(struct dsa_switch *ds, int port, int sset)
1113 {
1114 /* We only support SS_STATS */
1115 if (sset != ETH_SS_STATS)
1116 return 0;
1117 /* RX and TX packets, then 3 RX counters, 3 TX counters */
1118 return 8;
1119 }
1120
1121 static void vsc73xx_get_ethtool_stats(struct dsa_switch *ds, int port,
1122 uint64_t *data)
1123 {
1124 struct vsc73xx *vsc = ds->priv;
1125 u8 regs[] = {
1126 VSC73XX_RXOCT,
1127 VSC73XX_C_RX0,
1128 VSC73XX_C_RX1,
1129 VSC73XX_C_RX2,
1130 VSC73XX_TXOCT,
1131 VSC73XX_C_TX0,
1132 VSC73XX_C_TX1,
1133 VSC73XX_C_TX2,
1134 };
1135 u32 val;
1136 int ret;
1137 int i;
1138
1139 for (i = 0; i < ARRAY_SIZE(regs); i++) {
1140 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_MAC, port,
1141 regs[i], &val);
1142 if (ret) {
1143 dev_err(vsc->dev, "error reading counter %d\n", i);
1144 return;
1145 }
1146 data[i] = val;
1147 }
1148 }
1149
1150 static const struct dsa_switch_ops vsc73xx_ds_ops = {
1151 .get_tag_protocol = vsc73xx_get_tag_protocol,
1152 .setup = vsc73xx_setup,
1153 .phy_read = vsc73xx_phy_read,
1154 .phy_write = vsc73xx_phy_write,
1155 .adjust_link = vsc73xx_adjust_link,
1156 .get_strings = vsc73xx_get_strings,
1157 .get_ethtool_stats = vsc73xx_get_ethtool_stats,
1158 .get_sset_count = vsc73xx_get_sset_count,
1159 .port_enable = vsc73xx_port_enable,
1160 .port_disable = vsc73xx_port_disable,
1161 };
1162
1163 static int vsc73xx_gpio_get(struct gpio_chip *chip, unsigned int offset)
1164 {
1165 struct vsc73xx *vsc = gpiochip_get_data(chip);
1166 u32 val;
1167 int ret;
1168
1169 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_SYSTEM, 0,
1170 VSC73XX_GPIO, &val);
1171 if (ret)
1172 return ret;
1173
1174 return !!(val & BIT(offset));
1175 }
1176
1177 static void vsc73xx_gpio_set(struct gpio_chip *chip, unsigned int offset,
1178 int val)
1179 {
1180 struct vsc73xx *vsc = gpiochip_get_data(chip);
1181 u32 tmp = val ? BIT(offset) : 0;
1182
1183 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_SYSTEM, 0,
1184 VSC73XX_GPIO, BIT(offset), tmp);
1185 }
1186
1187 static int vsc73xx_gpio_direction_output(struct gpio_chip *chip,
1188 unsigned int offset, int val)
1189 {
1190 struct vsc73xx *vsc = gpiochip_get_data(chip);
1191 u32 tmp = val ? BIT(offset) : 0;
1192
1193 return vsc73xx_update_bits(vsc, VSC73XX_BLOCK_SYSTEM, 0,
1194 VSC73XX_GPIO, BIT(offset + 4) | BIT(offset),
1195 BIT(offset + 4) | tmp);
1196 }
1197
1198 static int vsc73xx_gpio_direction_input(struct gpio_chip *chip,
1199 unsigned int offset)
1200 {
1201 struct vsc73xx *vsc = gpiochip_get_data(chip);
1202
1203 return vsc73xx_update_bits(vsc, VSC73XX_BLOCK_SYSTEM, 0,
1204 VSC73XX_GPIO, BIT(offset + 4),
1205 0);
1206 }
1207
1208 static int vsc73xx_gpio_get_direction(struct gpio_chip *chip,
1209 unsigned int offset)
1210 {
1211 struct vsc73xx *vsc = gpiochip_get_data(chip);
1212 u32 val;
1213 int ret;
1214
1215 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_SYSTEM, 0,
1216 VSC73XX_GPIO, &val);
1217 if (ret)
1218 return ret;
1219
1220 return !(val & BIT(offset + 4));
1221 }
1222
1223 static int vsc73xx_gpio_probe(struct vsc73xx *vsc)
1224 {
1225 int ret;
1226
1227 vsc->gc.label = devm_kasprintf(vsc->dev, GFP_KERNEL, "VSC%04x",
1228 vsc->chipid);
1229 vsc->gc.ngpio = 4;
1230 vsc->gc.owner = THIS_MODULE;
1231 vsc->gc.parent = vsc->dev;
1232 vsc->gc.of_node = vsc->dev->of_node;
1233 vsc->gc.base = -1;
1234 vsc->gc.get = vsc73xx_gpio_get;
1235 vsc->gc.set = vsc73xx_gpio_set;
1236 vsc->gc.direction_input = vsc73xx_gpio_direction_input;
1237 vsc->gc.direction_output = vsc73xx_gpio_direction_output;
1238 vsc->gc.get_direction = vsc73xx_gpio_get_direction;
1239 vsc->gc.can_sleep = true;
1240 ret = devm_gpiochip_add_data(vsc->dev, &vsc->gc, vsc);
1241 if (ret) {
1242 dev_err(vsc->dev, "unable to register GPIO chip\n");
1243 return ret;
1244 }
1245 return 0;
1246 }
1247
1248 static int vsc73xx_probe(struct spi_device *spi)
1249 {
1250 struct device *dev = &spi->dev;
1251 struct vsc73xx *vsc;
1252 int ret;
1253
1254 vsc = devm_kzalloc(dev, sizeof(*vsc), GFP_KERNEL);
1255 if (!vsc)
1256 return -ENOMEM;
1257
1258 spi_set_drvdata(spi, vsc);
1259 vsc->spi = spi_dev_get(spi);
1260 vsc->dev = dev;
1261 mutex_init(&vsc->lock);
1262
1263 /* Release reset, if any */
1264 vsc->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
1265 if (IS_ERR(vsc->reset)) {
1266 dev_err(dev, "failed to get RESET GPIO\n");
1267 return PTR_ERR(vsc->reset);
1268 }
1269 if (vsc->reset)
1270 /* Wait 20ms according to datasheet table 245 */
1271 msleep(20);
1272
1273 spi->mode = SPI_MODE_0;
1274 spi->bits_per_word = 8;
1275 ret = spi_setup(spi);
1276 if (ret < 0) {
1277 dev_err(dev, "spi setup failed.\n");
1278 return ret;
1279 }
1280
1281 ret = vsc73xx_detect(vsc);
1282 if (ret) {
1283 dev_err(dev, "no chip found (%d)\n", ret);
1284 return -ENODEV;
1285 }
1286
1287 eth_random_addr(vsc->addr);
1288 dev_info(vsc->dev,
1289 "MAC for control frames: %02X:%02X:%02X:%02X:%02X:%02X\n",
1290 vsc->addr[0], vsc->addr[1], vsc->addr[2],
1291 vsc->addr[3], vsc->addr[4], vsc->addr[5]);
1292
1293 /* The VSC7395 switch chips have 5+1 ports which means 5
1294 * ordinary ports and a sixth CPU port facing the processor
1295 * with an RGMII interface. These ports are numbered 0..4
1296 * and 6, so they leave a "hole" in the port map for port 5,
1297 * which is invalid.
1298 *
1299 * The VSC7398 has 8 ports, port 7 is again the CPU port.
1300 *
1301 * We allocate 8 ports and avoid access to the nonexistant
1302 * ports.
1303 */
1304 vsc->ds = dsa_switch_alloc(dev, 8);
1305 if (!vsc->ds)
1306 return -ENOMEM;
1307 vsc->ds->priv = vsc;
1308
1309 vsc->ds->ops = &vsc73xx_ds_ops;
1310 ret = dsa_register_switch(vsc->ds);
1311 if (ret) {
1312 dev_err(dev, "unable to register switch (%d)\n", ret);
1313 return ret;
1314 }
1315
1316 ret = vsc73xx_gpio_probe(vsc);
1317 if (ret) {
1318 dsa_unregister_switch(vsc->ds);
1319 return ret;
1320 }
1321
1322 return 0;
1323 }
1324
1325 static int vsc73xx_remove(struct spi_device *spi)
1326 {
1327 struct vsc73xx *vsc = spi_get_drvdata(spi);
1328
1329 dsa_unregister_switch(vsc->ds);
1330 gpiod_set_value(vsc->reset, 1);
1331
1332 return 0;
1333 }
1334
1335 static const struct of_device_id vsc73xx_of_match[] = {
1336 {
1337 .compatible = "vitesse,vsc7385",
1338 },
1339 {
1340 .compatible = "vitesse,vsc7388",
1341 },
1342 {
1343 .compatible = "vitesse,vsc7395",
1344 },
1345 {
1346 .compatible = "vitesse,vsc7398",
1347 },
1348 { },
1349 };
1350 MODULE_DEVICE_TABLE(of, vsc73xx_of_match);
1351
1352 static struct spi_driver vsc73xx_driver = {
1353 .probe = vsc73xx_probe,
1354 .remove = vsc73xx_remove,
1355 .driver = {
1356 .name = "vsc73xx",
1357 .of_match_table = vsc73xx_of_match,
1358 },
1359 };
1360 module_spi_driver(vsc73xx_driver);
1361
1362 MODULE_AUTHOR("Linus Walleij <linus.walleij@linaro.org>");
1363 MODULE_DESCRIPTION("Vitesse VSC7385/7388/7395/7398 driver");
1364 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support