drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * RSS and Classifier definitions for Marvell PPv2 Network Controller
   4  *
   5  * Copyright (C) 2014 Marvell
   6  *
   7  * Marcin Wojtas <mw@semihalf.com>
   8  */
   9
  10 #ifndef _MVPP2_CLS_H_
  11 #define _MVPP2_CLS_H_
  12
  13 #include "mvpp2.h"
  14 #include "mvpp2_prs.h"
  15
  16 /* Classifier constants */
  17 #define MVPP2_CLS_FLOWS_TBL_SIZE        512
  18 #define MVPP2_CLS_FLOWS_TBL_DATA_WORDS  3
  19 #define MVPP2_CLS_LKP_TBL_SIZE          64
  20 #define MVPP2_CLS_RX_QUEUES             256
  21
  22 /* Classifier flow constants */
  23
  24 #define MVPP2_FLOW_N_FIELDS             4
  25
  26 enum mvpp2_cls_engine {
  27         MVPP22_CLS_ENGINE_C2 = 1,
  28         MVPP22_CLS_ENGINE_C3A,
  29         MVPP22_CLS_ENGINE_C3B,
  30         MVPP22_CLS_ENGINE_C4,
  31         MVPP22_CLS_ENGINE_C3HA = 6,
  32         MVPP22_CLS_ENGINE_C3HB = 7,
  33 };
  34
  35 #define MVPP22_CLS_HEK_OPT_MAC_DA       BIT(0)
  36 #define MVPP22_CLS_HEK_OPT_VLAN         BIT(1)
  37 #define MVPP22_CLS_HEK_OPT_L3_PROTO     BIT(2)
  38 #define MVPP22_CLS_HEK_OPT_IP4SA        BIT(3)
  39 #define MVPP22_CLS_HEK_OPT_IP4DA        BIT(4)
  40 #define MVPP22_CLS_HEK_OPT_IP6SA        BIT(5)
  41 #define MVPP22_CLS_HEK_OPT_IP6DA        BIT(6)
  42 #define MVPP22_CLS_HEK_OPT_L4SIP        BIT(7)
  43 #define MVPP22_CLS_HEK_OPT_L4DIP        BIT(8)
  44 #define MVPP22_CLS_HEK_N_FIELDS         9
  45
  46 #define MVPP22_CLS_HEK_L4_OPTS  (MVPP22_CLS_HEK_OPT_L4SIP | \
  47                                  MVPP22_CLS_HEK_OPT_L4DIP)
  48
  49 #define MVPP22_CLS_HEK_IP4_2T   (MVPP22_CLS_HEK_OPT_IP4SA | \
  50                                  MVPP22_CLS_HEK_OPT_IP4DA)
  51
  52 #define MVPP22_CLS_HEK_IP6_2T   (MVPP22_CLS_HEK_OPT_IP6SA | \
  53                                  MVPP22_CLS_HEK_OPT_IP6DA)
  54
  55 /* The fifth tuple in "5T" is the L4_Info field */
  56 #define MVPP22_CLS_HEK_IP4_5T   (MVPP22_CLS_HEK_IP4_2T | \
  57                                  MVPP22_CLS_HEK_L4_OPTS)
  58
  59 #define MVPP22_CLS_HEK_IP6_5T   (MVPP22_CLS_HEK_IP6_2T | \
  60                                  MVPP22_CLS_HEK_L4_OPTS)
  61
  62 enum mvpp2_cls_field_id {
  63         MVPP22_CLS_FIELD_MAC_DA = 0x03,
  64         MVPP22_CLS_FIELD_VLAN = 0x06,
  65         MVPP22_CLS_FIELD_L3_PROTO = 0x0f,
  66         MVPP22_CLS_FIELD_IP4SA = 0x10,
  67         MVPP22_CLS_FIELD_IP4DA = 0x11,
  68         MVPP22_CLS_FIELD_IP6SA = 0x17,
  69         MVPP22_CLS_FIELD_IP6DA = 0x1a,
  70         MVPP22_CLS_FIELD_L4SIP = 0x1d,
  71         MVPP22_CLS_FIELD_L4DIP = 0x1e,
  72 };
  73
  74 enum mvpp2_cls_flow_seq {
  75         MVPP2_CLS_FLOW_SEQ_NORMAL = 0,
  76         MVPP2_CLS_FLOW_SEQ_FIRST1,
  77         MVPP2_CLS_FLOW_SEQ_FIRST2,
  78         MVPP2_CLS_FLOW_SEQ_LAST,
  79         MVPP2_CLS_FLOW_SEQ_MIDDLE
  80 };
  81
  82 /* Classifier C2 engine constants */
  83 #define MVPP22_CLS_C2_TCAM_EN(data)             ((data) << 16)
  84
  85 enum mvpp22_cls_c2_action {
  86         MVPP22_C2_NO_UPD = 0,
  87         MVPP22_C2_NO_UPD_LOCK,
  88         MVPP22_C2_UPD,
  89         MVPP22_C2_UPD_LOCK,
  90 };
  91
  92 enum mvpp22_cls_c2_fwd_action {
  93         MVPP22_C2_FWD_NO_UPD = 0,
  94         MVPP22_C2_FWD_NO_UPD_LOCK,
  95         MVPP22_C2_FWD_SW,
  96         MVPP22_C2_FWD_SW_LOCK,
  97         MVPP22_C2_FWD_HW,
  98         MVPP22_C2_FWD_HW_LOCK,
  99         MVPP22_C2_FWD_HW_LOW_LAT,
 100         MVPP22_C2_FWD_HW_LOW_LAT_LOCK,
 101 };
 102
 103 #define MVPP2_CLS_C2_TCAM_WORDS                 5
 104 #define MVPP2_CLS_C2_ATTR_WORDS                 5
 105
 106 struct mvpp2_cls_c2_entry {
 107         u32 index;
 108         u32 tcam[MVPP2_CLS_C2_TCAM_WORDS];
 109         u32 act;
 110         u32 attr[MVPP2_CLS_C2_ATTR_WORDS];
 111 };
 112
 113 /* Classifier C2 engine entries */
 114 #define MVPP22_CLS_C2_RSS_ENTRY(port)   (port)
 115 #define MVPP22_CLS_C2_N_ENTRIES         MVPP2_MAX_PORTS
 116
 117 /* RSS flow entries in the flow table. We have 2 entries per port for RSS.
 118  *
 119  * The first performs a lookup using the C2 TCAM engine, to tag the
 120  * packet for software forwarding (needed for RSS), enable or disable RSS, and
 121  * assign the default rx queue.
 122  *
 123  * The second configures the hash generation, by specifying which fields of the
 124  * packet header are used to generate the hash, and specifies the relevant hash
 125  * engine to use.
 126  */
 127 #define MVPP22_RSS_FLOW_C2_OFFS         0
 128 #define MVPP22_RSS_FLOW_HASH_OFFS       1
 129 #define MVPP22_RSS_FLOW_SIZE            (MVPP22_RSS_FLOW_HASH_OFFS + 1)
 130
 131 #define MVPP22_RSS_FLOW_C2(port)        ((port) * MVPP22_RSS_FLOW_SIZE + \
 132                                          MVPP22_RSS_FLOW_C2_OFFS)
 133 #define MVPP22_RSS_FLOW_HASH(port)      ((port) * MVPP22_RSS_FLOW_SIZE + \
 134                                          MVPP22_RSS_FLOW_HASH_OFFS)
 135 #define MVPP22_RSS_FLOW_FIRST(port)     MVPP22_RSS_FLOW_C2(port)
 136
 137 /* Packet flow ID */
 138 enum mvpp2_prs_flow {
 139         MVPP2_FL_START = 8,
 140         MVPP2_FL_IP4_TCP_NF_UNTAG = MVPP2_FL_START,
 141         MVPP2_FL_IP4_UDP_NF_UNTAG,
 142         MVPP2_FL_IP4_TCP_NF_TAG,
 143         MVPP2_FL_IP4_UDP_NF_TAG,
 144         MVPP2_FL_IP6_TCP_NF_UNTAG,
 145         MVPP2_FL_IP6_UDP_NF_UNTAG,
 146         MVPP2_FL_IP6_TCP_NF_TAG,
 147         MVPP2_FL_IP6_UDP_NF_TAG,
 148         MVPP2_FL_IP4_TCP_FRAG_UNTAG,
 149         MVPP2_FL_IP4_UDP_FRAG_UNTAG,
 150         MVPP2_FL_IP4_TCP_FRAG_TAG,
 151         MVPP2_FL_IP4_UDP_FRAG_TAG,
 152         MVPP2_FL_IP6_TCP_FRAG_UNTAG,
 153         MVPP2_FL_IP6_UDP_FRAG_UNTAG,
 154         MVPP2_FL_IP6_TCP_FRAG_TAG,
 155         MVPP2_FL_IP6_UDP_FRAG_TAG,
 156         MVPP2_FL_IP4_UNTAG, /* non-TCP, non-UDP, same for below */
 157         MVPP2_FL_IP4_TAG,
 158         MVPP2_FL_IP6_UNTAG,
 159         MVPP2_FL_IP6_TAG,
 160         MVPP2_FL_NON_IP_UNTAG,
 161         MVPP2_FL_NON_IP_TAG,
 162         MVPP2_FL_LAST,
 163 };
 164
 165 struct mvpp2_cls_flow {
 166         /* The L2-L4 traffic flow type */
 167         int flow_type;
 168
 169         /* The first id in the flow table for this flow */
 170         u16 flow_id;
 171
 172         /* The supported HEK fields for this flow */
 173         u16 supported_hash_opts;
 174
 175         /* The Header Parser result_info that matches this flow */
 176         struct mvpp2_prs_result_info prs_ri;
 177 };
 178
 179 #define MVPP2_N_FLOWS   52
 180
 181 #define MVPP2_ENTRIES_PER_FLOW                  (MVPP2_MAX_PORTS + 1)
 182 #define MVPP2_FLOW_C2_ENTRY(id)                 ((id) * MVPP2_ENTRIES_PER_FLOW)
 183 #define MVPP2_PORT_FLOW_HASH_ENTRY(port, id)    ((id) * MVPP2_ENTRIES_PER_FLOW + \
 184                                                 (port) + 1)
 185 struct mvpp2_cls_flow_entry {
 186         u32 index;
 187         u32 data[MVPP2_CLS_FLOWS_TBL_DATA_WORDS];
 188 };
 189
 190 struct mvpp2_cls_lookup_entry {
 191         u32 lkpid;
 192         u32 way;
 193         u32 data;
 194 };
 195
 196 void mvpp22_rss_fill_table(struct mvpp2_port *port, u32 table);
 197
 198 void mvpp22_rss_port_init(struct mvpp2_port *port);
 199
 200 void mvpp22_rss_enable(struct mvpp2_port *port);
 201 void mvpp22_rss_disable(struct mvpp2_port *port);
 202
 203 int mvpp2_ethtool_rxfh_get(struct mvpp2_port *port, struct ethtool_rxnfc *info);
 204 int mvpp2_ethtool_rxfh_set(struct mvpp2_port *port, struct ethtool_rxnfc *info);
 205
 206 void mvpp2_cls_init(struct mvpp2 *priv);
 207
 208 void mvpp2_cls_port_config(struct mvpp2_port *port);
 209
 210 void mvpp2_cls_oversize_rxq_set(struct mvpp2_port *port);
 211
 212 int mvpp2_cls_flow_eng_get(struct mvpp2_cls_flow_entry *fe);
 213
 214 u16 mvpp2_flow_get_hek_fields(struct mvpp2_cls_flow_entry *fe);
 215
 216 struct mvpp2_cls_flow *mvpp2_cls_flow_get(int flow);
 217
 218 u32 mvpp2_cls_flow_hits(struct mvpp2 *priv, int index);
 219
 220 void mvpp2_cls_flow_read(struct mvpp2 *priv, int index,
 221                          struct mvpp2_cls_flow_entry *fe);
 222
 223 u32 mvpp2_cls_lookup_hits(struct mvpp2 *priv, int index);
 224
 225 void mvpp2_cls_lookup_read(struct mvpp2 *priv, int lkpid, int way,
 226                            struct mvpp2_cls_lookup_entry *le);
 227
 228 u32 mvpp2_cls_c2_hit_count(struct mvpp2 *priv, int c2_index);
 229
 230 void mvpp2_cls_c2_read(struct mvpp2 *priv, int index,
 231                        struct mvpp2_cls_c2_entry *c2);
 232
 233 #endif