drivers/net/ethernet/mscc/ocelot_board.c

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /*
   3  * Microsemi Ocelot Switch driver
   4  *
   5  * Copyright (c) 2017 Microsemi Corporation
   6  */
   7 #include <linux/interrupt.h>
   8 #include <linux/module.h>
   9 #include <linux/of_net.h>
  10 #include <linux/netdevice.h>
  11 #include <linux/of_mdio.h>
  12 #include <linux/of_platform.h>
  13 #include <linux/mfd/syscon.h>
  14 #include <linux/skbuff.h>
  15 #include <net/switchdev.h>
  16
  17 #include "ocelot.h"
  18
  19 static int ocelot_parse_ifh(u32 *ifh, struct frame_info *info)
  20 {
  21         int i;
  22         u8 llen, wlen;
  23
  24         /* The IFH is in network order, switch to CPU order */
  25         for (i = 0; i < IFH_LEN; i++)
  26                 ifh[i] = ntohl((__force __be32)ifh[i]);
  27
  28         wlen = (ifh[1] >> 7) & 0xff;
  29         llen = (ifh[1] >> 15) & 0x3f;
  30         info->len = OCELOT_BUFFER_CELL_SZ * wlen + llen - 80;
  31
  32         info->port = (ifh[2] & GENMASK(14, 11)) >> 11;
  33
  34         info->cpuq = (ifh[3] & GENMASK(27, 20)) >> 20;
  35         info->tag_type = (ifh[3] & BIT(16)) >> 16;
  36         info->vid = ifh[3] & GENMASK(11, 0);
  37
  38         return 0;
  39 }
  40
  41 static int ocelot_rx_frame_word(struct ocelot *ocelot, u8 grp, bool ifh,
  42                                 u32 *rval)
  43 {
  44         u32 val;
  45         u32 bytes_valid;
  46
  47         val = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
  48         if (val == XTR_NOT_READY) {
  49                 if (ifh)
  50                         return -EIO;
  51
  52                 do {
  53                         val = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
  54                 } while (val == XTR_NOT_READY);
  55         }
  56
  57         switch (val) {
  58         case XTR_ABORT:
  59                 return -EIO;
  60         case XTR_EOF_0:
  61         case XTR_EOF_1:
  62         case XTR_EOF_2:
  63         case XTR_EOF_3:
  64         case XTR_PRUNED:
  65                 bytes_valid = XTR_VALID_BYTES(val);
  66                 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
  67                 if (val == XTR_ESCAPE)
  68                         *rval = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
  69                 else
  70                         *rval = val;
  71
  72                 return bytes_valid;
  73         case XTR_ESCAPE:
  74                 *rval = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
  75
  76                 return 4;
  77         default:
  78                 *rval = val;
  79
  80                 return 4;
  81         }
  82 }
  83
  84 static irqreturn_t ocelot_xtr_irq_handler(int irq, void *arg)
  85 {
  86         struct ocelot *ocelot = arg;
  87         int i = 0, grp = 0;
  88         int err = 0;
  89
  90         if (!(ocelot_read(ocelot, QS_XTR_DATA_PRESENT) & BIT(grp)))
  91                 return IRQ_NONE;
  92
  93         do {
  94                 struct sk_buff *skb;
  95                 struct net_device *dev;
  96                 u32 *buf;
  97                 int sz, len, buf_len;
  98                 u32 ifh[4];
  99                 u32 val;
 100                 struct frame_info info;
 101
 102                 for (i = 0; i < IFH_LEN; i++) {
 103                         err = ocelot_rx_frame_word(ocelot, grp, true, &ifh[i]);
 104                         if (err != 4)
 105                                 break;
 106                 }
 107
 108                 if (err != 4)
 109                         break;
 110
 111                 ocelot_parse_ifh(ifh, &info);
 112
 113                 dev = ocelot->ports[info.port]->dev;
 114
 115                 skb = netdev_alloc_skb(dev, info.len);
 116
 117                 if (unlikely(!skb)) {
 118                         netdev_err(dev, "Unable to allocate sk_buff\n");
 119                         err = -ENOMEM;
 120                         break;
 121                 }
 122                 buf_len = info.len - ETH_FCS_LEN;
 123                 buf = (u32 *)skb_put(skb, buf_len);
 124
 125                 len = 0;
 126                 do {
 127                         sz = ocelot_rx_frame_word(ocelot, grp, false, &val);
 128                         *buf++ = val;
 129                         len += sz;
 130                 } while (len < buf_len);
 131
 132                 /* Read the FCS */
 133                 sz = ocelot_rx_frame_word(ocelot, grp, false, &val);
 134                 /* Update the statistics if part of the FCS was read before */
 135                 len -= ETH_FCS_LEN - sz;
 136
 137                 if (unlikely(dev->features & NETIF_F_RXFCS)) {
 138                         buf = (u32 *)skb_put(skb, ETH_FCS_LEN);
 139                         *buf = val;
 140                 }
 141
 142                 if (sz < 0) {
 143                         err = sz;
 144                         break;
 145                 }
 146
 147                 /* Everything we see on an interface that is in the HW bridge
 148                  * has already been forwarded.
 149                  */
 150                 if (ocelot->bridge_mask & BIT(info.port))
 151                         skb->offload_fwd_mark = 1;
 152
 153                 skb->protocol = eth_type_trans(skb, dev);
 154                 netif_rx(skb);
 155                 dev->stats.rx_bytes += len;
 156                 dev->stats.rx_packets++;
 157         } while (ocelot_read(ocelot, QS_XTR_DATA_PRESENT) & BIT(grp));
 158
 159         if (err)
 160                 while (ocelot_read(ocelot, QS_XTR_DATA_PRESENT) & BIT(grp))
 161                         ocelot_read_rix(ocelot, QS_XTR_RD, grp);
 162
 163         return IRQ_HANDLED;
 164 }
 165
 166 static const struct of_device_id mscc_ocelot_match[] = {
 167         { .compatible = "mscc,vsc7514-switch" },
 168         { }
 169 };
 170 MODULE_DEVICE_TABLE(of, mscc_ocelot_match);
 171
 172 static int mscc_ocelot_probe(struct platform_device *pdev)
 173 {
 174         int err, irq;
 175         unsigned int i;
 176         struct device_node *np = pdev->dev.of_node;
 177         struct device_node *ports, *portnp;
 178         struct ocelot *ocelot;
 179         struct regmap *hsio;
 180         u32 val;
 181
 182         struct {
 183                 enum ocelot_target id;
 184                 char *name;
 185         } res[] = {
 186                 { SYS, "sys" },
 187                 { REW, "rew" },
 188                 { QSYS, "qsys" },
 189                 { ANA, "ana" },
 190                 { QS, "qs" },
 191         };
 192
 193         if (!np && !pdev->dev.platform_data)
 194                 return -ENODEV;
 195
 196         ocelot = devm_kzalloc(&pdev->dev, sizeof(*ocelot), GFP_KERNEL);
 197         if (!ocelot)
 198                 return -ENOMEM;
 199
 200         platform_set_drvdata(pdev, ocelot);
 201         ocelot->dev = &pdev->dev;
 202
 203         for (i = 0; i < ARRAY_SIZE(res); i++) {
 204                 struct regmap *target;
 205
 206                 target = ocelot_io_platform_init(ocelot, pdev, res[i].name);
 207                 if (IS_ERR(target))
 208                         return PTR_ERR(target);
 209
 210                 ocelot->targets[res[i].id] = target;
 211         }
 212
 213         hsio = syscon_regmap_lookup_by_compatible("mscc,ocelot-hsio");
 214         if (IS_ERR(hsio)) {
 215                 dev_err(&pdev->dev, "missing hsio syscon\n");
 216                 return PTR_ERR(hsio);
 217         }
 218
 219         ocelot->targets[HSIO] = hsio;
 220
 221         err = ocelot_chip_init(ocelot);
 222         if (err)
 223                 return err;
 224
 225         irq = platform_get_irq_byname(pdev, "xtr");
 226         if (irq < 0)
 227                 return -ENODEV;
 228
 229         err = devm_request_threaded_irq(&pdev->dev, irq, NULL,
 230                                         ocelot_xtr_irq_handler, IRQF_ONESHOT,
 231                                         "frame extraction", ocelot);
 232         if (err)
 233                 return err;
 234
 235         regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_INIT], 1);
 236         regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_ENA], 1);
 237
 238         do {
 239                 msleep(1);
 240                 regmap_field_read(ocelot->regfields[SYS_RESET_CFG_MEM_INIT],
 241                                   &val);
 242         } while (val);
 243
 244         regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_ENA], 1);
 245         regmap_field_write(ocelot->regfields[SYS_RESET_CFG_CORE_ENA], 1);
 246
 247         ocelot->num_cpu_ports = 1; /* 1 port on the switch, two groups */
 248
 249         ports = of_get_child_by_name(np, "ethernet-ports");
 250         if (!ports) {
 251                 dev_err(&pdev->dev, "no ethernet-ports child node found\n");
 252                 return -ENODEV;
 253         }
 254
 255         ocelot->num_phys_ports = of_get_child_count(ports);
 256
 257         ocelot->ports = devm_kcalloc(&pdev->dev, ocelot->num_phys_ports,
 258                                      sizeof(struct ocelot_port *), GFP_KERNEL);
 259
 260         INIT_LIST_HEAD(&ocelot->multicast);
 261         ocelot_init(ocelot);
 262
 263         for_each_available_child_of_node(ports, portnp) {
 264                 struct device_node *phy_node;
 265                 struct phy_device *phy;
 266                 struct resource *res;
 267                 struct phy *serdes;
 268                 void __iomem *regs;
 269                 char res_name[8];
 270                 int phy_mode;
 271                 u32 port;
 272
 273                 if (of_property_read_u32(portnp, "reg", &port))
 274                         continue;
 275
 276                 snprintf(res_name, sizeof(res_name), "port%d", port);
 277
 278                 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
 279                                                    res_name);
 280                 regs = devm_ioremap_resource(&pdev->dev, res);
 281                 if (IS_ERR(regs))
 282                         continue;
 283
 284                 phy_node = of_parse_phandle(portnp, "phy-handle", 0);
 285                 if (!phy_node)
 286                         continue;
 287
 288                 phy = of_phy_find_device(phy_node);
 289                 if (!phy)
 290                         continue;
 291
 292                 err = ocelot_probe_port(ocelot, port, regs, phy);
 293                 if (err)
 294                         return err;
 295
 296                 phy_mode = of_get_phy_mode(portnp);
 297                 if (phy_mode < 0)
 298                         ocelot->ports[port]->phy_mode = PHY_INTERFACE_MODE_NA;
 299                 else
 300                         ocelot->ports[port]->phy_mode = phy_mode;
 301
 302                 switch (ocelot->ports[port]->phy_mode) {
 303                 case PHY_INTERFACE_MODE_NA:
 304                         continue;
 305                 case PHY_INTERFACE_MODE_SGMII:
 306                         break;
 307                 case PHY_INTERFACE_MODE_QSGMII:
 308                         /* Ensure clock signals and speed is set on all
 309                          * QSGMII links
 310                          */
 311                         ocelot_port_writel(ocelot->ports[port],
 312                                            DEV_CLOCK_CFG_LINK_SPEED
 313                                            (OCELOT_SPEED_1000),
 314                                            DEV_CLOCK_CFG);
 315                         break;
 316                 default:
 317                         dev_err(ocelot->dev,
 318                                 "invalid phy mode for port%d, (Q)SGMII only\n",
 319                                 port);
 320                         return -EINVAL;
 321                 }
 322
 323                 serdes = devm_of_phy_get(ocelot->dev, portnp, NULL);
 324                 if (IS_ERR(serdes)) {
 325                         err = PTR_ERR(serdes);
 326                         if (err == -EPROBE_DEFER)
 327                                 dev_dbg(ocelot->dev, "deferring probe\n");
 328                         else
 329                                 dev_err(ocelot->dev,
 330                                         "missing SerDes phys for port%d\n",
 331                                         port);
 332
 333                         goto err_probe_ports;
 334                 }
 335
 336                 ocelot->ports[port]->serdes = serdes;
 337         }
 338
 339         register_netdevice_notifier(&ocelot_netdevice_nb);
 340         register_switchdev_notifier(&ocelot_switchdev_nb);
 341         register_switchdev_blocking_notifier(&ocelot_switchdev_blocking_nb);
 342
 343         dev_info(&pdev->dev, "Ocelot switch probed\n");
 344
 345         return 0;
 346
 347 err_probe_ports:
 348         return err;
 349 }
 350
 351 static int mscc_ocelot_remove(struct platform_device *pdev)
 352 {
 353         struct ocelot *ocelot = platform_get_drvdata(pdev);
 354
 355         ocelot_deinit(ocelot);
 356         unregister_switchdev_blocking_notifier(&ocelot_switchdev_blocking_nb);
 357         unregister_switchdev_notifier(&ocelot_switchdev_nb);
 358         unregister_netdevice_notifier(&ocelot_netdevice_nb);
 359
 360         return 0;
 361 }
 362
 363 static struct platform_driver mscc_ocelot_driver = {
 364         .probe = mscc_ocelot_probe,
 365         .remove = mscc_ocelot_remove,
 366         .driver = {
 367                 .name = "ocelot-switch",
 368                 .of_match_table = mscc_ocelot_match,
 369         },
 370 };
 371
 372 module_platform_driver(mscc_ocelot_driver);
 373
 374 MODULE_DESCRIPTION("Microsemi Ocelot switch driver");
 375 MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@bootlin.com>");
 376 MODULE_LICENSE("Dual MIT/GPL");