drivers/net/phy/mdio-bcm-unimac.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Broadcom UniMAC MDIO bus controller driver
   4  *
   5  * Copyright (C) 2014-2017 Broadcom
   6  */
   7
   8 #include <linux/kernel.h>
   9 #include <linux/phy.h>
  10 #include <linux/platform_device.h>
  11 #include <linux/sched.h>
  12 #include <linux/module.h>
  13 #include <linux/io.h>
  14 #include <linux/delay.h>
  15 #include <linux/clk.h>
  16
  17 #include <linux/of.h>
  18 #include <linux/of_platform.h>
  19 #include <linux/of_mdio.h>
  20
  21 #include <linux/platform_data/mdio-bcm-unimac.h>
  22
  23 #define MDIO_CMD                0x00
  24 #define  MDIO_START_BUSY        (1 << 29)
  25 #define  MDIO_READ_FAIL         (1 << 28)
  26 #define  MDIO_RD                (2 << 26)
  27 #define  MDIO_WR                (1 << 26)
  28 #define  MDIO_PMD_SHIFT         21
  29 #define  MDIO_PMD_MASK          0x1F
  30 #define  MDIO_REG_SHIFT         16
  31 #define  MDIO_REG_MASK          0x1F
  32
  33 #define MDIO_CFG                0x04
  34 #define  MDIO_C22               (1 << 0)
  35 #define  MDIO_C45               0
  36 #define  MDIO_CLK_DIV_SHIFT     4
  37 #define  MDIO_CLK_DIV_MASK      0x3F
  38 #define  MDIO_SUPP_PREAMBLE     (1 << 12)
  39
  40 struct unimac_mdio_priv {
  41         struct mii_bus          *mii_bus;
  42         void __iomem            *base;
  43         int (*wait_func)        (void *wait_func_data);
  44         void                    *wait_func_data;
  45         struct clk              *clk;
  46         u32                     clk_freq;
  47 };
  48
  49 static inline u32 unimac_mdio_readl(struct unimac_mdio_priv *priv, u32 offset)
  50 {
  51         /* MIPS chips strapped for BE will automagically configure the
  52          * peripheral registers for CPU-native byte order.
  53          */
  54         if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
  55                 return __raw_readl(priv->base + offset);
  56         else
  57                 return readl_relaxed(priv->base + offset);
  58 }
  59
  60 static inline void unimac_mdio_writel(struct unimac_mdio_priv *priv, u32 val,
  61                                       u32 offset)
  62 {
  63         if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
  64                 __raw_writel(val, priv->base + offset);
  65         else
  66                 writel_relaxed(val, priv->base + offset);
  67 }
  68
  69 static inline void unimac_mdio_start(struct unimac_mdio_priv *priv)
  70 {
  71         u32 reg;
  72
  73         reg = unimac_mdio_readl(priv, MDIO_CMD);
  74         reg |= MDIO_START_BUSY;
  75         unimac_mdio_writel(priv, reg, MDIO_CMD);
  76 }
  77
  78 static inline unsigned int unimac_mdio_busy(struct unimac_mdio_priv *priv)
  79 {
  80         return unimac_mdio_readl(priv, MDIO_CMD) & MDIO_START_BUSY;
  81 }
  82
  83 static int unimac_mdio_poll(void *wait_func_data)
  84 {
  85         struct unimac_mdio_priv *priv = wait_func_data;
  86         unsigned int timeout = 1000;
  87
  88         do {
  89                 if (!unimac_mdio_busy(priv))
  90                         return 0;
  91
  92                 usleep_range(1000, 2000);
  93         } while (--timeout);
  94
  95         if (!timeout)
  96                 return -ETIMEDOUT;
  97
  98         return 0;
  99 }
 100
 101 static int unimac_mdio_read(struct mii_bus *bus, int phy_id, int reg)
 102 {
 103         struct unimac_mdio_priv *priv = bus->priv;
 104         int ret;
 105         u32 cmd;
 106
 107         /* Prepare the read operation */
 108         cmd = MDIO_RD | (phy_id << MDIO_PMD_SHIFT) | (reg << MDIO_REG_SHIFT);
 109         unimac_mdio_writel(priv, cmd, MDIO_CMD);
 110
 111         /* Start MDIO transaction */
 112         unimac_mdio_start(priv);
 113
 114         ret = priv->wait_func(priv->wait_func_data);
 115         if (ret)
 116                 return ret;
 117
 118         cmd = unimac_mdio_readl(priv, MDIO_CMD);
 119
 120         /* Some broken devices are known not to release the line during
 121          * turn-around, e.g: Broadcom BCM53125 external switches, so check for
 122          * that condition here and ignore the MDIO controller read failure
 123          * indication.
 124          */
 125         if (!(bus->phy_ignore_ta_mask & 1 << phy_id) && (cmd & MDIO_READ_FAIL))
 126                 return -EIO;
 127
 128         return cmd & 0xffff;
 129 }
 130
 131 static int unimac_mdio_write(struct mii_bus *bus, int phy_id,
 132                              int reg, u16 val)
 133 {
 134         struct unimac_mdio_priv *priv = bus->priv;
 135         u32 cmd;
 136
 137         /* Prepare the write operation */
 138         cmd = MDIO_WR | (phy_id << MDIO_PMD_SHIFT) |
 139                 (reg << MDIO_REG_SHIFT) | (0xffff & val);
 140         unimac_mdio_writel(priv, cmd, MDIO_CMD);
 141
 142         unimac_mdio_start(priv);
 143
 144         return priv->wait_func(priv->wait_func_data);
 145 }
 146
 147 /* Workaround for integrated BCM7xxx Gigabit PHYs which have a problem with
 148  * their internal MDIO management controller making them fail to successfully
 149  * be read from or written to for the first transaction.  We insert a dummy
 150  * BMSR read here to make sure that phy_get_device() and get_phy_id() can
 151  * correctly read the PHY MII_PHYSID1/2 registers and successfully register a
 152  * PHY device for this peripheral.
 153  *
 154  * Once the PHY driver is registered, we can workaround subsequent reads from
 155  * there (e.g: during system-wide power management).
 156  *
 157  * bus->reset is invoked before mdiobus_scan during mdiobus_register and is
 158  * therefore the right location to stick that workaround. Since we do not want
 159  * to read from non-existing PHYs, we either use bus->phy_mask or do a manual
 160  * Device Tree scan to limit the search area.
 161  */
 162 static int unimac_mdio_reset(struct mii_bus *bus)
 163 {
 164         struct device_node *np = bus->dev.of_node;
 165         struct device_node *child;
 166         u32 read_mask = 0;
 167         int addr;
 168
 169         if (!np) {
 170                 read_mask = ~bus->phy_mask;
 171         } else {
 172                 for_each_available_child_of_node(np, child) {
 173                         addr = of_mdio_parse_addr(&bus->dev, child);
 174                         if (addr < 0)
 175                                 continue;
 176
 177                         read_mask |= 1 << addr;
 178                 }
 179         }
 180
 181         for (addr = 0; addr < PHY_MAX_ADDR; addr++) {
 182                 if (read_mask & 1 << addr) {
 183                         dev_dbg(&bus->dev, "Workaround for PHY @ %d\n", addr);
 184                         mdiobus_read(bus, addr, MII_BMSR);
 185                 }
 186         }
 187
 188         return 0;
 189 }
 190
 191 static void unimac_mdio_clk_set(struct unimac_mdio_priv *priv)
 192 {
 193         unsigned long rate;
 194         u32 reg, div;
 195
 196         /* Keep the hardware default values */
 197         if (!priv->clk_freq)
 198                 return;
 199
 200         if (!priv->clk)
 201                 rate = 250000000;
 202         else
 203                 rate = clk_get_rate(priv->clk);
 204
 205         div = (rate / (2 * priv->clk_freq)) - 1;
 206         if (div & ~MDIO_CLK_DIV_MASK) {
 207                 pr_warn("Incorrect MDIO clock frequency, ignoring\n");
 208                 return;
 209         }
 210
 211         /* The MDIO clock is the reference clock (typicaly 250Mhz) divided by
 212          * 2 x (MDIO_CLK_DIV + 1)
 213          */
 214         reg = unimac_mdio_readl(priv, MDIO_CFG);
 215         reg &= ~(MDIO_CLK_DIV_MASK << MDIO_CLK_DIV_SHIFT);
 216         reg |= div << MDIO_CLK_DIV_SHIFT;
 217         unimac_mdio_writel(priv, reg, MDIO_CFG);
 218 }
 219
 220 static int unimac_mdio_probe(struct platform_device *pdev)
 221 {
 222         struct unimac_mdio_pdata *pdata = pdev->dev.platform_data;
 223         struct unimac_mdio_priv *priv;
 224         struct device_node *np;
 225         struct mii_bus *bus;
 226         struct resource *r;
 227         int ret;
 228
 229         np = pdev->dev.of_node;
 230
 231         priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
 232         if (!priv)
 233                 return -ENOMEM;
 234
 235         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 236         if (!r)
 237                 return -EINVAL;
 238
 239         /* Just ioremap, as this MDIO block is usually integrated into an
 240          * Ethernet MAC controller register range
 241          */
 242         priv->base = devm_ioremap(&pdev->dev, r->start, resource_size(r));
 243         if (!priv->base) {
 244                 dev_err(&pdev->dev, "failed to remap register\n");
 245                 return -ENOMEM;
 246         }
 247
 248         priv->clk = devm_clk_get(&pdev->dev, NULL);
 249         if (PTR_ERR(priv->clk) == -EPROBE_DEFER)
 250                 return PTR_ERR(priv->clk);
 251         else
 252                 priv->clk = NULL;
 253
 254         ret = clk_prepare_enable(priv->clk);
 255         if (ret)
 256                 return ret;
 257
 258         if (of_property_read_u32(np, "clock-frequency", &priv->clk_freq))
 259                 priv->clk_freq = 0;
 260
 261         unimac_mdio_clk_set(priv);
 262
 263         priv->mii_bus = mdiobus_alloc();
 264         if (!priv->mii_bus) {
 265                 ret = -ENOMEM;
 266                 goto out_clk_disable;
 267         }
 268
 269         bus = priv->mii_bus;
 270         bus->priv = priv;
 271         if (pdata) {
 272                 bus->name = pdata->bus_name;
 273                 priv->wait_func = pdata->wait_func;
 274                 priv->wait_func_data = pdata->wait_func_data;
 275                 bus->phy_mask = ~pdata->phy_mask;
 276         } else {
 277                 bus->name = "unimac MII bus";
 278                 priv->wait_func_data = priv;
 279                 priv->wait_func = unimac_mdio_poll;
 280         }
 281         bus->parent = &pdev->dev;
 282         bus->read = unimac_mdio_read;
 283         bus->write = unimac_mdio_write;
 284         bus->reset = unimac_mdio_reset;
 285         snprintf(bus->id, MII_BUS_ID_SIZE, "%s-%d", pdev->name, pdev->id);
 286
 287         ret = of_mdiobus_register(bus, np);
 288         if (ret) {
 289                 dev_err(&pdev->dev, "MDIO bus registration failed\n");
 290                 goto out_mdio_free;
 291         }
 292
 293         platform_set_drvdata(pdev, priv);
 294
 295         dev_info(&pdev->dev, "Broadcom UniMAC MDIO bus at 0x%p\n", priv->base);
 296
 297         return 0;
 298
 299 out_mdio_free:
 300         mdiobus_free(bus);
 301 out_clk_disable:
 302         clk_disable_unprepare(priv->clk);
 303         return ret;
 304 }
 305
 306 static int unimac_mdio_remove(struct platform_device *pdev)
 307 {
 308         struct unimac_mdio_priv *priv = platform_get_drvdata(pdev);
 309
 310         mdiobus_unregister(priv->mii_bus);
 311         mdiobus_free(priv->mii_bus);
 312         clk_disable_unprepare(priv->clk);
 313
 314         return 0;
 315 }
 316
 317 static int __maybe_unused unimac_mdio_suspend(struct device *d)
 318 {
 319         struct unimac_mdio_priv *priv = dev_get_drvdata(d);
 320
 321         clk_disable_unprepare(priv->clk);
 322
 323         return 0;
 324 }
 325
 326 static int __maybe_unused unimac_mdio_resume(struct device *d)
 327 {
 328         struct unimac_mdio_priv *priv = dev_get_drvdata(d);
 329         int ret;
 330
 331         ret = clk_prepare_enable(priv->clk);
 332         if (ret)
 333                 return ret;
 334
 335         unimac_mdio_clk_set(priv);
 336
 337         return 0;
 338 }
 339
 340 static SIMPLE_DEV_PM_OPS(unimac_mdio_pm_ops,
 341                          unimac_mdio_suspend, unimac_mdio_resume);
 342
 343 static const struct of_device_id unimac_mdio_ids[] = {
 344         { .compatible = "brcm,genet-mdio-v5", },
 345         { .compatible = "brcm,genet-mdio-v4", },
 346         { .compatible = "brcm,genet-mdio-v3", },
 347         { .compatible = "brcm,genet-mdio-v2", },
 348         { .compatible = "brcm,genet-mdio-v1", },
 349         { .compatible = "brcm,unimac-mdio", },
 350         { /* sentinel */ },
 351 };
 352 MODULE_DEVICE_TABLE(of, unimac_mdio_ids);
 353
 354 static struct platform_driver unimac_mdio_driver = {
 355         .driver = {
 356                 .name = UNIMAC_MDIO_DRV_NAME,
 357                 .of_match_table = unimac_mdio_ids,
 358                 .pm = &unimac_mdio_pm_ops,
 359         },
 360         .probe  = unimac_mdio_probe,
 361         .remove = unimac_mdio_remove,
 362 };
 363 module_platform_driver(unimac_mdio_driver);
 364
 365 MODULE_AUTHOR("Broadcom Corporation");
 366 MODULE_DESCRIPTION("Broadcom UniMAC MDIO bus controller");
 367 MODULE_LICENSE("GPL");
 368 MODULE_ALIAS("platform:" UNIMAC_MDIO_DRV_NAME);